CN115211032A - Signal strength detector - Google Patents

Signal strength detector Download PDF

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Publication number
CN115211032A
CN115211032A CN202080097753.2A CN202080097753A CN115211032A CN 115211032 A CN115211032 A CN 115211032A CN 202080097753 A CN202080097753 A CN 202080097753A CN 115211032 A CN115211032 A CN 115211032A
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Prior art keywords
signal
stage
capacitor
differential
output
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Chinese (zh)
Inventor
徐杰
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/01—Arrangements for measuring electric power or power factor in circuits having distributed constants
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
    • H03F3/505—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45542—Indexing scheme relating to differential amplifiers the IC comprising bias stabilisation means, e.g. DC level stabilisation, and temperature coefficient dependent control, e.g. by DC level shifting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45628—Indexing scheme relating to differential amplifiers the LC comprising bias stabilisation means, e.g. DC level stabilisation means, and temperature coefficient dependent control, e.g. DC level shifting means

Abstract

The present disclosure relates to techniques for signal strength detection. An apparatus for detecting signal strength is disclosed. The apparatus includes a differential sensor stage having an input and an output; a differential reference stage having an input and an output; a capacitor stage configured to couple an input signal to an input of the differential sensor stage; a bias circuit configured to bias the differential sensor stage and the differential reference stage. The device has a differential output between the output of the differential sensor stage and the output of the differential reference stage. The differential output is configured to provide a signal indicative of the strength of the input signal.

Description

Signal strength detector
Technical Field
The present disclosure relates generally to detecting signal (e.g., radio Frequency (RF) signal) strength.
Background
Signal power detectors are widely used to detect the power level of a signal. For example, signal power detectors may be used in communication systems, radar systems, and measurement instruments. The signal power detector may generate a voltage signal indicative of the input signal power. For example, the RF power detector may generate a voltage signal indicative of the RF signal power. RF power detectors may be used in wireless RF communication systems to monitor the power of RF signals transmitted by an RF transmitter and/or the power of RF signals received by an RF receiver.
The accuracy of the signal power detector may be affected by factors such as process variations and operating temperature. The process variation refers to a process for manufacturing the signal power detector. For example, there may be mismatches in transistors, capacitors, resistors, or other electronic components, which may result in inaccurate determinations of signal power levels.
Variations in operating temperature can also affect the accuracy of the signal power detector. For example, for some conventional signal power detectors, the output voltage for a given signal power level may be temperature dependent. Thus, some conventional signal power detectors may not produce accurate results over the operating temperature range. In many cases, signal power detectors are used in environments where the operating temperature varies widely, for example, the signal power detector may be located near an electronic component that generates a large amount of heat.
Disclosure of Invention
According to one aspect of the present disclosure, an apparatus for detecting signal strength is provided. The apparatus includes a differential sensor stage having an input and an output; a differential reference stage having an input and an output; a capacitor stage configured to couple an input signal to an input of the differential sensor stage; a bias circuit configured to bias the differential sensor stage and the differential reference stage; and a differential output between the output of the differential sensor stage and the output of the differential reference stage. The differential output is configured to provide a signal indicative of the input signal strength.
Optionally, in any preceding aspect, the bias circuit is configured to bias the differential sensor stage and the differential reference stage in a weak inversion region.
Optionally, in any preceding aspect, the bias circuit is configured to apply substantially the same bias conditions to the differential sensor stage and the differential reference stage.
Optionally, in any preceding aspect, the capacitor stage is configured to maintain the differential sensor stage operating in the weak inversion region.
Optionally, in any preceding aspect, the capacitor stage is configured to maintain an input signal at an input of the differential sensor stage within a target range to maintain the differential sensor stage operating in the weak inversion region.
Optionally, in any preceding aspect, the capacitor stage comprises an H-type capacitor bridge.
Optionally, in any preceding aspect, the H-type capacitor bridge comprises: a first capacitor having a first terminal and a second terminal; a second capacitor having a first terminal and a second terminal, the first terminals of the first and second capacitors configured to receive the input signal; a third capacitor having a first terminal connected to the second terminal of the first capacitor, the third capacitor having a second terminal connected to the first terminal of the input of the differential sensor stage; a fourth capacitor having a first terminal connected to the second terminal of the second capacitor, the fourth capacitor having a second terminal connected to the second terminal of the input of the differential sensor stage; and a fifth capacitor having a first terminal connected to the second terminal of the first capacitor and the first terminal of the third capacitor, the fifth capacitor having a second terminal connected to the second terminal of the second capacitor and the first terminal of the fourth capacitor.
Optionally, in any preceding aspect, the first capacitor and the second capacitor have substantially the same capacitance.
Optionally, in any preceding aspect, the third capacitor and the fourth capacitor have substantially the same capacitance.
Optionally, in any preceding aspect, the differential sensor stage comprises a first transistor and a second transistor having a source follower configuration. The differential reference stage includes a third transistor and a fourth transistor having a source follower configuration.
Optionally, in any preceding aspect, the differential sensor stage comprises a first MOSFET transistor and a second MOSFET transistor having a source follower configuration. The differential reference stage includes a third MOSFET transistor and a fourth MOSFET transistor having a source follower configuration.
Optionally, in any preceding aspect, the differential sensor stage comprises a first loading block coupled to an output of the differential sensor stage. The differential reference stage includes a second load block coupled to an output of the differential reference stage.
Optionally, in any preceding aspect, the first loading block comprises a first resistor. The second load block includes a second resistor. The first resistor and the second resistor have substantially the same resistance.
Optionally, in any preceding aspect, the second load block is configured to provide temperature compensation to the circuit.
Optionally, in any preceding aspect, the second loading block is configured to maintain the signal at the differential output within a target range independent of temperature.
Optionally, in any preceding aspect, the second loading block further comprises a Proportional To Absolute Temperature (PTAT) current source in parallel with the second resistor.
Optionally, in any preceding aspect, the first loading block further comprises a capacitor in parallel with the first resistor.
Optionally, in any preceding aspect, the first load block comprises a passive load block. The second load block comprises an active load block.
Optionally, in any preceding aspect, the first load block is configured to provide temperature compensation.
Optionally, in any preceding aspect, the first loading block is configured to maintain the signal at the differential output within a target range independent of temperature.
Optionally, in any preceding aspect, the first loading block further comprises a current source in inverse absolute temperature (CTAT) in parallel with the first resistor.
Optionally, in any preceding aspect, the first load block comprises an active load block. The second load block comprises a passive load block.
Optionally, in any preceding aspect, the input signal is based on a Radio Frequency (RF) signal.
Optionally, in any preceding aspect, the apparatus further comprises an RF transmitter configured to generate the RF signal. The apparatus also includes an antenna coupled to the RF transmitter and configured to transmit the RF signal. The strength of the input signal is proportional to the power of the transmitted RF signal.
Optionally, in any preceding aspect, the apparatus further comprises an RF receiver configured to generate the RF signal. The apparatus also includes an antenna coupled to the RF receiver and configured to receive the RF signal. The strength of the input signal is proportional to the power of the received RF signal.
Optionally, in any preceding aspect, the intensity comprises a peak voltage of the input signal.
Optionally, in any preceding aspect, the intensity corresponds to a peak power of the input signal.
Another aspect includes a method for detecting signal strength. The method includes biasing a differential sensor stage having an input and an output. The method includes biasing a differential reference stage having an input and an output. The method includes coupling an input signal to an input of the differential sensor stage using a capacitor stage. The method includes providing a signal indicative of the input signal strength at a differential output between the output of the differential sensor stage and the output of the differential reference stage.
Another aspect includes a wireless communication device. The wireless communication device includes a transceiver configured to receive and transmit Radio Frequency (RF) signals; a differential sensor stage having an input and an output; a differential reference stage having an input and an output; a capacitor stage coupled to the transceiver and configured to couple a voltage signal based on an RF signal to an input of the differential sensor stage; a bias circuit configured to bias the differential sensor stage and the differential reference stage; and a differential output between the output of the differential sensor stage and the output of the differential reference stage. The differential output is configured to provide a signal indicative of a power of the RF signal.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the background.
Drawings
Aspects of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate elements.
Fig. 1 illustrates a wireless network for transmitting data.
Fig. 2 shows example details of a User Equipment (UE) that may implement methods and teachings in accordance with the present disclosure.
Fig. 3 illustrates an example Base Station (BS) that may implement methods and teachings in accordance with this disclosure.
Fig. 4 depicts an apparatus configured to detect input signal strength.
FIG. 5 depicts one embodiment of an apparatus configured to detect input signal strength.
Fig. 6 is a circuit schematic of one embodiment of a signal power detector.
Fig. 7 is a circuit schematic of one embodiment of a signal power detector.
FIG. 8 depicts a flow diagram of one embodiment of a process of detecting input signal power.
FIG. 9 depicts a flowchart of one embodiment of a process of operating a differential stage of a signal power detector in a weak inversion region.
FIG. 10 depicts a flow diagram of one embodiment of a process for providing temperature compensation in a signal power detector.
Fig. 11 depicts the relationship between signal power and voltage of a MOSFET in an embodiment of a signal power detector.
FIG. 12 depicts a flow diagram of one embodiment of a process for adjusting the sensitivity of an RF receiver based on the detected power level of an RF signal received by the RF receiver.
FIG. 13 depicts a flow diagram of one embodiment of a process for adjusting the gain of an RF transmitter based on the detected power level of an RF signal transmitted by the RF transmitter.
Detailed Description
The present disclosure will now be described with reference to the accompanying drawings, which generally relate to an apparatus and method for detecting signal strength. The signal strength may be a power level, a voltage level, but is not limited thereto. The device can detect the signal intensity with high precision. In some embodiments, the apparatus compensates for process variations. For example, there may be some structural differences between transistors. In some embodiments, the device compensates for operating temperature variations.
It should be understood that the present embodiments of the disclosure may be embodied in many different forms and that the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the embodiments of the invention to those skilled in the art. Indeed, the present disclosure is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be apparent to one of ordinary skill in the art that the present embodiments of the disclosure may be practiced without these specific details.
The signal power detector may be used in a wireless network for transmitting data, but is not limited to a wireless network. Fig. 1 illustrates a wireless network for transmitting data. The communication system 100 includes, for example, user equipment 110A, 110B, and 110C, radio Access Networks (RANs) 120A and 120B, a core network 130, a Public Switched Telephone Network (PSTN) 140, the internet 150, and other networks 160. Additional or alternative networks include private and public data packet networks, including corporate intranets. Although some number of these components or elements are shown, any number of these components or elements may be included in the system 100. Some embodiments of the signal power detector are implemented in the UE 110. Some embodiments of the signal power detector are implemented in the RAN 120. The signal power detector may be used elsewhere in the communication system 100.
In one embodiment, the wireless network may be a 5G network including at least one fifth generation (5G) base station, the 5G base station communicating with the communication device using Orthogonal Frequency Division Multiplexing (OFDM) and/or non-OFDM and Transmission Time Interval (TTI) shorter than 1ms (e.g., 100 or 200 microseconds). In general, a base station may also be used to refer to any one of an eNB and a 5G BS (gNB). Further, the network may also include a network server for processing information received from the communication device via at least one eNB or gNB.
System 100 enables multiple wireless users to send and receive data and other content. System 100 may implement one or more channel access methods such as, but not limited to, code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), frequency Division Multiple Access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).
User Equipment (UE) 110A, 110B, and 110C may be referred to individually as UE 110 or collectively as UE 110, and are configured to operate and/or communicate in system 100. For example, UE 110 may be configured to transmit and/or receive wireless signals or wired signals. Each UE 110 represents any suitable end-user device and may include devices (or may be referred to as), for example, user equipment/equipment, a wireless transmit/receive Unit (UE), a mobile station, a fixed or mobile subscriber unit, a pager, a cellular telephone, a Personal Digital Assistant (PDA), a smartphone, a laptop, a computer, a touchpad, a wireless sensor, a wearable device, or a consumer electronics device.
In the depicted embodiment, the RANs 120A, 120B include one or more Base Stations (BSs) 170A, 170B, respectively. The RANs 120A and 120B may be referred to individually as the RANs 120, or collectively as the RANs 120. Similarly, base Stations (BSs) 170A and 170B may be referred to individually as Base Stations (BSs) 170 or collectively as Base Stations (BSs) 170. Each BS 170 is configured to wirelessly connect with one or more UEs 110 to enable access to core network 130, PSTN 140, internet 150, and/or other networks 160. For example, the Base Station (BS) 170 may include one or more of several well-known devices, such as a Base Transceiver Station (BTS), a node B (NodeB), an evolved node B (eNB), a next generation (fifth) generation (5G) NodeB (gNB), a home node B, a home eNodeB, a site controller, an Access Point (AP), or a wireless router, or a server, a router, a switch, or other processing entity with a wired or wireless network.
In one embodiment, the BS 170A forms a portion of the RAN 120A, and the RAN 120A may include one or more other BSs 170, elements, and/or devices. Similarly, the BS 170B forms a part of the RAN 120B, and the RAN 120B may include one or more other BSs 170, elements, and/or devices. Each BS 170 operates within a particular geographic area or region (sometimes referred to as a "cell") to transmit and/or receive wireless signals, and in some embodiments may employ multiple-input multiple-output (MIMO) technology, with multiple transceivers per cell.
BS 170 communicates with one or more UEs 110 over one or more air interfaces (not shown) using a wireless communication link. The air interface may utilize any suitable radio access technology.
It is contemplated that system 100 may use multi-channel access functionality including, for example, schemes in which BS 170 and UE 110 are configured to implement Long Term Evolution wireless communication standard (LTE), LTE-Advanced (LTE-a), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base station 170 and the user equipment 110A-110C are configured to implement UMTS, HSPA or HSPA + standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.
RAN 120 communicates with core network 130 to provide Voice, data, applications, voice over Internet Protocol (VoIP), or other services to UE 110. As is understood, the RAN 120 and/or the core network 130 may communicate directly or indirectly with one or more other RANs (not shown). Core network 130 may also serve as a gateway access for other networks, such as PSTN 140, internet 150, and other networks 160. Further, some or all of UEs 110 may include functionality to communicate with different wireless networks over different wireless links using different wireless technologies and/or protocols.
The RAN 120 may also include millimeter and/or microwave Access Points (APs). The AP may be part of BS 170 or may be remote from BS 170. The AP may include, but is not limited to, a connection point (mmW CP) or a BS 170 (e.g., mmW base station) capable of mmW communication. mmW APs may transmit and receive signals in a frequency range, for example, from 24GHz to 100GHz, but need not operate over the entire range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.
Although fig. 1 shows one example of a communication system, various changes may be made to fig. 1. For example, communication system 100 may include any number of user devices, base stations, networks, or other components in any suitable configuration. It should also be understood that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target equipment, device-to-device (D2D) user equipment, machine type user equipment or machine-to-machine (M2M) communication capable user equipment, laptop, PDA, iPad, tablet, mobile terminal, smartphone, laptop Embedded Equipment (LEE), laptop Mounted Equipment (LME), and USB dongle.
Fig. 2 shows example details of a UE 110 that may implement methods and teachings in accordance with the present disclosure. The UE 110 may be, for example, a mobile phone, but in further examples may be other devices, such as a desktop computer, laptop computer, tablet computer, handheld computing device, automotive computing device, and/or other computing devices. As shown, the exemplary UE 110 is shown to include at least one transmitter 202, at least one receiver 204, memory 206, at least one processor 208, and at least one input/output device 212. Processor 208 may perform various processing operations for UE 110. For example, processor 208 may perform signal coding, data processing, power control, input/output processing, or any other functionality that enables UE 110 to operate in system 100 (fig. 1). Processor 208 may include any suitable processing or computing device configured to perform one or more operations. For example, the processor 208 may include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit. In one embodiment, memory 206 is a non-transitory memory storage.
The transmitter 202 may be configured to modulate data or other content for transmission by at least one antenna 210. The transmitter 202 may also be configured to amplify, filter, and frequency convert the RF signals before providing them to the antenna 210 for transmission. Transmitter 202 may include any suitable structure for generating a wireless transmission signal. In some embodiments, a signal power detector is used to detect the power level of the signal generated by the transmitter 202. In some embodiments, the signal power detector output includes a DC voltage indicative of the power of the signal (e.g., RF signal). The DC voltage may be indicative of the power of the signal output by the transmitter 202, or the power of the wireless RF signal transmitted by the antenna 210.
The receiver 204 may be configured to demodulate data or other content received by the at least one antenna 210. The receiver 204 may also be configured to amplify, filter, and frequency convert RF signals received via the antenna 210. In some embodiments, receiver 204 is an RF signal receiver. Receiver 204 may include any suitable structure for processing wirelessly received signals. Antenna 210 may include any suitable structure for transmitting and/or receiving wireless signals. The same antenna 210 may be used for transmitting and receiving RF signals, or different antennas 210 may be used for transmitting and receiving signals. In some embodiments, a signal power detector is used to detect the power level of the signal received by the antenna. In some embodiments, the signal power detector output includes a DC voltage indicative of the power of the signal (e.g., RF signal) received by the antenna.
It should be understood that one or more transmitters 202 may be used in UE 110, one or more receivers 204 may be used in UE 110, and one or more antennas 210 may be used in UE 110. Although shown as separate blocks or components, the at least one transmitter 202 and the at least one receiver 204 may be combined into a transceiver. Thus, in fig. 2, separate blocks of the transmitter 202 and of the receiver 204 are not shown, but rather separate blocks of the transceiver are shown.
UE 110 also includes one or more input/output devices 212. The input/output devices 212 facilitate interaction with a user. Each input/output device 212 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.
Further, UE 110 includes at least one memory 206. Memory 206 stores instructions and data used, generated, or collected by UE 110. For example, the memory 206 may store software or firmware instructions executed by the processor 208 and data for reducing or eliminating interference in the input signal. Each memory 206 includes any suitable volatile and/or non-volatile storage and retrieval device. Any suitable type of memory may be used, such as Random Access Memory (RAM), read Only Memory (ROM), hard disk, optical disk, subscriber Identity Module (SIM) card, memory stick, secure Digital (SD) memory card, and so forth.
Fig. 3 illustrates an example BS 170 in which methods and teachings according to this disclosure may be implemented. As shown, BS 170 includes at least one processor 308, at least one transmitter 302, at least one receiver 304, one or more antennas 310, and at least one memory 306. Processor 308 performs various processing operations for BS 170 such as signal coding, data processing, power control, input/output processing, or any other function. Each processor 308 comprises any suitable processing or computing device configured to perform one or more operations. Each processor 308 may comprise, for example, a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit. In one embodiment, memory 306 is a non-transitory memory storage.
Each transmitter 302 includes any suitable structure for generating signals for wireless transmission to one or more UEs 110 or other devices. Each receiver 304 includes any suitable structure for processing signals wirelessly received from one or more UEs 110 or other devices. Although shown as separate blocks or components, the at least one transmitter 302 and the at least one receiver 304 may be combined into a transceiver. Each antenna 310 includes any suitable structure for transmitting and/or receiving wireless signals. Although a common antenna 310 is shown here as being coupled to both the transmitter 302 and the receiver 304, one or more antennas 310 may be coupled to the transmitter 302 and one or more individual antennas 310 may be coupled to the receiver 304. Each memory 306 includes any suitable volatile and/or non-volatile storage and retrieval device.
In some embodiments, the base station 170 includes a signal power detector configured to detect a power level of a signal transmitted by the transmitter 302. In some embodiments, the base station 170 includes a signal power detector configured to detect a power level of a signal received by the receiver 304. In some embodiments, the signal power detector outputs a DC voltage indicative of the power level of the RF signal (which may be received or transmitted by the base station 170).
Fig. 4 depicts an apparatus 400 configured to detect input signal strength. For example, the apparatus 400 may detect a power level or a voltage level of an input signal of the capacitor stage 402. In some cases, it is desirable to determine the power level of an RF signal (e.g., a wireless RF signal). In this case, the input signal in fig. 4 is not necessarily a wireless RF signal. Instead, the input signal may be a voltage signal whose magnitude is proportional to the power of the wireless RF signal. To compare the magnitude of the voltage signal to the power of the RF signal, the voltage signal may be associated with a resistance. In one embodiment, the relationship between the power of the input signal and the RF signal is given by:
P＝A*V 2 [ equation 1 ]
In equation 1, P is the power of the RF signal, V is the voltage of the input signal, R is the resistance associated with the input signal, and a is a scaling factor, which may be determined empirically. Thus, based on the strength of the input signal, the power of the wireless RF signal may be determined.
In one embodiment, the input signal in FIG. 4 is an RF signal (although wireless RF signals are not required). The apparatus 400 may be used in a system 100, but is not limited to a communication system. In one embodiment, apparatus 400 is used in a UE 110 (e.g., a wireless communication device). The apparatus 400 may be used in other devices such as the RAN 120. In one embodiment, the apparatus 400 is used to detect a power level of an RF signal received by a wireless communication device. In one embodiment, the apparatus 400 is used to detect a power level of an RF signal transmitted by a wireless communication device. The term "input signal" is used because a signal is input into the apparatus 400. However, this does not mean that the signal has to be input to, for example, a wireless communication device. For example, the input signal may come from a transmitter in the wireless communication device.
The apparatus includes a capacitor stage 402, a differential sensor stage 404, a differential reference stage 406, and a bias circuit 408. In some embodiments, the differential sensor stage 404 and the differential reference stage 406 operate in the weak inversion region. A weak inversion system is a system in which the transistor operates in a weak inversion region (e.g., a gate-source voltage that is lower than a desired threshold voltage). Operating the transistors in the weak inversion region may make the device 400 less sensitive to structural differences between the transistors. Such structural differences may be due to process limitations in fabricating transistors. Therefore, operating the transistor in the weak inversion region may reduce inaccuracies due to such structural differences. One possible equation describing the weak inversion region is given by equation 2.
Figure BDA0003821279900000081
In equation 2, I ds Is the drain to source current, I s Is a characteristic current, V, defining the current leaking through the transistor gs Is the gate-to-source voltage, V th Is the threshold voltage of the transistor, n is the sub-threshold slope factor, V t Is the thermal voltage (kT/q). When V is gs Is less than or equal to V th Equation 1 applies. Note that while equation 1 represents one possible way to describe weak inversion regions, other equations may be used. For example, other equations may add additional factors.
The biasing circuit 408 is configured to bias the differential sensor stage 404 and the differential reference stage 406. In one embodiment, the bias circuit 408 is configured to bias the differential sensor stage 404 and the differential reference stage 406 in a weak inversion region. The bias circuit 408 provides voltages to a bias input 416 of the differential sensor stage 404 and a bias input 418 of the differential reference stage 406.
The capacitor stage 402 is configured to couple an input signal to the differential sensor stage 404. The capacitor stage 402 has an input 410 configured to receive an input signal. Note that the input signal may be provided by, for example, the transmitter 202 or the receiver 204 (see fig. 2). Such signals need not be wireless signals (e.g., RF signals received or transmitted by antenna 210). In some embodiments, the apparatus 400 detects a power level of the input signal, which may be related to, for example, a power level of an RF signal received or transmitted by the antenna 210.
The capacitor stage 402 has an output 412 connected to a signal input 414 of the differential sensor stage 404. Note that the signal input 414 may overlap, in whole or in part, the bias input 416. For example, the signal input 414 and the bias input 416 may both comprise gate terminals of MOS transistors.
In one embodiment, the capacitor stage 402 is configured to maintain the strength of the input signal at the input of the differential sensor stage 404 within a target range, which in turn maintains the transistors (in the differential sensor stage 404) in the weak inversion region. In one embodiment, the target range is a target voltage range. Thus, in some embodiments, the capacitor stage 402 helps to overcome structural differences in transistors due to, for example, process variations. Thus, the capacitor stage 402 may improve the accuracy of the apparatus 400 in signal strength detection.
The differential sensor stage 404 has an output 420. The differential reference stage 406 has an output 422. The voltage between these two outputs 420, 422 serves as a differential output for the apparatus 400. In some embodiments, the DC voltage between these two outputs 420, 422 is used as a differential output of the apparatus 400. In one embodiment, the voltage (e.g., DC voltage) between the outputs 420, 422 is indicative of the strength of the input signal. In some cases, the strength of an input signal may be proportional to the power of another signal (e.g., a wireless RF signal), as described in equation 1. In one embodiment, the apparatus 400 is configured as a peak power detector. For example, the apparatus 400 may detect a peak power of the RF signal.
Fig. 5 depicts one embodiment of an apparatus 500 configured to detect the strength (e.g., voltage level, power level) of an input signal. The input signal may be based on an RF signal. The apparatus 500 may be used, for example, to detect the power of a wireless RF signal without directly measuring the power of the RF signal. As discussed above in connection with equation 1, the strength of the input signal may be proportional to the power in the wireless RF signal. However, the apparatus 500 has other uses besides detecting the power of wireless RF signals. Apparatus 500 may be used in system 100 (but is not limited to a communication system). In one embodiment, apparatus 400 is used in a UE 110 (e.g., a wireless communication device). The apparatus 500 may be used on other devices such as the RAN 120.
Apparatus 500 depicts further details of one embodiment of apparatus 400. In particular, further details of one embodiment of the differential sensor stage 404 and the differential reference stage 406 are depicted. The differential sensor stage 404 includes a sensor transistor 502 and a sensor loading block 506. The differential reference stage 406 includes a reference transistor 504 and a reference load block 508.
In one embodiment, the sensor Transistor 502 and the reference Transistor 504 comprise Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs) transistors. The sensor transistor 502 and the reference transistor 504 may be of the same type. In one embodiment, the sensor transistor 502 and the reference transistor 504 comprise MOSFET transistors. The sensor transistor 502 and the reference transistor 504 may have the same configuration. In one embodiment, the sensor transistor 502 and the reference transistor 504 comprise MOSFET transistors having a source follower configuration.
Various transistors may have some structural differences due to variations in the manufacturing process. There may be structural differences between the sensor transistor 502 and the reference transistor 504. There may be structural differences between the transistors in the sensor transistor 502. There may be structural differences between the transistors in the reference transistor 504. Such structural differences may result in different characteristics, such as different capacitances. In some cases, the capacitance of the two transistors may differ by up to 20%. In some cases, the capacitances of the two transistors may differ by more than 20%. In some embodiments, the device 500 operates the transistor in the weak inversion region. Operating the transistor in the weak inversion region may make the transistor less sensitive to such structural and characteristic variations, thereby improving the accuracy of the device 500.
In one embodiment, the sensor loading block 506 and the reference loading block 508 each comprise a resistor. These resistors may be substantially matched in resistance. However, the resistors need not have exactly the same resistance. For example, the resistances may be slightly different from each other due to limitations of the manufacturing process. In one embodiment, the resistance values are within 2% of each other. In one embodiment, the resistance values are within 5% of each other. In one embodiment, the resistance values are within 10% of each other.
In one embodiment, the signal at the differential sensor stage output 420 has a DC component and an AC component. The DC component may come at least in part from the bias circuit 408. The AC component may be generated by the input signal. The sensor loading block 506 has a capacitor in parallel with the aforementioned resistor. The capacitor and the resistor may form a filter. In one embodiment, the filter smoothes the AC component, which may be used to stabilize the voltage at the differential sensor stage output 420.
In some embodiments, the apparatus 500 provides temperature compensation. In one embodiment, temperature compensation is provided in the reference load block 508. In one embodiment, the temperature compensation is provided by a Proportional To Absolute Temperature (PTAT) current source in the reference load block 508. In one embodiment, temperature compensation is provided in the sensor loading block 506. In one embodiment, the temperature compensation is provided by an inverse absolute temperature (CTAT) current source in the sensor loading block 506.
A PTAT or CTAT current source may help to keep the output signal of the differential output (between outputs 420, 422) within a target range. For example, the current source may be factory tuned to achieve an output signal range of 10dB to 20 dB. As another example, the current source may be tuned in the factory to achieve an output signal range of 0dB to 10 dB. In one embodiment, the PTAT current source in the reference load block 508 helps to maintain the output signal within a target range regardless of operating temperature. In one embodiment, the CTAT current source in the sensor loading block 506 helps to maintain the output signal within the target range regardless of the operating temperature. In some embodiments, each output 420, 422 is located at the source terminal of a MOSFET transistor. By adjusting the source terminal voltage, the gate-source voltage of the MOSFET can be adjusted. Thus, both techniques help to keep the transistors operating in the weak inversion region where they are less sensitive to process variations. Thus, the accuracy of the apparatus 500 is improved.
Fig. 6 is a circuit schematic of one embodiment of a signal power detector. The signal power detector 600 may be used to detect the power of an RF signal, but is not limited to an RF signal. Signal power detector 600 may be used in system 100, but is not limited to a communication system. In one embodiment, signal power detector 600 is used in UE 110 (e.g., a wireless communication device). The signal power detector 600 may be used on other devices such as the RAN 120.
The signal power detector 600 includes a capacitor stage 402, a bias circuit 408, a sensor transistor 502, a reference transistor 504, a sensor loading block 506, and a reference loading block 508. Together, the sensor transistor 502 and the sensor loading block 506 are one embodiment of the differential sensor stage 404. The reference transistor 504 and the reference load block 508 together are one embodiment of the differential reference stage 406.
Capacitor stage 402 includes an H-type capacitor bridge. The capacitor stage 402 receives input signals (V _ sig +, V _ sig-). The input signals (V _ sig +, V _ sig-) may be based on or derived from RF signals. In some embodiments, the RF signal is converted to an input signal. The input signal may be referred to herein as a voltage signal. In one embodiment, the input signal is derived from an RF signal generated by the transmitter 202. In one embodiment, the input signal is derived from an RF signal received by antenna 210. In some embodiments, signal power detector 600 detects a peak power level of the RF wireless signal based on detecting a peak voltage of V _ sig +, V _ sig-.
In the described embodiment, the H-type capacitor bridge includes five capacitors. Here, an "H-type capacitor bridge" is defined to include at least five capacitors in the configuration depicted in capacitor stage 402 of fig. 6. The capacitors in the H-type capacitor bridge may be referred to as a first input capacitor 602, a second input capacitor 604, a first output capacitor 606, a second output capacitor 608, and an H-capacitor 610. The first input capacitor 602 has a first terminal configured to receive V sig +. The first input capacitor 602 has a second terminal connected to a first terminal of the first output capacitor 606 and a first terminal of the H-capacitor 610. Second input capacitor 604 has a first terminal configured to receive V _ sig-. Second input capacitor 604 has a second terminal connected to a first terminal of second output capacitor 608 and to a second terminal of H-capacitor 610. A first terminal of the first output capacitor 606 is connected to a first terminal of an H capacitor 610. A second terminal of first output capacitor 606 is connected to a gate terminal of transistor 612. A first terminal of second output capacitor 608 is connected to a second terminal of H capacitor 610. A second terminal of second output capacitor 608 is connected to a gate terminal of transistor 614. Thus, the H-type capacitor bridge is configured to couple the input signal to the gates of the transistors 612, 614. Note that the gates of transistors 612, 614 may be used as signal inputs to differential sensor stage 404. Thus, the H-type capacitor bridge is configured to couple the input signal to the signal input of the differential sensor stage 404.
In one embodiment, the first input capacitor 602 and the second input capacitor 604 have substantially the same capacitance. In one embodiment, first output capacitor 606 and second output capacitor 608 have substantially the same capacitance. In one embodiment, the two capacitors have substantially the same capacitance, and their capacitances are within 2% of each other. In one embodiment, the two capacitors have substantially the same capacitance, and their capacitances are within 5% of each other. In one embodiment, the two capacitors have substantially the same capacitance, and their capacitances are within 10% of each other.
In one embodiment, the ratio of the capacitance of the input capacitors 602, 604 to the capacitance of the output capacitors 606, 608 is selected to control how much input signal is coupled to the gates of the sensor transistors 502. In one embodiment, the capacitance of the H-capacitor 610 may range from about 10% of the capacitance of the input capacitors 602, 604 to about the capacitance of the input capacitors 602, 604. In one embodiment, the capacitance of the H-capacitor 610 may range from about 10% of the capacitance of the output capacitors 606, 608 to about the capacitance of the output capacitors 606, 608. H-capacitor 610 may have a greater or lesser capacitance than these examples.
The sensor transistors 502 include a first sensor NMOS transistor 612 and a second sensor NMOS transistor 614. The sensor transistor 502 has a source follower configuration. Reference transistor 504 includes a first reference NMOS transistor 616 and a second reference NMOS transistor 618. The reference transistor 504 has a source follower configuration. Note that the gates of the first and second sensor NMOS transistors 612, 612 are one embodiment of the bias input 416 of the differential sensor stage 404. Similarly, the gates of first reference NMOS transistor 616 and second reference NMOS transistor 618 are one embodiment of bias input 418 of differential reference stage 406.
The bias circuit 408 has four bias resistors 622, 624, 626, 628. A bias resistor 622 is connected to the gate of the first sensor NMOS transistor 612 to provide a bias voltage (V _ bias). A bias resistor 624 is connected to the gate of the second sensor NMOS transistor 614 to provide a bias voltage (V _ bias). A bias resistor 626 is connected to the gate of the first reference NMOS transistor 616 to provide a bias voltage (V _ bias). A bias resistor 628 is connected to the gate of the second reference NMOS transistor 618 to provide a bias voltage (V _ bias). In one embodiment, the bias circuit 408 is configured to bias each transistor 612, 614, 616, and 618 in the weak inversion region.
The sensor load block 506 includes a sensor load resistor 632 and a load capacitor 634. In one embodiment, the sensor loading resistor 632 and loading capacitor 634 function as a filter. The filter may be used to smooth the AC signal component at the output 420. In some embodiments, the output 422 is free of an AC signal component. In some embodiments, the voltage between output 420 and output 422 is indicative of the peak power of the input signal. In fig. 6, the sensor loading block 506 may be referred to as a passive loading block.
The reference load block 508 includes a reference load resistor 636 and a PTAT current source 638. In one embodiment, the sensor load resistor 632 and the reference load resistor 636 are resistively matched. There may be some variation in resistance due to limitations in the resistor manufacturing process.
The reference loading block 508 is configured to provide temperature compensation to the signal power detector 600. The PTAT current source 638 may be configured to provide temperature compensation. In one embodiment, PTAT current source 638 is tuned such that the output signal at the differential output (between output 420 and output 422) is within a target range. The PTAT current source helps to keep the output signal within a target range, independent of operating temperature. Since the output is at the source terminal of the MOSFET transistor, the PTAT current source helps to keep the source voltage within the target range even if the temperature varies. Thus, the gate-source voltage of the MOSFET transistor can be adjusted. Thus, the PTAT current sources may help to keep the MOS transistors operating in weak inversion, in which case they are less sensitive to process variations. Thus, the accuracy of the detector 600 is improved. In FIG. 6, the reference load block 508 may be referred to as an active load block.
Fig. 7 is a circuit schematic of one embodiment of a signal power detector. The signal power detector 700 may be used to detect the power of an RF signal, but is not limited to an RF signal. Signal power detector 700 may be used in system 100, but is not limited to a communication system. In one embodiment, signal power detector 600 is used in UE 110 (e.g., a wireless communication device). The signal power detector 600 may be used on other devices such as the RAN 120.
Signal power detector 700 in fig. 7 is similar to signal power detector 700, but sensor load block 506 and reference load block 508 are configured differently. While temperature compensation is provided by the reference load block 508 in the circuit of fig. 6, temperature compensation is provided by the sensor load block 506 in the circuit of fig. 7. Capacitor stage 402, bias circuit 408, sensor transistor 502, and reference transistor 504 in signal power detector 700 are similar to those in signal power detector 600 and therefore will not be described in detail.
The sensor loading block 506 includes a sensor loading resistor 732, a loading capacitor 734, and a CTAT current source 736. In one embodiment, the sensor loading resistor 732 and the loading capacitor 734 function as a filter. The filter may be used to smooth the AC signal component at the output 420. In some embodiments, the output 422 is free of an AC signal component. In some embodiments, the voltage between output 420 and output 422 is indicative of the peak power of the input signal.
Sensor loading block 506 is configured to provide temperature compensation to signal power detector 700. The CTAT current source 736 may be configured to provide temperature compensation. In one embodiment, CTAT current source 736 is tuned such that the output signal at the differential output (between output 420 and output 422) is within a target range. The CTAT current source helps to maintain the output signal within a target range, independent of operating temperature. Since the output is at the source terminal of the MOSFET transistor, the CTAT current source helps to keep the source voltage within the target range even if the temperature varies. Thus, the gate-source voltage of the MOSFET transistor can be adjusted. Thus, the CTAT current source may help to keep the MOSFET transistors operating in weak inversion, in which case they are less sensitive to process variations. Accordingly, the accuracy of the signal power detector 700 is improved. In fig. 6, the passive load block 508 may be referred to as an active load block.
The reference load block 508 includes a reference load resistor 738. In one embodiment, the sensor loading resistor 732 and the reference loading resistor 738 are matched in resistance. There may be some variation in resistance due to limitations in the resistor manufacturing process. In FIG. 7, reference load block 508 may be referred to as a passive load block.
Figure 8 depicts a flow diagram of one embodiment of a process 800 of detecting input signal strength. In one embodiment, the input signal is an RF signal, or is at least based on an RF signal. Process 800 may be implemented in, but is not limited to, apparatus 400, apparatus 500, signal power detector 600, signal power detector 700. For ease of explanation, the steps are described in a certain order. Some or all of the steps may occur simultaneously.
Step 802 includes biasing the differential sensor stage 404. Step 802 may include biasing circuit 408 applying V _ bias to the gates of MOSFET transistor 612 and MOSFET transistor 614. Step 802 may also include applying Vdd to the drain terminals of MOSFET transistor 612 and MOSFET transistor 614. Step 802 may also include grounding the sensor loading block 506.
Step 804 includes biasing the differential reference stage 406. In some embodiments, substantially the same bias conditions are applied to the differential sensor stage 404 and the differential reference stage 406. In one embodiment, step 804 includes biasing circuit 408 applying V _ bias to the gates of MOSFET transistor 616 and MOSFET transistor 618. Step 804 may also include applying Vdd to the drain terminals of MOSFET transistor 616 and MOSFET transistor 618. Step 804 may also include grounding reference load block 508.
By applying the same bias voltage to the gate terminal and by applying substantially the supply voltage (e.g., vdd) to the drain terminal, substantially the same bias conditions can be achieved. In some cases, there may be some small differences in the precise bias voltages applied to the gates due to, for example, small differences in the resistances of the various bias resistors 622, 624, 626, 628. Furthermore, there may be some small differences in the exact bias voltages applied to the gates due to, for example, small differences in the bias voltages (e.g., V _ bias) applied to the bias resistors 622, 624, 626, 628.
Step 806 includes coupling the input signal to the differential sensor using the capacitor stage 402. In one embodiment, capacitor stage 402 includes an H-type capacitor bridge. The input signal may be generated by converting the RF signal into a voltage signal, wherein the voltage signal is proportional to the power of the RF signal, as shown in equation 1.
Step 808 includes accessing a signal at the differential output indicative of the strength of the input signal. In some embodiments, a differential output is formed from the output 420 of the differential sensor stage 404 and the output 422 of the differential reference stage 406. In one embodiment, the signal is indicative of a peak voltage level of the input signal. In one embodiment, the signal is indicative of a peak power level of the input signal. Note that given equation 1, the strength of an input signal may be related to another signal, such as the power of a wireless RF signal.
Fig. 9 depicts a flow diagram of one embodiment of a process 900 for operating a differential stage of a signal power detector in a weak inversion region. Process 900 describes one embodiment of operating the differential sensor stage 404 and the differential reference stage 406 in the weak inversion region. Process 900 describes further details of one embodiment of steps 802, 804, and 806 in process 800. In one embodiment, the input signal is an RF signal. Process 900 may be implemented in, but is not limited to, apparatus 400, apparatus 500, signal power detector 600, signal power detector 700. For ease of explanation, the steps are described in a certain order. Some or all of the steps may occur simultaneously.
Step 902 includes biasing a source follower configuration in the differential sensor stage 404 in the weak inversion region. Step 904 includes biasing the source follower configuration in the differential reference 406 in the weak inversion region. Steps 902 and 904 include applying a suitable bias voltage (V bias) to the gates of MOSFETs 612, 614, 616 and 618. The magnitude of the bias voltage will depend on the threshold voltage of the MOSFET. The magnitude of the bias voltage may also depend on other factors, such as the resistances of the bias resistors 622, 624, 626, and 628 and the load resistors 632, 636, 732, and/or 738.
Step 906 includes coupling a voltage signal (e.g., V _ sig +, V _ sig-) to an input of the differential sensor stage 404 while maintaining the differential sensor stage 404 in a weak inversion region. In one embodiment, the capacitor stage 402 is configured to maintain the magnitude of the input signal coupled to the gates of the MOSFETs in the differential sensor stage 404 within a target range such that the MOSFETs in the differential sensor stage 404 remain in the weak inversion region under a combination of the bias voltage and the coupled input voltage.
Fig. 10 depicts a flow diagram of one embodiment of a process 1000 of providing temperature compensation in a signal power detector. Process 1000 describes further details of one embodiment of process 800. In one embodiment, the input signal is an RF signal. Process 1000 may be implemented in, but is not limited to, apparatus 400, apparatus 500, signal power detector 600, signal power detector 700. For ease of explanation, the steps are described in a certain order. Some or all of the steps may occur simultaneously.
Step 1002 includes biasing a differential sensor stage 404 having sensor transistors 612, 614 and a sensor loading block 506.
Step 1004 includes biasing the differential reference stage 406 with reference transistors 616, 618 and the reference load block 508.
Step 1006 includes coupling the input signal to the differential sensor using the capacitor stage 402. In one embodiment, capacitor stage 402 includes an H-type capacitor bridge.
Step 1008 includes providing temperature compensation using one of the load blocks. In one embodiment, the reference load block 508 is used to provide temperature compensation. In one embodiment, providing temperature compensation includes using a Proportional To Absolute Temperature (PTAT) current source in the reference load block 508. Providing temperature compensation using the reference load block 508 may result in maintaining the output signal at the differential output within a target range independent of temperature. This helps to keep the MOSFETs operating in the weak inversion region, thereby improving the accuracy of the signal detector.
In one embodiment, the sensor loading block 506 is used to provide temperature compensation. In one embodiment, providing temperature compensation includes using an inverse proportional to absolute temperature (CTAT) current source in the sensor loading block 506. Providing temperature compensation using the sensor loading block 506 may result in maintaining the output signal at the differential output within a target range independent of temperature. This helps to keep the MOSFET operating in the weak inversion region, thereby improving the accuracy of the signal detector.
Step 1010 includes accessing a signal at the differential output indicative of the strength of the input signal.
Fig. 11 depicts the relationship between signal power and voltage of a MOSFET in an embodiment of a signal power detector. Fig. 11 pertains to one embodiment of the sensors MOSET 612, 614. Line 1102 represents the DC gate voltage (Vg) of the MOSFET. This is a voltage that may be generated due to biasing the MOSFET. Line 1106 represents the threshold voltage (Vth) of the MOSFET. Neither the DC gate voltage 1102 nor the threshold voltage 1106 is dependent on the signal power. Curve 1104 represents the source terminal voltage (Vs) of the MOSFET. Note that Vs increases with increasing signal power. Curve 1108 represents Vgs, which is given by the difference between line 1102 and curve 1104. Thus, as Vs increases, vgs decreases. Note that Vgs is below Vth for any power, indicating that the MOSFET is in the weak inversion region. Note also that as power increases, vgs decreases, which provides some room for the AC signal at the MOSFET gate since the input signal is coupled to the gate. However, even if the input signal is coupled to the gate of the MOSFET, the MOSFET can still operate in the weak inversion region.
There are many possible applications for embodiments of the signal strength detector. One embodiment includes an apparatus that adjusts a sensitivity of an RF receiver based on a detected power level of an RF signal received by the apparatus. The apparatus may be a wireless communication device such as, but not limited to, a cellular telephone. Fig. 12 depicts a flow diagram of one embodiment of a process 1200 for adjusting the sensitivity of an RF receiver based on the detected power level of an RF signal received by the RF receiver. Process 1200 may be implemented in UE 110, but is not limited thereto.
Step 1202 includes receiving an RF signal at a wireless communication device (e.g., UE 110). The received RF signal may be a wireless RF signal. Referring to fig. 2, an antenna 210 may be used to access wireless RF signals processed by the receiver 204.
Step 1204 includes sampling the RF signal and converting the RF signal to a voltage signal. The strength of the voltage signal has a magnitude proportional to the power of the wireless RF signal. To compare the strength of the voltage signal with the power of the RF signal, the voltage signal may be associated with a resistance. Therefore, there will be a power (P = V) associated with the voltage signal 2 and/R). In one embodiment, a directional coupler is used to sample the RF signal. The directional coupler may also convert the RF signal to a voltage signal. Thus, process 1200 describes a technique that does not directly measure the power of the wireless RF signal. Instead, the strength of the voltage signal is measured, wherein the power of the wireless RF signal may be determined from the strength of the voltage signal.
Step 1206 includes providing a voltage signal to an input of the RF power detector. For example, the voltage signal may be an input signal of the apparatus 400 or the apparatus 500. For example, the voltage signal (V _ sig +, V _ sig-) may be input to the signal power detector 600 or the signal strength detector 700.
Step 1208 includes detecting a strength of the voltage signal. Since the voltage signal is proportional to the power of the wireless RF signal, step 1208 indirectly determines the power of the wireless RF signal. As described above, the voltage at the differential output (420, 422) may be indicative of the strength of the input signal. Step 1208 may be based on the voltage at the differential output (420, 422). This voltage (e.g., a DC voltage) may be used to determine the strength (e.g., voltage or power) of the input signal (e.g., V _ sig +, V _ sig-). In some embodiments, the strength of V _ sig + and V _ sig-is used to determine the power level of a wireless RF signal received by the wireless communication device.
Step 1210 includes determining whether to adjust the sensitivity of the RF receiver 204. This is based on the strength of the detected voltage signal. Step 1210 may include determining whether the intensity is outside of the window. The window may correspond to a range of acceptable power levels of the wireless RF signal. If sensitivity is to be adjusted, control passes to step 1212. Step 1212 includes adjusting the sensitivity of the RF receiver 204. After adjusting the sensitivity, process 1200 may repeat so that the adjustment may be made on an ongoing basis. In the event that it is determined in step 1210 that no adjustment is to be made, process 1200 may repeat so that an adjustment may be made if the RF signal strength changes.
One embodiment includes an apparatus that adjusts a gain of an RF transmitter based on a detected power level of an RF signal transmitted by the apparatus. The apparatus may be a wireless communication device such as, but not limited to, a cellular telephone. Fig. 13 depicts a flow diagram of one embodiment of a process 1300 of adjusting a gain of an RF transmitter based on a detected power level of an RF signal transmitted by the RF transmitter. Process 1300 may be implemented in UE 110, but is not limited to such.
Step 1302 includes accessing an RF signal transmitted by a wireless communication device (e.g., UE 110). Referring to fig. 2, the transmitter 202 may be used to generate an RF signal that is then transmitted by an antenna 210. The RF signal may be accessed prior to wireless transmission. For example, a directional coupler may be used to sample the RF signal prior to wireless transmission through antenna 210.
Step 1304 includes converting the incoming RF signal to a voltage signal. The magnitude of the voltage signal is proportional to the power of the transmitted wireless RF signal. Thus, process 1300 describes a technique for not directly measuring the power of a wireless RF signal. Instead, the strength of the voltage signal is measured.
Step 1306 includes providing a voltage signal to an input of the RF power detector. The voltage signal may be an input signal to the apparatus 400, the apparatus 500, the signal power detector 600, or the signal strength detector 700.
Step 1308 includes detecting a strength of the voltage signal. Step 1308 may indirectly determine the power of the transmitted wireless RF signal. As described above, the voltage at the differential output (420, 422) may be indicative of the strength of the input signal.
Step 1310 includes determining whether to adjust the gain of the RF transmitter 202. This is based on the strength of the detected voltage signal. Step 1308 can include determining whether the detected strength of the voltage signal is outside a window corresponding to an acceptable power range of the transmitted RF signal. The window refers to the range of acceptable power levels of the transmitted RF signal. For example, there may be provisions to limit the power level of the transmitted RF signal. On the other hand, the transmitted RF signal should be strong enough to be adequately received by the target of the RF transmission. In practice, the gain of the RF transmitter may thus be adjusted based on the power of the transmitted RF signal.
If the gain is to be adjusted, control passes to step 1312. Step 1312 includes adjusting the gain of the RF transmitter 202. After adjusting the gain, the process 1300 may repeat so that the adjustment may be made on an ongoing basis. Where it is determined in step 1310 that no adjustment is to be made, process 1300 may repeat so that an adjustment may be made if the strength of the transmitted RF signal changes. For example, operating conditions such as temperature may affect the gain of the RF transmitter. Further, in some cases, the window in step 1310 may change. For example, in situations where a target has difficulty receiving RF signals, it may be desirable to increase the gain to transmit stronger RF signals.
The techniques described herein may be implemented using hardware, software, or a combination of hardware and software. The software used is stored on the one or more processor readable storage devices to program the one or more processors to perform the functions described herein. The processor-readable storage device may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer-readable media may comprise computer-readable storage media and communication media. Computer-readable storage media may be implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. One or more computer-readable media do not include propagated, modulated, or transitory signals.
Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.
In alternative embodiments, some or all of the software may be replaced by dedicated hardware logic components. For example, but not limited to, illustrative types of hardware Logic components that may be used include Field-Programmable Gate arrays (FPGAs), application-specific Integrated circuits (ASICs), application-specific Standard products (ASSPs), system-on-chip (SOCs), complex Programmable Logic Devices (CPLDs), special purpose computers, and the like. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors may communicate with one or more computer-readable media/storage devices, peripherals, and/or communication interfaces.
It should be understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete, and will fully convey the disclosure to those skilled in the art. Indeed, the present subject matter is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. It will be apparent, however, to one skilled in the art that the present subject matter may be practiced without these specific details.
Aspects of the present disclosure are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various modifications as are suited to the particular use contemplated.
For purposes herein, each process associated with the disclosed technology may be performed continuously by one or more computing devices. Each step in the process may be performed by the same or different computing device as used in the other steps, and each step need not be performed by a single computing device.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (69)

1. An apparatus for detecting signal strength, wherein the apparatus comprises:
a differential sensor stage having an input and an output;
a differential reference stage having an input and an output;
a capacitor stage configured to couple an input signal to an input of the differential sensor stage;
a bias circuit configured to bias the differential sensor stage and the differential reference stage; and
a differential output between an output of the differential sensor stage and an output of the differential reference stage, the differential output configured to provide a signal indicative of the input signal strength.
2. The apparatus of claim 1, wherein:
the biasing circuit is configured to bias the differential sensor stage and the differential reference stage in a weak inversion region.
3. The apparatus of claim 1 or 2, wherein:
the bias circuit is configured to apply substantially the same bias conditions to the differential sensor stage and the differential reference stage.
4. The apparatus of claim 2 or 3, wherein the capacitor stage is configured to maintain the differential sensor stage operating in the weak inversion region.
5. The apparatus of claim 4, wherein the capacitor stage is configured to maintain an input signal at an input of the differential sensor stage within a target range to maintain the differential sensor stage operating in the weak inversion region.
6. The apparatus of any one of claims 1-5, wherein:
the capacitor stage includes an H-type capacitor bridge.
7. The apparatus of claim 6, wherein the H-type capacitor bridge comprises:
a first capacitor having a first terminal and a second terminal;
a second capacitor having a first terminal and a second terminal, the first terminals of the first and second capacitors configured to receive the input signal;
a third capacitor having a first terminal connected to the second terminal of the first capacitor, the third capacitor having a second terminal connected to the first terminal of the input of the differential sensor stage;
a fourth capacitor having a first terminal connected to the second terminal of the second capacitor, the fourth capacitor having a second terminal connected to the second terminal of the input of the differential sensor stage; and
a fifth capacitor having a first terminal connected to the second terminal of the first capacitor and the first terminal of the third capacitor, the fifth capacitor having a second terminal connected to the second terminal of the second capacitor and the first terminal of the fourth capacitor.
8. The apparatus of claim 7, wherein the first capacitor and the second capacitor have substantially the same capacitance.
9. The apparatus of claim 7 or 8, wherein the third capacitor and the fourth capacitor have substantially the same capacitance.
10. The apparatus of any one of claims 1-9, wherein:
the differential sensor stage comprises a first transistor and a second transistor having a source follower configuration; and
the differential reference stage includes third and fourth transistors having a source follower configuration.
11. The apparatus of any one of claims 1-10, wherein:
the differential sensor stage comprises a first MOSFET transistor and a second MOSFET transistor having a source follower configuration; and
the differential reference stage includes a third MOSFET transistor and a fourth MOSFET transistor having a source follower configuration.
12. The apparatus of any one of claims 1-11, wherein:
the differential sensor stage comprises a first load block coupled to an output of the differential sensor stage; and
the differential reference stage includes a second load block coupled to an output of the differential reference stage.
13. The apparatus of claim 12, wherein:
the first load block includes a first resistor; and
the second load block includes a second resistor, wherein the first resistor and the second resistor have substantially the same resistance.
14. The apparatus of claim 12 or 13, wherein the second load block is configured to provide temperature compensation to the circuit.
15. The apparatus of any of claims 12-14, wherein the second load block is configured to maintain the signal at the differential output within a target range independent of temperature.
16. The apparatus of any of claims 12-15, wherein the second load block further comprises a current source proportional to absolute temperature PTAT in parallel with the second resistor.
17. The apparatus of any of claims 12-16, wherein the first load block further comprises a capacitor in parallel with the first resistor.
18. The apparatus of any one of claims 11-17, wherein:
the first load block comprises a passive load block; and
the second load block comprises an active load block.
19. The apparatus of claim 12 or 13, wherein the first loading block is configured to provide temperature compensation.
20. The apparatus of claim 12, 13 or 19, wherein the first loading block is configured to maintain the signal at the differential output within a target range independent of temperature.
21. The apparatus of claim 12, 13, 19 or 20, wherein the first loading block further comprises a current source in inverse proportional to absolute temperature CTAT in parallel with the first resistor.
22. The apparatus of any one of claims 12, 13, or 19-21, wherein:
the first load block comprises an active load block; and
the second load block comprises a passive load block.
23. The apparatus of any one of claims 1-22, wherein the input signal is based on a Radio Frequency (RF) signal.
24. The apparatus of claim 23, further comprising:
an RF transmitter configured to generate the RF signal; and
an antenna coupled to the RF transmitter and configured to transmit the RF signal, wherein a strength of the input signal is proportional to a power of the transmitted RF signal.
25. The apparatus of claim 23, further comprising:
an RF receiver configured to generate the RF signal; and
an antenna coupled to the RF receiver and configured to receive the RF signal, wherein a strength of the input signal is proportional to a power of the received RF signal.
26. The apparatus of any of claims 1-25, wherein the strength comprises a peak voltage of the input signal.
27. The apparatus of any of claims 1-26, wherein the strength corresponds to a peak power of the input signal.
28. A method for detecting signal strength, the method comprising:
biasing a differential sensor stage having an input and an output;
biasing a differential reference stage having an input and an output;
coupling an input signal to an input of the differential sensor stage using a capacitor stage; and
providing a signal indicative of the input signal strength at a differential output between the output of the differential sensor stage and the output of the differential reference stage.
29. The method of claim 28, wherein biasing the differential sensor stage and biasing the differential reference stage comprises:
biasing the differential sensor stage in a weak inversion region; and
biasing the differential reference in a weak inversion region.
30. The method of claim 28 or 29, wherein biasing the differential sensor stage and biasing the differential reference stage comprises:
applying substantially the same bias condition to the differential sensor stage and the differential reference stage.
31. The method of any one of claims 28-30, wherein:
biasing the differential sensor stage comprises biasing a first MOSFET transistor and a second MOSFET transistor having a source follower configuration; and
biasing the differential reference stage includes biasing a third MOSFET transistor and a fourth MOSFET transistor having a source follower configuration.
32. The method according to any one of claims 29-31, further comprising:
maintaining the differential sensor stage in the weak inversion region by coupling the input signal to an input of the differential sensor stage using the capacitor stage.
33. The method according to any one of claims 29-32, further comprising:
maintaining an input signal at an input of the differential sensor stage within a target range to maintain the differential sensor stage operating in the weak inversion region.
34. The method of any of claims 28-33, wherein coupling the input signal to the input of the differential sensor stage using the capacitor stage comprises:
coupling the input signal to an input of the differential sensor stage using an H-type capacitor bridge in the capacitor stage.
35. The method of any one of claims 28-34, wherein:
biasing the differential sensor stage further comprises grounding a first loading block coupled to an output of the differential sensor stage; and
biasing the differential reference stage further comprises grounding a second load block coupled to an output of the differential reference stage.
36. The method of claim 35, further comprising:
providing temperature compensation using the first load block.
37. The method of claim 35 or 36, further comprising:
temperature compensation is provided in the first loading block using a proportional to absolute temperature PTAT current source.
38. The method of any one of claims 36 or 37, wherein providing temperature compensation using the first load block comprises:
the signal at the differential output is maintained within a target range independent of temperature.
39. The method of claim 35, further comprising:
providing temperature compensation using the second load block.
40. The method of claim 35, further comprising:
temperature compensation is provided in the second loading block using a current source that is inversely proportional to absolute temperature (CTAT).
41. The method of any one of claims 39 or 40, wherein providing temperature compensation using the second load block comprises:
the signal at the differential output is maintained within a target range independent of temperature.
42. The method of any one of claims 28-41, wherein the input signal is based on a Radio Frequency (RF) signal.
43. The method of claim 42, further comprising:
adjusting a wireless transceiver in response to a signal indicating that the strength of the input signal exceeds a threshold.
44. A wireless communication device, comprising:
a transceiver configured to receive and transmit Radio Frequency (RF) signals;
a differential sensor stage having an input and an output;
a differential reference stage having an input and an output;
a capacitor stage coupled to the transceiver and configured to couple a voltage signal based on an RF signal to an input of the differential sensor stage;
a bias circuit configured to bias the differential sensor stage and the differential reference stage; and
a differential output between an output of the differential sensor stage and an output of the differential reference stage, the differential output configured to provide a signal indicative of a power of the RF signal.
45. The wireless communication device of claim 44, wherein:
the biasing circuit is configured to bias the differential sensor stage and the differential reference stage in a weak inversion region.
46. The wireless communication device of claim 44 or 45, wherein:
the bias circuit is configured to apply substantially the same bias conditions to the differential sensor stage and the differential reference stage.
47. The wireless communication device of claim 45 or 46, wherein the capacitor stage is configured to maintain the differential sensor stage operating in the weak inversion region.
48. The wireless communication device of claim 47, wherein the capacitor stage is configured to maintain a voltage signal at an input of the differential sensor stage within a target range to maintain the differential sensor stage operating in the weak inversion region.
49. The wireless communication device of any one of claims 44-48, wherein:
the capacitor stage includes an H-type capacitor bridge.
50. The wireless communication device of claim 49, wherein the H-type capacitor bridge comprises:
a first capacitor having a first terminal and a second terminal;
a second capacitor having a first terminal and a second terminal, the first terminals of the first and second capacitors configured to receive the voltage signal;
a third capacitor having a first terminal connected to the second terminal of the first capacitor, the third capacitor having a second terminal connected to the first terminal of the input of the differential sensor stage;
a fourth capacitor having a first terminal connected to the second terminal of the second capacitor, the fourth capacitor having a second terminal connected to the second terminal of the input of the differential sensor stage; and
a fifth capacitor having a first terminal connected to the second terminal of the first capacitor and the first terminal of the third capacitor, the fifth capacitor having a second terminal connected to the second terminal of the second capacitor and the first terminal of the fourth capacitor.
51. The wireless communication device of claim 50, wherein the first capacitor and the second capacitor have substantially the same capacitance.
52. The wireless communication device of claim 50 or 51, wherein the third capacitor and the fourth capacitor have substantially the same capacitance.
53. The wireless communication device of any one of claims 44-52, wherein:
the differential sensor stage comprises a first transistor and a second transistor having a source follower configuration; and
the differential reference stage includes third and fourth transistors having a source follower configuration.
54. The wireless communication device of any one of claims 44-53, wherein:
the differential sensor stage comprises a first MOSFET transistor and a second MOSFET transistor having a source follower configuration; and
the differential reference stage includes a third MOSFET transistor and a fourth MOSFET transistor having a source follower configuration.
55. The wireless communication device of any one of claims 44-54, wherein:
the differential sensor stage comprises a first load block coupled to an output of the differential sensor stage; and
the differential reference stage includes a second load block coupled to an output of the differential reference stage.
56. The wireless communication device of claim 55, wherein:
the first load block includes a first resistor; and
the second load block includes a second resistor, wherein the first and second resistors have substantially the same resistance.
57. The wireless communication device of claim 55 or 56, wherein the second loading block is configured to provide temperature compensation to the circuit.
58. The wireless communication device of any one of claims 55-57, wherein the second loading block is configured to maintain the signal at the differential output within a target range independent of temperature.
59. The wireless communication device of any of claims 55-58, wherein the second load block further comprises a current source in parallel with the second resistor that is a proportional to absolute temperature PTAT.
60. The wireless communication device of any one of claims 55-59, wherein the first loading block further comprises a capacitor in parallel with the first resistor.
61. The wireless communication device of any of claims 55-60, wherein:
the first load block comprises a passive load block; and
the second load block comprises an active load block.
62. The wireless communication device of claim 55 or 56, wherein the first loading block is configured to provide temperature compensation.
63. The wireless communication device of any one of claims 55, 56, or 62, wherein the first loading block is configured to maintain the voltage signal at the differential output within a target range independent of temperature.
64. The wireless communication device of claim 55, 56, 63 or 63, wherein the first loading block further comprises a current source in parallel with the first resistor that is inversely proportional to absolute temperature (CTAT).
65. The wireless communication device of any of claims 55, 56, or 62-64, wherein:
the first load block comprises an active load block; and
the second load block comprises a passive load block.
66. The wireless communication device of any one of claims 44-65, wherein the RF signal is transmitted by a transmitter in the transceiver, and further comprising:
adjusting a gain of the transmitter in response to the power of the RF signal outside of the window.
67. The wireless communication device of any one of claims 44-65, wherein the RF signal is received by a receiver in the transceiver, and further comprising:
adjusting the sensitivity of the receiver in response to the power of the RF signal outside the window.
68. The wireless communication device of any of claims 44-67, wherein the power comprises a peak power level of the RF signal.
69. The wireless communication device of any one of claims 44-68, wherein the signal indicative of the power of the RF signal comprises a DC voltage at the differential output.
CN202080097753.2A 2020-03-04 2020-04-01 Signal strength detector Pending CN115211032A (en)

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