WO2020114365A1

WO2020114365A1 - Transmitter output calibration

Info

Publication number: WO2020114365A1
Application number: PCT/CN2019/122530
Authority: WO
Inventors: Chun-Cheng Wang; Roger Rauvola
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-12-03
Filing date: 2019-12-03
Publication date: 2020-06-11

Abstract

A circuit includes a processor formed on a substrate to generate a digital output and a transmitter formed on the substrate. The transmitter is coupled to receive the digital output and generate a high-frequency analog signal from the digital output. The transmitter includes a power amplifier to amplify the high-frequency analog signal. A self-test circuit formed on the substrate is coupled to the high-frequency analog signal to generate a digital value according to the high-frequency analog signal and send the digital value to the processor to calibrate the transmitter.

Description

TRANSMITTER OUTPUT CALIBRATION

CROSS-REFERENCE

This application claims priority to U.S. provisional patent application Serial No. 62/774,421, filed on December 3, 2018 and entitled “Transmitter Output Calibration” , which is incorporated herein by reference as if reproduced in its entirety.

FIELD

The disclosure generally relates to electrical circuits including integrated circuits used in communications.

BACKGROUND

Electronic circuits, including electronic circuits formed as integrated circuits (ICs) on semiconductor substrates, are used in a variety of applications including in communication systems. For example, a transmitter circuit may be formed of one or more integrated circuits formed on one or more silicon substrates and a receiver circuit may be formed of one or more integrated circuits formed on one or more silicon substrates. In some cases, transmitter and receiver circuits are formed on the same silicon substrate. Process variations when forming such circuits (in combination with other factors) may result in variation in characteristics between such circuits. Such variation may present challenges, particularly at high frequencies (e.g. at frequencies above 20GHz) . Variation in ICs may be measured and used to sort ICs (e.g. ICs may pass or fail testing in a factory) . In some cases, circuits may be calibrated according to their measured characteristics so that variation between ICs due to process variation or other factors may be reduced.

BRIEF SUMMARY

According to one aspect of the present disclosure, there is provided a circuit that includes a processor to generate a digital output. A transmitter is formed on a substrate. The transmitter is coupled to receive the digital output and generate a high-frequency analog signal from the digital output, the transmitter including a power amplifier to amplify the high-frequency analog signal. A self-test circuit is formed on the substrate, the self-test circuit coupled to the high-frequency analog signal to generate a digital value according to the high-frequency analog signal. The self-test circuit is coupled to the processor to send the digital value to the processor to calibrate the transmitter. This allows on-chip calibration of the transmitter so that calibration may be performed in the field, without use of external equipment.

Optionally, in any of the preceding aspects, the processor is coupled to control one or more parameters of one or more transmitter components.

Optionally, in any of the preceding aspects, the transmitter components include: one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal, one or more filters to filter the low-frequency analog signal, and one or more mixers to up-convert the low-frequency analog signal.

Optionally, in any of the preceding aspects, the one or more parameters include gain of the one or more of the digital-to-analog converters, the one or more filters, and the one or more mixers and wherein the processor is configured to vary the gain while sampling the digital value.

Optionally, in any of the preceding aspects, the processor is configured to select gain settings for the one or more of the digital-to-analog converters, the one or more filters, and the one or more mixers according to results of the sampling.

Optionally, in any of the preceding aspects, the processor is configured to turn off the power amplifier to vary the gain while sampling the digital value.

Optionally, in any of the preceding aspects, the digital value represents peak voltage of the high-frequency analog signal.

Optionally, in any of the preceding aspects, the self-test circuit includes a differential input coupled to the high-frequency analog signal, capacitors to decouple direct current (DC) from the high-frequency analog signal, and transistors coupled to DC voltages from the capacitors.

Optionally, in any of the preceding aspects, the self-test circuit further includes a bias voltage circuit to provide a bias voltage to gates of the transistors, the bias voltage adjusted for temperature of the substrate and for device characteristics.

According to one other aspect of the present disclosure, there is provided a method that includes: generating a digital output in a processor; generating a high-frequency analog signal from the digital output in a transmitter formed on a substrate; providing the high-frequency analog signal to a power amplifier on the substrate; generating a digital value from the high-frequency analog signal provided to the power amplifier; and sending the digital value to the processor to calibrate the transmitter. The digital output may be a test signal and digital values may be received with different transmitter configurations (e.g. different gain settings) to allow self-calibration.

Optionally, in any of the preceding aspects, the high-frequency analog signal is generated by transmitter components that include: one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal, one or more filters to filter the low-frequency analog signal, and one or more mixers to up-convert the low-frequency analog signal, the method further comprising controlling one or more parameters of one or more transmitter components while generating the digital output and while sending the digital value to the processor.

Optionally, in any of the preceding aspects, the one or more parameters include gain of one or more transmitter components, the method further comprising: varying the gain of the one or more transmitter components while generating the digital output and sending the digital value to the processor to generate calibration data; obtaining gain settings of the one or more transmitter components from the calibration data; and applying the gain settings in the one or more transmitter components.

Optionally, in any of the preceding aspects, the digital value is obtained from peak voltage of the high-frequency analog signal and obtaining the gain settings includes consulting a stored relationship between target peak voltage of the high-frequency analog signal and operating variables of the transmitter.

Optionally, in any of the preceding aspects, the operating variables of the transmitter include temperature and device characteristics.

Optionally, in any of the preceding aspects, the method includes turning on the power amplifier while applying the gain settings in one or more transmitter components; and turning off the power amplifier while generating the calibration data.

Optionally, in any of the preceding aspects, the method includes, subsequent to turning on the power amplifier and while applying the gain settings, sending a test signal through the transmitter, the power amplifier, and a receiver to check transmitter operation using the gain settings.

Optionally, in any of the preceding aspects, the method further includes varying the gain of the one or more transmitter components, obtaining gain settings, and applying the gain settings are performed as a self-calibration routine in response to at least one of: product testing, temperature change, change in transmitter characteristics from use, and time since previous self-calibration.

According to still one other aspect of the present disclosure, there is provided a system comprising: a transmitter formed on a substrate, the transmitter coupled to receive a digital output, the transmitter including: one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal; one or more filters to filter the low-frequency analog signal; one or more mixers to up-convert the low-frequency analog signal to a high-frequency analog signal; and a power amplifier to amplify the high-frequency analog signal; a self-test circuit formed on the substrate, the self-test circuit coupled to the high-frequency analog signal to measure peak voltage of the high-frequency analog signal; and a processor formed on the substrate, the processor configured to generate the digital output and provide the digital output to the transmitter while varying gain of one or more of the digital-to-analog converters, filters, and mixers of the transmitter, and while receiving measured peak voltage from the self-test circuit to obtain a relationship between gain and peak voltage.

Optionally, in any of the preceding aspects, the processor includes a stored target peak voltage, the processor configured to obtain gain values corresponding to the stored target peak voltage from the relationship between gain and peak voltage and to apply the gain values in the transmitter.

Optionally, in any of the preceding aspects, the processor is configured to obtain the relationship between gain and peak voltage in response to at least one of: product testing, temperature change, change in transmitter characteristics from use, and time since previous self-calibration.

According to still one other aspect of the present disclosure, there is provided a circuit that includes a processor module formed on a substrate to generate a digital output; a transmitter module formed on the substrate, the transmitter module coupled to receive the digital output and generate a high-frequency analog signal from the digital output, the transmitter module including a power amplifier to amplify the high-frequency analog signal; and a self-test module formed on the substrate, the self-test module coupled to the high-frequency analog signal to generate a digital value according to the high-frequency analog signal, the self-test module coupled to the processor module to send the digital value to the processor module to calibrate the transmitter module

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures (FIGS. ) for which like references indicate elements.

FIGURE (FIG. ) 1 illustrates an exemplary wireless network for communicating data.

FIG. 2 illustrates exemplary details of an instance of user equipment (UE) introduced in FIG. 1.

FIG. 3 illustrates exemplary details of an instance of a base station (BS) introduced in FIG. 1.

FIG. 4 illustrates exemplary details of a System on a Chip (SOC) implementation.

FIGs. 5A-B illustrate exemplary details of transmitters.

FIG. 6 illustrates exemplary details of a transmitter and self-test circuit.

FIGS. 7 illustrates exemplary details of transmitter components including mixers and a local oscillator.

FIG. 8 illustrates an example of a detector circuit in a self-test circuit.

FIGS. 9A-C illustrate examples of circuits to provide a gate voltage to a detector circuit.

FIG. 10 illustrates an example of a method to generate data to calibrate a transmitter.

FIGS. 11 illustrates an example of a method to obtain and apply gain settings.

FIG. 12 illustrates exemplary details of test equipment for transmitter testing and characterization.

DETAILED DESCRIPTION

The present disclosure will now be described with reference to the figures, which in general relate to self-test and calibration circuits that are formed on-chip so that an integrated circuit can perform some closed-loop testing and calibration without requiring external test equipment. This can save time and reduce equipment needed during testing and may allow an integrated circuit to perform recalibration in the field without external equipment (e.g. in a manner that may be transparent to a user) .

For example, a self-test circuit may be formed on-chip (i.e. on the same substrate) with a transmitter, such as a transmitter in a cell phone or other user equipment that uses wireless communication. The self-test circuit may be coupled to a high-frequency analog signal in a transmitter to measure peak voltage of the high-frequency analog signal that is provided to a power amplifier in the transmitter. The power amplifier may be turned off while the measurement is performed. This peak voltage may be converted to a digital value that is sent to a processor while the processor provides a digital output to the transmitter (e.g. the digital output may be part of a pattern of test signals) . The processor may also change parameters (e.g. gain) of one or more transmitter components so that peak voltage is sampled for different parameter values. Parameter values (e.g. gain settings) corresponding to a target peak voltage, or target peak voltage range, may then be selected according to the sampling. The target peak voltage may be obtained by consulting a stored relationship between target peak voltage and operating variables (e.g. temperature and process characteristics) . This relationship may be found from characterization of a number of integrated circuits with different operating variables (e.g. testing integrated circuits with different process characteristics over a range of temperatures) .

It is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

FIG. 1 illustrates a wireless network for communicating data. The communication system 100 includes, for example, user equipment 110A-110C, radio access networks (RANs) 120A-120B, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 100.

In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g. 100 or 200 microseconds) , to communicate with the communication devices. In general, a base station may also be used to refer any of the eNB and the 5G BS (gNB) . In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB.

System 100 enables multiple wireless users to transmit and receive data and other content. The system 100 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA) , time division multiple access (TDMA) , frequency division multiple access (FDMA) , orthogonal FDMA (OFDMA) , or single-carrier FDMA (SC-FDMA) .

The user equipment (UE) 110A-110C are configured to operate and/or communicate in the system 100. For example, the user equipment 110A-110C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 110A-110C represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE) , mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA) , smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device.

In the depicted embodiment, the RANs 120A-120B include one or

more base stations

170A, 170B (collectively, base stations 170) , respectively. Each of the base stations 170 is configured to wirelessly interface with one or more of the

UEs

110A, 110B, 110C to enable access to the core network 130, the PSTN 140, the Internet 150, and/or the other networks 160. For example, the base stations (BSs) 170 may include one or more of several well-known devices, such as a base transceiver station (BTS) , a Node-B (NodeB) , an evolved NodeB (eNB) , a next (fifth) generation (5G) NodeB (gNB) , a Home NodeB, a Home eNodeB, a site controller, an access point (AP) , or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network.

In one embodiment, the base station 170A forms part of the RAN 120A, which may include other base stations, elements, and/or devices. Similarly, the base station 170B forms part of the RAN 120B, which may include other base stations, elements, and/or devices. Each of the base stations 170 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell. ” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell.

The base stations 170 communicate with one or more of the user equipment 110A-110C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

It is contemplated that the system 100 may use multiple channel access functionality, including for example schemes in which the base stations 170 and user equipment 110A-110C are configured to implement the Long Term Evolution wireless communication standard (LTE) , LTE Advanced (LTE-A) , and/or LTE Multimedia Broadcast Multicast Service (MBMS) . In other embodiments, the base stations 170 and user equipment 110A-110C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.

The RANs 120A-120B are in communication with the core network 130 to provide the user equipment 110A-110C with voice, data, application, Voice over Internet Protocol (VoIP) , or other services. As appreciated, the RANs 120A-120B and/or the core network 130 may be in direct or indirect communication with one or more other RANs (not shown) . The core network 130 may also serve as a gateway access for other networks (such as PSTN 140, Internet 150, and other networks 160) . In addition, some or all of the user equipment 110A-110C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols.

The RANs 120A-120B may also include millimeter and/or microwave access points (APs) . The APs may be part of the base stations 170 or may be located remote from the base stations 170. The APs may include, but are not limited to, a connection point (an mmW CP) or a base station 170 capable of mmW communication (e.g., a mmW base station) . The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.

Although FIG. 1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 100 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE) , laptop mounted equipment (LME) and USB dongles.

FIG. 2 illustrates example details of an UE 110 that may implement the methods and teachings according to this disclosure. The UE 110 may for example be a mobile telephone but may be other devices in further examples such as a desktop computer, laptop computer, tablet, hand-held computing device, automobile computing device and/or other computing devices. As shown in the figure, the exemplary UE 110 is shown as including at least one transmitter 202, at least one receiver 204, memory 206, at least one processor 208, and at least one input/output device 212. The processor 208 can implement various processing operations of the UE 110. For example, the processor 208 can perform signal coding, data processing, power control, input/output processing, or any other functionality enabling the UE 110 to operate in the system 100 (FIG. 1) . The processor 208 may include any suitable processing or computing device configured to perform one or more operations. For example, the processor 208 may include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

The transmitter 202 can be configured to modulate data or other content for transmission by at least one antenna 210. The transmitter 202 can also be configured to amplify, filter and a frequency convert RF signals before such signals are provided to the antenna 210 for transmission. The transmitter 202 can include any suitable structure for generating signals for wireless transmission.

The receiver 204 can be configured to demodulate data or other content received by the at least one antenna 210. The receiver 204 can also be configured to amplify, filter and frequency convert RF signals received via the antenna 210. The receiver 204 can include any suitable structure for processing signals received wirelessly. The antenna 210 can include any suitable structure for transmitting and/or receiving wireless signals. The same antenna 210 can be used for both transmitting and receiving RF signals, or alternatively, different antennas 210 can be used for transmitting signals and receiving signals.

It is appreciated that one or multiple transmitters 202 could be used in the UE 110, one or multiple receivers 204 could be used in the UE 110, and one or multiple antennas 210 could be used in the UE 110. Although shown as separate blocks or components, at least one transmitter 202 and at least one receiver 204 could be combined into a transceiver. Accordingly, rather than showing a separate block for the transmitter 202 and a separate block for the receiver 204 in FIG. 2, a single block for a transceiver could have been shown.

The UE 110 further includes one or more input/output devices 212. The input/output devices 212 facilitate interaction with a user. Each input/output device 212 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

In addition, the UE 110 includes at least one memory 206. The memory 206 stores instructions and data used, generated, or collected by the UE 110. For example, the memory 206 could store software or firmware instructions executed by the processor (s) 208 and data used to reduce or eliminate interference in incoming signals. Each memory 206 includes any suitable volatile and/or non-volatile storage and retrieval device (s) . Any suitable type of memory may be used, such as random access memory (RAM) , read only memory (ROM) , hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

FIG. 3 illustrates an example BS 170 that may implement the methods and teachings according to this disclosure. As shown in the figure, the BS 170 includes at least one processor 308, at least one transmitter 302, at least one receiver 304, one or more antennas 310, and at least one memory 306. The processor 308 implements various processing operations of the BS 170, such as signal coding, data processing, power control, input/output processing, or any other functionality. Each processor 308 includes any suitable processing or computing device configured to perform one or more operations. Each processor 308 could, for example, include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

Each transmitter 302 includes any suitable structure for generating signals for wireless transmission to one or more UEs 110 or other devices. Each receiver 304 includes any suitable structure for processing signals received wirelessly from one or more UEs 110 or other devices. Although shown as separate blocks or components, at least one transmitter 302 and at least one receiver 304 may be combined into a transceiver. Each antenna 310 includes any suitable structure for transmitting and/or receiving wireless signals. While a common antenna 310 is shown here as being coupled to both the transmitter 302 and the receiver 304, one or more antennas 310 could be coupled to the transmitter (s) 302, and one or more separate antennas 310 could be coupled to the receiver (s) 304. Each memory 306 includes any suitable volatile and/or non-volatile storage and retrieval device (s) .

The technology described herein can be implemented using hardware, software, or a combination of both hardware and software. The software used is stored on one or more of the processor readable storage devices described above to program one or more of the processors to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

In alternative embodiments, some or all of the software can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs) , Application-specific Integrated Circuits (ASICs) , Application-specific Standard Products (ASSPs) , System-on-a-chip systems (SOCs) , Complex Programmable Logic Devices (CPLDs) , special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/storage devices, peripherals and/or communication interfaces.

Figure 4 shows an example of a System on a Chip, SOC 400, that includes transmitter (s) 402 and receiver (s) 404 formed on a common substrate 406. User equipment 110, base station 170, and other such systems may be formed in this way, so that components including transmitters and receivers are formed in an SOC, such as SOC 400. Thus, SOC 400 may be considered an embodiment of user equipment 110 or base station 170. Transmitter (s) 402 may include one or more transmitters and receiver (s) 404 may include one or more receivers that are coupled through transmitter/receiver (T/R) switch 408 to antenna 410. Thus, transmitter (s) 402 and receiver (s) share antenna 410 through switch 408. In other examples, separate antennas may be used by transmitter (s) and receiver (s) with transmitter (s) coupled to a transmitter antenna with receiver (s) coupled to a receiver antenna. Digital baseband processor 412 is coupled to transmitter (s) 402 to provide digital output to transmitter (s) 402 and is coupled to receiver (s) 404 to receive digital outputs from receiver (s) 404. A Universal Asynchronous Receiver Transmitter (UART) 414 and a Serial Peripheral Interface 416 are provided for communication with other components (e.g. components that are not formed on substrate 406 of SOC 400) . A processor 418 performs operations according to software that may be stored in memory 420 (e.g. an operating system, programs, and/or apps stored in a non-volatile memory) . A power management unit, PMU 422, manages power consumption and sensors 424 measure one or more variables such as temperature and/or IC process variables (e.g. variables that may vary from chip-to-chip because of process variation) .

FIG. 5A illustrates exemplary details of a transmitter 502, which can be the transmitter 202 included in the UE 110 (shown in FIG. 2) , the transmitter 302 included in the BS 170 (shown in FIG. 3) , or transmitter (s) 402 of SOC 400 but is not limited thereto. Referring to FIG. 5A, the transmitter 502 is shown as including a Digital-to-Analog Converter (D/A) 506, which converts a digital input (e.g. from processor 208, processor 308, or digital broadband processor 412) into an analog RF signal and provides the RF signal to a Low Pass Filter 508, which filters the RF signal and provides the filtered RF signal to mixer 510. Mixer 510, in addition to receiving the filtered RF signal from Low Pass Filter 508, also receives a local oscillator (LO) signal from local oscillator 531 and adjusts the frequency of the RF signal, e.g. from a first frequency to a second frequency that is higher than the first frequency. More specifically, mixer 510 may be an up-mixer (UP MIX) that frequency up-converts the filtered RF signal from a relatively low frequency (e.g. baseband frequency, or an intermediate frequency (IF) that is offset from the baseband frequency) to a relatively high frequency. Thus, an oscillator signal from local oscillator 531 is used as a carrier signal in transmitter 502. The RF signal from mixer 510 is then amplified by a Power Amplifier Driver (PAD) 512 (pre-amplifier) , and a Power Amplifier (PA) 514 and filtered by a filter 516 before being provided to an RF output 518 (RFout) . For example, RF output 518 may be coupled to an antenna or a coupler but is not limited thereto.

Figure 5B shows an example of how a transmitter 402 may be implemented using Quadrature Phase-Shift Keying (QPSK) on substrate 406 of SOC 400. Digital baseband processor 412 provides digital output to transmitter 550. In this example the digital output of digital baseband processor 412 includes in-phase (I) and quadrature (Q) components. Digital baseband processor 412 operates according to software 552 (e.g. firmware) which may be stored in a memory (e.g. memory 420) and may include instructions to configure digital baseband processor 412 to perform various operations. Digital-to-analog converters (DACs) , DAC 554 and DAC 556, convert I and Q components to low-frequency (e.g. baseband frequency, radio frequency (RF) ) analog signals. Low Pass Filters (LPFs) , LPF 558 and LPF 560 then filter these low-frequency analog signals. The filtered low-frequency analog signals are then provided to mixer 562 and mixer 564. In addition to receiving the filtered low-frequency analog signals from LPF 558 and LPF 560, mixer 562 and mixer 564 also receive local oscillator (LO) signals LO _I and LO _Q for in-phase and quadrature signals respectively and convert the frequencies of the low-frequency analog signals accordingly, e.g. from a first frequency to a second frequency that is higher than the first frequency. More specifically, mixer 562 and mixer 564 may be up-mixers that frequency up-convert the low-frequency analog signals from a relatively low frequency (e.g. baseband frequency, or an intermediate frequency (IF) that is offset from the baseband frequency) to relatively high-frequency analog signals (e.g. above 58GHz, such as unlicensed 60GHz band or 79GHz automotive radar band) . Thus, an oscillator signal from a local oscillator (e.g. local oscillator 531 –not shown in Figure 5B) is used as a carrier signal in transmitter 550. The RF signals from mixer 562 and mixer 564 are combined by adder 568 into a combined high-frequency analog signal that is then amplified by Power Amplifier Driver (PAD) 512 (pre-amplifier) , and Power Amplifier (PA) 514 (filter 516 and certain other components are omitted from Figure 5B for simplicity and clarity) . The output of PA 514 is an amplified high-frequency analog signal that is coupled to antenna 410.

It can be challenging to design a transmitter such as transmitter 550 with a power amplifier such as PA 514 to operate with high output power at high-frequencies (e.g. millimeter-wave frequencies) while achieving good power control and/or Error Vector Magnitude (EVM) because of various factors. Variations in process conditions from chip-to-chip is one example (e.g. substrate 406 may be subject to different process conditions than other substrates going through the same fabrication sequence, which leads to different characteristics of circuits formed on substrate 406 and other substrates) . Variations in parameters such as supply voltage, temperature, frequency, load impedance and aging may also be significant factors. In addition, production screening/testing for high frequency parts (e.g. parts for operation at frequencies greater than 20GHz) is challenging and may require expensive equipment and time to test full performance.

In general, open loop power control with the aid of an external power meter is undesirable. Also closed loop solutions with a detector between a power amplifier (PA) and an antenna to calibrate transmit output power may be affected by changes in load impedance that may result in voltage standing wave ratio (VSWR) causing inaccurate calibration. Couplers may be used to reduce the VSWR impact but area and additional loss at millimeter-wave frequencies may impact transmit efficiency and overall performance. Detector device 1/f noise may impact the calibration accuracy and dynamic range in such systems. Detector gain/responsivity at millimeter-wave frequency may be a significant factor to improve dynamic range. RF loopback to a receiver to monitor output power and EVM at high-frequency (e.g. millimeter-wave frequency) is generally a challenge.

According to examples of the present technology, in-situ calibration can be performed in the field during power-up, reset, idle state, temperature change, and/or in response to other triggering events. A power detector of a self-test circuit may be coupled to an input of a final power amplifier (PA) stage (e.g. PA 514) . The final PA stage generally has fixed gain, so it does not have to be part of a calibration algorithm. Thus, the final PA (e.g. PA 514) stage can be disabled (e.g. powered off) while performing calibration, making this method transparent to a user and to the user’s surroundings. Also, any load impedance variation has no effect on calibration when the PA is disabled. Production screening/testing can be performed by simply checking a DC value from such a detector. No expensive high frequency connectors/cables/calibration are necessary. Detector gain/sensitivity may be improved by taking advantage of differential RF signals. A baseband processor can synthesize different digital modulated signals (different test signals) , which can be upconverted to millimeter-wave frequency by going through the transmit chain (e.g. by mixer 562 and mixer 564. This modulated millimeter-wave signal when going through the detector, shifts the detector output voltage away from 1/f noise levels. To calibrate, the transmitter (TX) analog gain setting may be swept while monitoring the power detector. The final gain settings may be chosen based on a pre-determined power detector output target (e.g. target peak voltage range) . This output target may be based on the characterization of many devices over process, voltage and temperature (PVT) , such that high output power and acceptable EVM are met simultaneously for a wide range of devices over a wide range of conditions. Over-the-air testing to self-check a power calibration algorithm may be performed during production or as part of power calibration step.

Figure 6 shows an example of how aspects of the present technology may be applied to transmitter 550 (transmitter module) formed on substrate 406 using digital baseband processor 412 (processor module) and a self-test circuit 660 (self-test module) that is formed on substrate 406 (i.e. self-test circuit 660 is formed on-chip with transmitter 550 and digital baseband processor 412) . Digital baseband processor 412 generates a digital output including I and Q components as before and transmitter 550 is coupled to receive this digital output from digital baseband processor 412 and generate a high-frequency analog signal from the digital output. Transmitter 550 includes PA 514 to amplify the high-frequency analog signal.

Self-test circuit 660 is coupled to the high-frequency analog signal at the input to PA 514 to generate a digital value according to the high-frequency analog signal. Self-test circuit 660 is also coupled to digital baseband processor 412 to send the digital value to digital baseband processor 412 to calibrate transmitter 550. In particular, self-test circuit 660 includes detector circuit 662, which is coupled to the high-frequency analog signal provided by PAD 512 to PA 514. Detector circuit 662 may be a peak voltage detector that converts the high-frequency analog signal to a direct current (DC) voltage that reflects peak voltage of the high-frequency analog signal and converts the DC voltage to a digital value. Self-test circuit 660 also includes detector circuit 664, which is coupled to the amplified high-frequency analog signal generated by PA 514 (and provided to antenna 410) . Detector circuit 664 may be a peak voltage detector that converts the amplified high-frequency analog signal to another direct current (DC) voltage that reflects peak voltage of the amplified high-frequency analog signal. Additional detector circuits may be coupled to additional nodes of the transmit path and/or the Local Oscillator (LO) path. Multiplexer (MUX) 666 samples the voltages from detector circuit 662, detector circuit 664, and any other detector circuits in self-test circuits 660. These analog voltages are then provided to analog-to-digital converter, ADC 668, which converts the samples to digital values that reflect respective peak voltages. These digital values are provided by self-test circuit 660 to digital baseband processor 412. Using these digital values from detector circuits coupled to different nodes in transmitter 550, digital baseband processor 412 can calibrate components of transmitter 550 to meet one or more requirements such as an EVM requirement.

Figure 6 illustrates communication channel 670 between digital baseband processor 412 and components of transmitter 550, which couples digital baseband processor 412 to control one or more parameters of one or more transmitter components (e.g. one or more parameters of one or more of DAC 554, DAC 556, LPF 558, LPF 560, mixer 562, mixer 564, adder 568, PAD 512, and PA 514) . For example, communication channel 670 may be a command bus, or set of discrete channels that allow digital baseband processor 412 to send commands to components to adjust gain and/or other parameters of components of transmitter 550. In this configuration, digital baseband processor 412 can apply different gain settings in one or more components of transmitter 550 while receiving digital values from self-test circuit 660 according to one or more high-frequency analog signals generated in transmitter 550 (e.g. according to peak voltage at the input of PA 514) . This allows processor 412 to perform a gain sweep (progressing through a sequence of gain settings) while observing resulting changes in peak voltage in a high-frequency analog signal with those gain settings.

Figure 7 shows an example of how local oscillator signals LO _I and LO _Q may be provided to mixer 562 and mixer 564 respectively. In particular, Figure 7 shows a local oscillator 770 configured to generate local oscillator signals and

amplifiers

772, 774, 776, 778 to amplify local oscillator signals for mixer 562 and mixer 564.

Amplifiers

772 and 774 amplify an in-phase local oscillator signal LO _I, which is provided to mixer 562 (which also receives an in-phase low-frequency analog signal I from LPF 558) , while

amplifiers

776 and 778 amplify a quadrature local oscillator signal LO _Q for mixer 564 (which also receives a quadrature low-frequency analog signal Q from LPF 560) .

Detector circuits

782, 784, 786, 788 are coupled to outputs of

amplifiers

772, 774, 776, 778 respectively.

Detector circuits

782, 784, 786, 788 may be peak voltage detectors that convert the high-frequency analog signals LOI and LOQ at outputs of

amplifiers

772, 774, 776, 778 to direct current (DC) voltages that reflect peak voltage of the respective high-frequency analog signals.

Detector circuits

782, 784, 786, 788 may be similar to

detector circuits

662 and 664 and may be considered components of self-test circuits 660.

Detector circuits

782, 784, 786, 788 may be connected to multiplexer 666 to provide DC voltages to multiplexer 666, which are then sampled and converted to digital values by analog-to-digital converter 668 and sent to digital baseband processor 412.

Detector circuits

782, 784, 786, 788 and their connections may be considered components of self-test circuits 660. Also,

amplifiers

772, 774, 776, 778 may be connected to digital baseband processor 412 (e.g. via communication channel 670) so that parameters (e.g. gain) of

amplifiers

772, 774, 776, 778 may be configured by digital baseband processor 412. Thus, digital baseband processor 412 may receive output information from

detector circuits

782, 784, 786, 788 that indicates peak voltage of local oscillator signals at different locations while changing gains of one or more of

amplifiers

772, 774, 776, 778. This allows processor 412 to perform a gain sweep that includes

amplifiers

772, 774, 776, 778. Additional components may be coupled to digital baseband processor 412 to allow control of parameters (e.g. gain) and additional detectors may be provided to detect peak voltage at additional locations.

Figure 8 shows an example of a detector circuit 800, which may be used to implement any of the detector circuits discussed above (

e.g. detector circuit

662, 664, 782, 784, 786, 788 of self-test circuits 660) . Detector circuit 800 includes a differential input 802 coupled to a high-frequency analog signal (such as the high-frequency analog signal at the output of PAD 512 and input of PA 514) . Detector circuit 800 includes capacitors 804 to decouple direct current (DC) from the high-frequency analog signal, and transistors 806, 808 (which may be small Field Effect Transistors, or FETs, e.g. 0.2μm/0.2μm) which receive differential signals from capacitors 804.

Transistors

806, 808 ensure high impedance to reduce effects of RF (i.e. no RF path is provided through detector circuit 800) . A gate bias voltage, Vg, is provided to gates of

transistors

806, 808 through

resistors

810, 812 respectively.

Transistors

806, 808 are connected through

resistors

814, 816 to node 818. Gate bias voltage Vg may be generated by a bias voltage circuit so that gate bias voltage Vg adjusts to track changes to the threshold voltages of

transistors

806, 808 due to device characteristics (e.g. from process variation) , temperature variation, and/or other variation.

Transistors

806 and 808 are coupled to differential input 802 with opposite connections. While transistor 806 has its source coupled to the positive input and its gate coupled to the negative input, transistor 808 has its source coupled to the negative input and its gate coupled to the positive input.

Biasing transistors 806, 808 in the linear/Ohmic region, the drain to source current i _DS with respect to the gate to source and drain to source voltages can be expressed as:

Where transistor parameters of

transistors

806, 808 are as follows: W and L are respectively gate width and length, μ is mobility of electrons, Cox is gate oxide capacitance, V _GS is gate to source voltage (from differential input 802) , V _DS is drain to source voltage, and V _TH is threshold voltage. From this relation, the first term V _GS (t) V _DS (t) and last term

can be used to generate a square-law relation with respect to the incident RF signal by taking advantage of the availability of a differential signal (from differential input 802) . Assuming the differential RF signal, V _RF, at differential input 802 is a sine wave, v _RF (t) =V _RFsin ωt, then:

Digital baseband processor 412 may send an I/Q single tone signal or an I/Q modulated signal which is upconverted to a high-frequency analog signal (RF signal) by an I/

Q mixers

562, 564 and adder 568. The high-frequency analog signal passes through PAD 512 to provide a modulated input signal at differential input 802 of detector circuit 800 so that this modulated input signal has the form v _RF (t) = V _RFsin ωt and the above relationship applies. This modulation allows low frequency 1/f noise to be ignored in the calibration procedure. The second component (sin2ωt component) is filtered out by the low-pass filter formed by

resistors

814, 816 and capacitor C1, leaving the first term

to provide a current at node 818 generated by drain-source currents of

transistors

806, 808. This current is a function of RF signal at differential input 802 (proportional to the square of the peak voltage V _RF) . The current at node 818 results in a corresponding DC voltage at node 818. The DC voltage from node 818 is provided to amplifier 820, which generates an output voltage Vout that is proportional to the DC voltage at node 818. Output voltage Vout may be multiplexed with other similar voltages from other detector circuits (e.g. by MUX 666 of Figure 6) . In some cases, detector circuits include ADCs so that multiplexing of DC voltages is unnecessary. Output voltage Vout is then digitized by analog-to-digital converter ADC 822, which generates a digital value according to Vout. ADC 822 may sample Vout periodically to generate a series of digital values bn... b2, b1, b0, which are sent to a processor such as digital baseband processor 412. This allows digital baseband processor 412 to collect peak voltage data for a high-frequency analog signal at differential input 802 (e.g. at input or output of PA 514, at inputs of mixer 562 and mixer 564, or other locations in transmitter 550) .

In some examples, voltage offset variations in a detector circuit such as detector circuit 800 may be calibrated to improve the accuracy of voltage readings (i.e. to ensure accuracy of digital values bn... b2, b1, b0) . The difference amplifier formed by

transistors

806, 808 may generate an output signal at node 818 that cancels the varying common mode voltage at differential input 802, resulting in an offset voltage that needs to be subtracted. This value may change with device characteristics and temperature. Continuous monitoring across device characteristics and temperature may be used to correct for such variation.

Figure 9A shows an example of a bias voltage generator 900, which may be coupled to provide gate bias voltage Vg for detector circuit 800. Bias voltage generator 900 includes transistors 902, 904 connected to a supply voltage V _DD. Transistors 902, 904 are arranged to form a current mirror with current source 906 providing a reference current Iref along one leg of the current mirror. Reference current Iref may be a constant current or may be a current that is proportional to absolute temperature (PTAT) to correct for temperature effects. A transistor 908 and a resistor 910 are connected in series on the second leg of the current mirror. In this arrangement, the gate voltage Vg of transistor 908 is given by the following equation:

Where Iref is the reference current provided by current source 906, W and L are respectively gate width and length, μ is mobility of electrons, Cox is gate oxide capacitance, and V _TH is threshold voltage of transistor 908, and Rs is the resistance of resistor 910. Transistor 908 and

transistors

806, 808 of detector circuit 800 may have similar transistor parameters (e.g. they may be designed to have identical physical dimensions, materials, etc. so that they have identical, or near-identical characteristics) . Thus, characteristics (e.g. threshold voltage V _TH) of transistor 908 tracks those of

transistors

806, 808 over time so that current source 906 generates gate bias voltage Vg to compensate for changes in characteristics (e.g. changes in V _TH) .

Figure 9B illustrates another example of a bias voltage generator 950, which includes transistors 952, 954 connected between a supply voltage V _DD and ground. Transistors 952, 954 are arranged to form a current mirror with current source 956 providing a reference current Iref along one leg of the current mirror. Reference current Iref may be a constant current or may be a current that is proportional to absolute temperature (PTAT) to correct for temperature effects. A transistor 958 is connected in series with transistor 952 on the second leg of the current mirror. The gate voltage Vg of transistor 958 (which may also be provided as the gate voltage of transistors 806, 808) is controlled by an amplifier 960 which receives a voltage from the source of transistor 958 and receives a reference voltage Vref so that Vg depends on the difference between Vref and the voltage at the source of transistor 958. In this arrangement, the gate voltage Vg of transistor 958 is given by the following equation:

Where Iref is the reference current provided by current source 956, W and L are respectively gate width and length, μ is mobility of electrons, Cox is gate oxide capacitance, and V _TH is threshold voltage of transistor 958. Transistor 958 and

transistors

806, 808 of detector circuit 800 may have similar transistor parameters (e.g. they may be designed to have identical physical dimensions, materials, etc. so that they have identical, or near-identical characteristics) . Reference voltage Vref may be provided by a suitable reference voltage generator. Reference voltage Vref may be a constant voltage or may be a voltage that is configurable to correct for device characteristics and/or environmental variables such as temperature. Gate voltage Vg may be provided as a gate voltage to

transistors

806, 808 so that changes in characteristics (e.g. threshold voltage V _TH) in

transistors

806, 808 also occur in transistor 958 and Vg adjusts for such changes.

Figure 9C illustrates an example of a reference voltage generator 970 that may be used to generate reference voltage Vref for bias voltage generator 950 (reference voltage generator 970 may also provide reference voltage Vref to other circuits) . Reference voltage generator 970 includes device characteristic detector 972, which detects one or more device characteristics of devices formed in an integrated circuit (e.g. characteristics that may vary between individual dies because of process-related variation or other factors) . For example, device characteristic detector 972 may perform testing to determine device speed and/or other device characteristics that may be used to configure individual dies to correct for variation in characteristics between dies. Reference voltage generator 970 includes temperature sensor 974, which detects on-chip temperature (i.e. temperature of a substrate on which temperature sensor 974 is formed, such as substrate 406) . Additional detectors may be provided to detect additional values that may affect device operation. Device characteristic detector 972 and temperature sensor 974 (and any other detectors provided in reference voltage generator 970) provide respective inputs to reference voltage calculator 976, which calculates and generates reference voltage Vref according to the inputs to correct for device characteristics and/or temperature. By correcting for such factors, reference voltage Vref provided to bias voltage generator 950 may correct for device characteristics and/or temperature so that gate voltage Vg generated by bias voltage generator 950 is corrected for device characteristics and/or temperature. Providing such a corrected gate voltage Vg to a detector circuit such as detector circuit 800 allows accurate detection of a parameter such as peak voltage and thereby allows accurate calibration of one or more components of a transmitter such as transmitter 550 for a range of ICs, at different temperatures, and at different stages of wear during a product lifecycle. Reference voltage generator 970, bias voltage generator 950 (or bias voltage generator 900) , and detector circuit 800 may be formed on a common substrate with a transmitter, e.g. on substrate 406 with transmitter 550 so that device characteristics, voltage and temperature are applicable to the transmitter.

Detector circuits coupled to a transmitter may allow one or more transmitter characteristics to be measured, which may be used to calibrate the transmitter. For example, a detector circuit such as detector circuit 800 may be used to measure peak voltage at one or more location in a transmitter such as transmitter 550. Such measurements (e.g. as digital values bn, ... b2, b1, b0 from detector circuit 800) may be provided to a processor such as digital baseband processor 412 and used to calibrate the transmitter (e.g. to calibrate one or more components of transmitter 550) . In addition, such measurements may be used during testing to screen for defective units and/or to categorize ICs according to their characteristics. In some cases, a detector circuit such as detector circuit 800 may provide continuous feedback over an extended period of time to monitor IC performance on a continuous basis. Such continuous monitoring may be implemented, for example, in automotive applications.

Figure 10 illustrates an example method that includes generating a digital output in a processor formed on a substrate 1000 (e.g. digital broadband processor 412 generating digital output such as in-phase and quadrature components provided to transmitter 550 in Figure 6) , generating a high-frequency analog signal from the digital output in a transmitter formed on the substrate 1002, and providing the high-frequency analog signal to a power amplifier on the substrate 1004 (e.g. transmitter 550 generating a high-frequency analog signal and providing it to PA 514) . The method of Figure 10 includes generating a digital value from the high-frequency analog signal provided to the power amplifier 1006 and sending the digital value to the processor to calibrate the transmitter 1008 (e.g. detector circuit 662, implemented as illustrated in Figure 8 or otherwise, generating digital values bn, ... b2, b1, b0 and sending them to digital broadband processor 412 to calibrate transmitter 550) .

Calibration of a transmitter may include gain calibration in which the gain settings of one or more components of a transmitter may be adjusted to obtain a target peak voltage (e.g. peak voltage at the input to a power amplifier such as PA 514 may be adjusted to be at or near a target value) . The gain settings to obtain a given target peak voltage may vary from die to die according to device characteristics and may vary according to conditions such as supply voltage, temperature, or other factors. Individual calibration of such gain settings may reduce differences between dies with different device characteristics and may compensate for voltage, frequency, and temperature variation to allow transmitters formed on different dies to meet one or more requirements while operating over a range of different conditions. Performing calibration using on-chip self-test circuits allows calibration to be performed at different times when external test equipment may not be available (e.g. after a transmitter is incorporated into a product and/or product is in use) . Calibration of a transmitter such as transmitter 550 may be performed while a power amplifier such as PA 514 is turned off so that such calibration may be transparent to a user of the product containing transmitter 550. In general, such a power amplifier (i.e. final power amplifier that provides an output signal to an antenna) has fixed gain so that it need not be included in transmitter calibration. Turning of the final power amplifier during calibration may also ensure that variation in load impedance does not affect calibration.

Figure 11 illustrates an example of a calibration method that includes turning off the power amplifier while generating the calibration data 1100 and varying the gain of one or more transmitter components while generating a digital signal and sending the digital value to the processor to generate calibration data 1102. For example, a processor, such as digital broadband processor 412 may vary gain of one or more of transmitter components: DAC 554, DAC 556, LPF 558, LPF 560, mixer 562, mixer 564, adder 568, PAD 512, and PA 514 via communication channel 670 while generating a digital signal, and while self-test circuit 660 sends digital values bn, ... b2, b1, b0 to digital broadband processor 412 to generate calibration data. The digital signal may be a test signal such as a single tone signal or modulated signal (I/Q single tone or modulated signal) . The calibration method further includes obtaining gain settings of the one or more transmitter components from the calibration data 1104 and applying the gain settings in the one or more transmitter components 1106. For example, gain settings that produce a target peak voltage, or a peak voltage close to a target value (e.g. within a target peak voltage range) may be selected from the calibration data and may be applied to the transmitter components. The method further includes turning on the power amplifier while applying the gain settings in one or more transmitter components 1108. Thus, for example, after calibration of transmitter 550 with PA 514 turned off, PA 514 may be turned on while applying the gain settings for additional calibration and for subsequent use. For example, an over-the-air (OTA) self-check procedure may be performed while applying the gain settings with the PA 514 turned on. Self-check may include digital broadband processor 412 sending test data (e.g. test packets) to transmitter 550, which sends a corresponding high-frequency analog signal from PA 514 to antenna 410. This test data may be received by a receiver formed on the same substrate as the transmitter (e.g. receiver (s) 404 formed on substrate 406) , decoded, and compared with the test data that was sent. In general, the methods illustrated in Figures 10 and 11 may be combined with other testing and calibration procedures (including over-the-air testing) as part of IC testing/calibration and/or product testing/calibration.

The calibration steps of Figure 11 may be performed as a self-calibration routine in response to some triggering event. For example, self-calibration may be performed during product testing (e.g. initial testing in a factory to determine if a product is defective and/or determine basic characteristics of the product) . Self-calibration may be triggered by temperature change (e.g. as detected by temperature sensor 974) so that gain settings are updated to reflect different gain settings found to produce a target peak voltage at different temperatures. Device characteristics may change with use and self-calibration may be triggered by changes in transmitter characteristics from use so that gain settings are updated according to any such changes. Self-calibration may also be performed periodically, i.e. in response to a certain amount of time since the previous self-calibration, or may be triggered by some other triggering event (e.g. at power-on, or reset) .

A transmitter may be expected to meet one or more requirements such as output power or Error Vector Magnitude (EVM) requirements. In general, output power and EVM may be correlated with peak voltage from a detector such as detector 662 at the input of PA 514 so that gain settings may be applied to obtain a target peak voltage (apeak voltage within some desired range) and thereby obtain a target power and/or target EVM (within some acceptable margin) . Gain of one or more transmitter components may be configured accordingly to ensure that power and/or EVM or other metrics fall within a predetermined range under given conditions (e.g. for given process induced device characteristics, supply voltage, and/or temperature) . One or more target peak voltages may be stored on-chip (e.g. on substrate 406) in an appropriate format. For example, target peak voltage for different device characteristics, voltage, and temperature may be recorded as a function (equation) , as a lookup table, or in some other manner (e.g. stored in software 552 of digital baseband processor 412) .

In order to identify target peak voltages for a transmitter, some characterization may be performed to find a correlation between peak voltage and parameters of interest such as output power and EVM, under different conditions (e.g. voltage and temperature) , and for different transmitters (e.g. transmitters on substrates with different device characteristics due to different process-related differences) .

Figure 12 shows an example of test equipment 1220 that may be used to characterize dies to obtain correlations such as a correlation between peak voltage in a transmitter and EVM. Test equipment 1220 allows over-the-air testing and/or self-testing of a die to obtain characterization data. A Die Under Test (DUT) 1222 may be a die such as an SOC (e.g. SOC formed on substrate 406 as illustrated in Figure 4) that includes a transmitter and a peak voltage detector (e.g. transmitter 550 and detector 662 on substrate 406) . DUT 1222 is coupled to test fixture 1224, e.g. wirelessly coupled, and/or coupled via a wired connection such as through an interface such as a test interface, RF coupler, probes contacting pads on DUT 1222, or some other coupling or a combination of such couplings. A power meter 1226 is coupled to test fixture 1224 to measure output power from DUT 1222, e.g. to measure output power at an input and/or output of a final power amplifier such as power amplifier PA 514 and/or output by an antenna such as antenna 410. EVM test equipment 1228 is coupled to test fixture 1224 to receive a high-frequency analog signal from DUT 1222 and to analyze it to measure EVM. Thus, test equipment 1220 allows characterization of both output power and EVM for DUT 1222 (additional test equipment may be used to obtain additional characterization data) . DUT 1222 may go through a series of tests while coupled to power meter 1226 and EVM test equipment 1228. For example, A series of different gain settings may be applied to a transmitter (e.g. transmitter 550) while on-chip self-test circuits (e.g. self-test circuit 660) detect peak voltage at one or more locations and while power meter 1226 and EVM test equipment 1228 measure output power and EVM respectively. This may be repeated for a given DUT at different temperature, supply voltage, and/or other conditions (process, voltage, temperature (PVT) testing) . This testing may be performed for all transmitters to allow individual characterization, or for a representative sample from which characteristics of the overall population may be extracted. For example, a sample of DUTs with different device characteristics may be tested in this way so that different target peak voltages may be found for different dies with different device characteristics. Each DUT may be tested over a range of conditions (e.g. temperature, supply voltage) so that different target peak voltages may be found for different temperatures. Such data may be recorded and used to correlate peak voltage from one or more detectors of self-test circuits with output power and/or EVM. Target peak voltages may then be found for various conditions and die characteristics and may be recorded in a manner that provides access by a processor (e.g. digital broadband processor 412) so that an appropriate target peak voltage may be found for given conditions in a given die (e.g. recorded as an equation, lookup table, or other data structure in software 552 of digital broadband processor 412) . Thus, when on-chip calibration is performed, a processor may record peak voltage over a range of gain settings and choose the gain settings that produce a peak voltage that corresponds to a recorded target peak voltage.

It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

Although the present disclosure has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from scope of the disclosure. The specification and drawings are, accordingly, to be regarded simply as an illustration of the disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present disclosure. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

A circuit, comprising:

a processor to generate a digital output;

a transmitter formed on a substrate, the transmitter coupled to receive the digital output and generate a high-frequency analog signal from the digital output, the transmitter including a power amplifier to amplify the high-frequency analog signal; and

a self-test circuit formed on the substrate, the self-test circuit coupled to the high-frequency analog signal to generate a digital value according to the high-frequency analog signal, the self-test circuit coupled to the processor to send the digital value to the processor to calibrate the transmitter.
The circuit of claim 1 wherein the processor is coupled to control one or more parameters of one or more transmitter components.
The circuit of any of claims 1-2 wherein the transmitter components include: one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal, one or more filters to filter the low-frequency analog signal, and one or more mixers to up-convert the low-frequency analog signal.
The circuit of any one of claims 1-3 wherein the one or more parameters include gain of the one or more of the digital-to-analog converters, the one or more filters, and the one or more mixers and wherein the processor is configured to vary the gain while sampling the digital value.
The circuit of any one of claims 1-4 wherein the processor is configured to select gain settings for the one or more of the digital-to-analog converters, the one or more filters, and the one or more mixers according to results of the sampling.
The circuit of any one of claims 1-5 wherein the processor is configured to turn off the power amplifier to vary the gain while sampling the digital value.
The circuit of any one of claims 1-6 wherein the digital value represents peak voltage of the high-frequency analog signal.
The circuit of any one of claims 1-7 wherein the self-test circuit includes a differential input coupled to the high-frequency analog signal, capacitors to decouple direct current (DC) from the high-frequency analog signal, and transistors coupled to DC voltages from the capacitors.
The circuit of claims 1-8 wherein the self-test circuit further includes a bias voltage circuit to provide a bias voltage to gates of the transistors, the bias voltage adjusted for temperature of the substrate and for device characteristics.
A method, comprising:

generating a digital output in a processor;

generating a high-frequency analog signal from the digital output in a transmitter formed on a substrate;

providing the high-frequency analog signal to a power amplifier on the substrate;

generating a digital value from the high-frequency analog signal provided to the power amplifier; and

sending the digital value to the processor to calibrate the transmitter.
The method of claim 10 wherein the high-frequency analog signal is generated by transmitter components that include: one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal, one or more filters to filter the low-frequency analog signal, and one or more mixers to up-convert the low-frequency analog signal, the method further comprising controlling one or more parameters of one or more transmitter components while generating the digital output and while sending the digital value to the processor.
The method of any one of claims 10-11 wherein the one or more parameters include gain of one or more transmitter components, the method further comprising:

varying the gain of the one or more transmitter components while generating the digital output and sending the digital value to the processor to generate calibration data;

obtaining gain settings of the one or more transmitter components from the calibration data; and

applying the gain settings in the one or more transmitter components.
The method of any one of claims 10-12 wherein the digital value is obtained from peak voltage of the high-frequency analog signal and obtaining the gain settings includes consulting a stored relationship between target peak voltage of the high-frequency analog signal and operating variables of the transmitter.
The method of any one of claims 10-13 wherein the operating variables of the transmitter include temperature and device characteristics.
The method of any of claims 10-14 further comprising:

turning on the power amplifier while applying the gain settings in one or more transmitter components; and

turning off the power amplifier while generating the calibration data.
The method of any of claims 10-15 further comprising, subsequent to turning on the power amplifier and while applying the gain settings, sending a test signal through the transmitter, the power amplifier, and a receiver to check transmitter operation using the gain settings.
The method of any of claims 10-16 wherein varying the gain of the one or more transmitter components, obtaining gain settings, and applying the gain settings are performed as a self-calibration routine in response to at least one of: product testing, temperature change, change in transmitter characteristics from use, and time since previous self-calibration.
A system comprising:

a transmitter formed on a substrate, the transmitter coupled to receive a digital output, the transmitter including:

one or more digital-to-analog converters to convert the digital output to a low-frequency analog signal;

one or more filters to filter the low-frequency analog signal;

one or more mixers to up-convert the low-frequency analog signal to a high-frequency analog signal; and

a power amplifier to amplify the high-frequency analog signal;

a self-test circuit formed on the substrate, the self-test circuit coupled to the high-frequency analog signal to measure peak voltage of the high-frequency analog signal; and

a processor formed on the substrate, the processor configured to generate the digital output and provide the digital output to the transmitter while varying gain of one or more of the digital-to-analog converters, filters, and mixers of the transmitter, and while receiving measured peak voltage from the self-test circuit to obtain a relationship between gain and peak voltage.
The system of claim 18 wherein the processor includes a stored target peak voltage, the processor configured to obtain gain values corresponding to the stored target peak voltage from the relationship between gain and peak voltage and to apply the gain values in the transmitter.
The system of any of claims 18-19 wherein the processor is configured to obtain the relationship between gain and peak voltage in response to at least one of:product testing, temperature change, change in transmitter characteristics from use, and time since previous self-calibration.
A circuit, comprising:

a processor module formed on a substrate to generate a digital output;

a transmitter module formed on the substrate, the transmitter module coupled to receive the digital output and generate a high-frequency analog signal from the digital output, the transmitter module including a power amplifier to amplify the high-frequency analog signal; and

a self-test module formed on the substrate, the self-test module coupled to the high-frequency analog signal to generate a digital value according to the high-frequency analog signal, the self-test module coupled to the processor module to send the digital value to the processor module to calibrate the transmitter module.