CN115208782A - Link state testing method and device and computer readable storage medium - Google Patents
Link state testing method and device and computer readable storage medium Download PDFInfo
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Abstract
The invention provides a link state testing method and device and a computer readable storage medium. Wherein the link state testing method is applied to a first device connected with a second device through a SerDes link group, the SerDes link group including a first SerDes link and a second SerDes link, the testing method comprising: the method includes sending a test signal to the second device through the first SerDes link, and obtaining a feedback signal from the second device through the second SerDes link, and determining an operating state of the set of SerDes links based on the test signal and the feedback signal, wherein the feedback signal is homologous to the test signal. In the embodiment of the invention, the problem hidden danger corresponding to the SerDes link group is found out by determining the working state of the SerDes link group, and the problem reason is not required to be gradually found from the corresponding service logic layer after the SerDes link group has a problem, so that the working load of finding the problem of the SerDes link group can be reduced, and the finding efficiency of the problem of the SerDes link group is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a link state testing method and device and a computer readable storage medium.
Background
Currently, for most hardware devices, in order to match the increasingly expanded communication networks, the design capacity, communication rate and function type of the hardware devices can only be continuously increased, and accordingly, the performance requirement of serial-Deserializer (SerDes) links applied by the hardware devices is higher and higher. Currently, in the industry, with the increasing complexity of products, after a problem occurs in a SerDes link corresponding to hardware, a worker will gradually search for a cause of the problem from a corresponding business logic layer, which consumes a great time cost.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a link state testing method, a device thereof and a computer readable storage medium, which can reduce the workload of searching SerDes link problems and improve the searching efficiency of the SerDes link problems.
In a first aspect, an embodiment of the present invention provides a link status testing method applied to a first device connected to a second device by a serial deserializing SerDes link group, the SerDes link group including a first SerDes link and a second SerDes link, the method including:
transmitting a test signal to the second device over the first SerDes link;
obtaining a feedback signal from the second device over the second SerDes link, wherein the feedback signal is homologous to the test signal;
determining an operating state of the SerDes link set based on the test signal and the feedback signal.
In a second aspect, an embodiment of the present invention further provides a link status testing method applied to a second device connected to a first device through a SerDes link group, where the SerDes link group includes a first SerDes link and a second SerDes link, the method including:
obtaining a test signal transmitted by the first device over the first SerDes link;
sending a feedback signal to the first device over the second SerDes link to cause the first device to determine an operational status of the set of SerDes links from the test signal and the feedback signal, wherein the feedback signal is homologous to the test signal.
In a third aspect, an embodiment of the present invention further provides a first apparatus, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the link state testing method of the first aspect as described above when executing the computer program.
In a fourth aspect, an embodiment of the present invention further provides a second apparatus, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the link state testing method of the second aspect as described above when executing the computer program.
In a fifth aspect, embodiments of the present invention further provide a computer-readable storage medium storing computer-executable instructions for performing the link state testing method according to the first aspect or the second aspect.
The embodiment of the invention comprises the following steps: a link state testing method applied to a first device connected to a second device through a SerDes link group including a first SerDes link and a second SerDes link, the testing method comprising: the method includes sending a test signal to the second device over the first SerDes link, obtaining a feedback signal from the second device over the second SerDes link, and determining an operational state of the set of SerDes links based on the test signal and the feedback signal, wherein the feedback signal is homologous to the test signal. According to the scheme provided by the embodiment of the invention, under the condition that the first device is connected with the second device through the SerDes link group, the test signal is sent to the second device through the first SerDes link, and the feedback signal which is from the second device and is homologous with the test signal is obtained through the second SerDes link, so that the working state of the SerDes link group can be determined according to the test signal and the feedback signal, namely, the working state of the SerDes link group can be determined only based on the related communication detection signal between the two hardware devices, and the problem hidden danger correspondingly existing in the SerDes link group can be found, so that the performance of the SerDes link group and corresponding hardware equipment can be perfected according to the known problem hidden danger, and the problem reason can be gradually found from the corresponding service logic layer after the problem of the SerDes link group occurs, so that the burden of finding problems of workers is reduced, the efficiency of the SerDes link group is improved, and the service performance of the corresponding SerDes link group is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and do not constitute a limitation thereof.
FIG. 1 is a schematic diagram of a test platform for performing a link state test method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a test platform for performing a link state test method according to another embodiment of the invention;
FIG. 3 is a flow chart of a method for link state testing provided by one embodiment of the present invention;
fig. 4 is a flowchart of determining an operating state of a SerDes link group in a link state testing method according to an embodiment of the present invention;
fig. 5 is a flowchart of determining an operating state of a SerDes link group in a link state testing method according to another embodiment of the present invention;
fig. 6 is a flowchart of determining an operating state of a SerDes link group in a link state testing method according to another embodiment of the present invention;
fig. 7 is a flowchart of a link state testing method provided by another embodiment of the present invention in a case where it is determined that a SerDes link group is in an abnormal operating state;
FIG. 8 is a flow chart of a method for link state testing provided by another embodiment of the present invention;
fig. 9 is a flowchart for causing a first device to determine an operating state of a SerDes link group in a link state test method according to an embodiment of the present invention;
FIG. 10 is a flowchart of a link state testing method provided by an embodiment of the invention after acquiring a test signal;
FIG. 11 is a schematic diagram of a first apparatus provided in accordance with an embodiment of the present invention;
fig. 12 is a schematic diagram of a second apparatus provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that although functional blocks are partitioned in a schematic diagram of an apparatus and a logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the partitioning of blocks in the apparatus or the order in the flowchart. The terms first, second and the like in the description and in the claims, as well as in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The invention provides a link state testing method, a device thereof and a computer readable storage medium, wherein under the condition that a first device is connected with a second device through a SerDes link group, a testing signal is sent to the second device through a first SerDes link, and a feedback signal which is from the second device and is homologous with the testing signal is obtained through a second SerDes link, so that the working state of the SerDes link group can be determined according to the testing signal and the feedback signal, namely, the working state of the SerDes link group can be determined only based on a related communication detection signal between two hardware devices, and accordingly, the problem hidden danger of the SerDes link group is found, the performance of the SerDes link group and corresponding hardware equipment is improved conveniently according to the found problem hidden danger, the problem reason of the SerDes link group is found from a corresponding service logic layer after the problem of the SerDes link group occurs is not required to be found, the burden of the problem found by a worker is reduced, the scheme provided by the embodiment of the invention is beneficial to the improvement of the burden of the problem of the working efficiency of the SerDes link group and the service performance of the SerDes link group.
The embodiments of the present invention will be further explained with reference to the drawings.
As shown in fig. 1, fig. 1 is a schematic diagram of a test platform for performing a link state test method according to an embodiment of the present invention.
In the example of fig. 1, a test platform includes, but is not limited to, a first device and a second device, wherein the first device is connected to the second device by a SerDes link set including, but not limited to, a first SerDes link and a second SerDes link, wherein the first SerDes link is for the first device to transmit a downlink signal from the first device to the second device, the second SerDes link is for the first device to receive an uplink signal from the second device to the first device, and the uplink signal is homologous to the downlink signal.
In an embodiment, as shown in fig. 1, the second device may be provided with a plurality of ports, each port being adapted to a corresponding SerDes link, in this case, the first device may be connected to each port in the second device through its corresponding SerDes link, if the connection status of a certain port shows that the port is not connected, the first device cannot connect the port, which indicates that the port cannot adapt to the SerDes link for corresponding testing, and accordingly, the worker may troubleshoot possible faults of the port.
In one embodiment, as shown in fig. 1, a port of a first device can be matched with a corresponding port of a second device to facilitate chaining to enable the first device to connect with the second device over a set of SerDes links.
In an embodiment, the first device may be, but not limited to, various types of line cards, and the line cards, when connected to the second device, can provide operating conditions such as a power supply, a clock driver, and the like for the second device, where a link test chip is integrated in the line cards, and the link test chip is connected to the second device through a SerDes link for implementing state detection on the SerDes link, and the type of the link test chip is not limited in this embodiment, and various types of ethernet switch chips may be used, for example, a blocom (broadcast modem, BCM) chip manufactured by blosson corporation, or the link test chip may be selected according to the SerDes link in practical applications.
In an embodiment, the second device may include, but is not limited to, various types of hardware devices with communication capability, which may be integrated and adapted to electronic devices or systems, such as controllers, computers, controller systems, computer systems, and the like, for example, the second device may be a Daughter card (Daughter Board) attached to a computer adapter card, the Daughter card does not need to match a slot contact design on the computer motherboard, but transmits related signals through contact points with the mother card, and the types of the Daughter card may include, but are not limited to, a Moving Picture Experts Group (MPEG) Daughter card, a capture Daughter card, a tv tuner Daughter card, and the like, and the Daughter card may be selected as a Daughter card carrying a CPU or a Daughter card not carrying a CPU according to actual situations, which is not limited in this embodiment.
In an embodiment, the second device is provided with a signal conditioning chip, through which the uplink signal in the second SerDes link can be further subjected to signal equalization and enhancement, so that the first device can obtain a more stable and reliable uplink signal, wherein a specific type of the signal conditioning chip may be set according to an actual situation of the uplink signal, for example, a Retimer (Retimer) chip is provided to increase transmission energy of the uplink signal, so as to perform clock reconstruction extension on the uplink signal, or a driver (Redriver) chip is provided to improve communication quality of the uplink signal, and the like, which is not limited in this embodiment.
In the example of fig. 1, the test platform may further include, but is not limited to, a third device (not shown), and the set of SerDes links may further include, but is not limited to, a third SerDes link and a fourth SerDes link, the second device being connected to the third device via the third SerDes link and the fourth SerDes link, wherein the third SerDes link allows the second device to transmit a downlink signal from the second device to the third device, the fourth SerDes link allows the second device to obtain an uplink signal from the third device to the second device, and the uplink signal and the downlink signal may be set to be homologous; the third device may match the second device to act as a load for the second device, in which case the third device may be configured to transmit only the associated communication signals to assist in performing a status test of the SerDes link set, without involving a specific determination of the status of the SerDes link set.
In an embodiment, the third apparatus may include, but is not limited to, various types of optical module holders and their sets, or simulated optical module holders obtained by simulating optical module holders and their sets, generally speaking, different optical module holders satisfy different communication protocols, and therefore, in order to match a communication protocol that can be applied by the second apparatus, an optical module holder matched therewith may be correspondingly set, which is not limited in this embodiment.
It should be noted that, for example, a set of a plurality of optical module fixtures is adopted for the third device, since the optical module fixtures and the second device may be matched in a manner that each port is correspondingly matched, that is, only corresponding ports are required to be ensured to match the optical module fixtures with the second device, in addition to selecting a single optical module fixture to match with the second device, a plurality of suitable optical module fixtures may also be selected to match with the second device, for example, the second device has 20 ports to be matched, in one case, if a certain optical module fixture also has at least 20 corresponding ports to match, the third device only needs to set the optical module fixture, in another case, if one optical module fixture has 15 corresponding ports and another optical module fixture has 5 corresponding ports, the third device may set two optical modules as shown above at the same time, and as a whole, the effect of matching with the second device can also be achieved.
In an embodiment, when performing a link status test, the third device may be matched with a corresponding port of the second device to implement a test, and a SerDes parameter of the third device may be configured to match the SerDes parameter with a corresponding port of the second device, if the parameter configuration fails, it may be determined that the third device or the corresponding port of the second device has a failure problem, and it may be confirmed by replacing the third device or the corresponding port of the second device, and it is understood that in this way, the second device and the third device can perform an adaptation test more easily, so as to meet the test requirement, where the SerDes parameter is a hardware parameter known to those skilled in the art, and for different third devices, the SerDes parameter may be set accordingly, such as a port rate, a serial data parameter, a serial clock parameter, a two-wire serial parameter, and the like, which is not limited in this embodiment.
In an embodiment, when the port rate of the second device is initially configured, in order to match the port rate with the third device, the port rate may be set to the maximum port rate, and if the port rate can be matched, it indicates that the port rate can also be matched with the third device at a corresponding rate smaller than the maximum port rate.
Fig. 2 is a schematic diagram of a test platform for performing a link state test method according to another embodiment of the present invention, as shown in fig. 2.
In the example of fig. 2, the test platform includes, but is not limited to, a first device and a second device, wherein the first device is connected to the second device via a SerDes link set including, but not limited to, a first SerDes link and a second SerDes link, wherein the first SerDes link is used for the second device to obtain a downlink signal from the first device to the second device, the second SerDes link is used for the second device to transmit an uplink signal from the second device to the first device, and the uplink signal is homologous to the downlink signal, in which case, the corresponding link status test can be achieved by a combination of the uplink signal and the downlink signal.
In one embodiment, as shown in fig. 2, a port of a first device can be matched with a corresponding port of a second device to facilitate establishment of a link to enable the first device to connect with the second device through a SerDes link set.
In an embodiment, the second device is provided with a Programmable logic chip, which has a test capability, and the working state of the first SerDes link can be obtained through the Programmable logic chip, so as to accurately know the working state of the first SerDes link and the uplink signal, where a specific type of the Programmable logic chip may be set according to an actual situation of the uplink signal, for example, the Programmable logic chip may be a Field Programmable Gate Array (FPGA) chip, or a Programmable logic chip with a similar function, which is not limited in this embodiment.
In the example of fig. 2, the test platform may further include, but is not limited to, a third device, and the SerDes link group may further include, but is not limited to, a third SerDes link and a fourth SerDes link, the second device being connected to the third device through the third SerDes link and the fourth SerDes link, wherein the third SerDes link may allow the second device to transmit a downlink signal from the second device to the third device, the fourth SerDes link may allow the second device to acquire an uplink signal from the third device to the second device, and the uplink signal and the downlink signal may be set to be homologous, in which case, a corresponding link status test may be achieved through a combination of the uplink signal and the downlink signal.
It should be noted that the test platform and the application scenario described in the embodiment of the present invention are for more clearly illustrating the technical solution of the embodiment of the present invention, and do not constitute a limitation to the technical solution provided in the embodiment of the present invention, and it is known to those skilled in the art that the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems along with the evolution of the test platform and the appearance of a new application scenario.
It will be appreciated by those skilled in the art that the configuration of the test platform shown in fig. 1 or 2 is not intended to limit embodiments of the present invention and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.
In the test platform shown in fig. 1 or fig. 2, the first device or the second device may call the link state test program stored therein respectively to execute the link state test method.
Based on the structure of the test platform, the invention provides various embodiments of the link state test method.
As shown in fig. 3, fig. 3 is a flowchart of a link state testing method according to an embodiment of the present invention, which may be applied to the first device in the testing platform according to the embodiment shown in fig. 1, where the testing method includes, but is not limited to, step S100, step S200, and step S300.
Step S100 transmits a test signal to the second device through the first SerDes link.
In an embodiment, the test signal may be set in any form as long as it can be transmitted in the first SerDes link to the second device, for example, the test signal may be set in the form of a digital code, a character string, a graphic scene, and the like, the digital code may be set randomly or fixedly, the length and size of the character string may be set variably, and the range of the graphic scene may also be set accordingly, which is not limited in this embodiment.
In one embodiment, before sending the test signal to the second device through the first SerDes link, the first device and the second device may be initialized, and the historical signal data of the first device and the second device is cleared through the initialization operation, so as to prevent the historical signal data of the first device and the second device from generating interference influence on the link state test, avoid causing larger link state test errors, and facilitate improving the accuracy of the link state test.
In an embodiment, the test signal may be sent in a form of a digital code, for example, a Pseudo-Random Binary Sequence (PRBS), and the PRBS is sent as the test signal, and can test a real-time status of the first SerDes link as a high-speed serial channel.
Step S200, a feedback signal from the second device is acquired over the second SerDes link, wherein the feedback signal is homologous to the test signal.
And step S300, determining the working state of the SerDes link group according to the test signal and the feedback signal.
In an embodiment, the feedback signal is a homologous signal with the test signal, so that basic signal functions and properties of the feedback signal and the test signal are corresponding, and corresponding differences between the two and state updates caused by the differences are both caused during link transmission, and specifically, since the test signal is transmitted through the first SerDes link and the feedback signal is transmitted through the second SerDes link, differences between the feedback signal and the test signal and state updates caused by the differences are caused based on the first SerDes link and the second SerDes link, the working state of the SerDes link set can be directly determined through the test signal and the feedback signal, so that potential problems existing in the SerDes link set can be found, performance of the SerDes link set and corresponding hardware equipment is improved according to the found potential problems, and the service problem of the SerDes link set can be found step by step from a service logic layer corresponding to the SerDes link set without waiting until the SerDes link set has problems, so that a worker can understand the problem, the efficiency of the SerDes link set can be improved in comparison with the conventional method, and the working efficiency of finding the SerDes link set can be improved.
It is understood that the homology of the feedback signal with the test signal means that the test signal and the feedback signal are from the same source, i.e., the feedback signal is substantially formed after the test signal passes through the link transmission, i.e., the feedback signal can be obtained after the test signal passes through the first SerDes link, the second device and the second SerDes link in sequence, so that the basic signal functions and properties of the feedback signal and the test signal are corresponding, the corresponding differences between the two and the status update caused by the differences are caused by the link transmission, and therefore, the operating status of the SerDes link set can be determined based on the two signals.
In an embodiment, the link status testing method may be further applied to the first device in the testing platform of the embodiment shown in fig. 2, in which case, the test signal is further transmitted to the third device through the second device and fed back, that is, the feedback signal may be obtained after the test signal sequentially passes through the first SerDes link, the second device, the third SerDes link, the third device, the fourth SerDes link, the second device and the second SerDes link, so that the working status of a SerDes link group composed of the first SerDes link, the second SerDes link, the third SerDes link and the fourth SerDes link may be determined through the test signal and the feedback signal, thereby finding out a problem hidden trouble corresponding to the SerDes link group, and further facilitating improvement of the usability of the second device corresponding to the whole SerDes link group.
Further, as shown in fig. 4, step S300 includes, but is not limited to:
step S310, determining error code parameters corresponding to the SerDes link group according to the test signal and the feedback signal;
step S320, the working state of the SerDes link group is determined according to the error code parameters.
In one embodiment, the error parameter is used to indicate the accuracy of data transmission within the SerDes link group over a certain time period, and the error parameter is determined by the test signal and the feedback signal, i.e., the data transmission status of the SerDes link group can be determined, and the operating status thereof can be accurately and reliably determined by determining the data transmission status.
In an embodiment, before determining the error code parameter corresponding to the SerDes link group according to the test signal and the feedback signal, it is further required to determine that the SerDes link group is in a locked state according to the test signal and the feedback signal, that is, it is determined that the SerDes link group can perform normal data transceiving, which is a small premise of acquiring the error code parameter, otherwise, if the SerDes link group is in an unlocked state, it can be directly determined that the SerDes link group is in an abnormal working state, so that a determination process of the working state of the SerDes link group can be optimized by setting the detection of the locked state, and it is more convenient to determine the working state of the SerDes link group.
Specifically, as shown in fig. 5, step S320 includes, but is not limited to:
step S321, determining that the SerDes link group is in an abnormal operating state when the error code parameter is greater than the error code threshold.
In an embodiment, when the error code parameter is greater than the error code threshold, it indicates that the error code data corresponding to the SerDes link group exceeds the error code data amount in the normal state, and it indicates that the data transmission accuracy in the SerDes link group does not reach the standard corresponding to the error code threshold, so that it can be determined that the SerDes link group is in the abnormal working state.
In an embodiment, the error code threshold may be preset, and for those skilled in the art, the error code threshold may be set according to a corresponding formula, which is common in the art, and therefore, the details thereof are not described herein.
Specifically, as shown in fig. 6, step S320 further includes, but is not limited to:
step S322, under the situation that the error code parameter is less than or equal to the error code threshold, confirm that SerDes periodic line group is in the normal operating condition.
In an embodiment, when the error code parameter is less than or equal to the error code threshold, it indicates that the error code data corresponding to the SerDes link group is within the range of the error code data amount in the normal state, and it indicates that the data transmission accuracy in the SerDes link group has reached the standard corresponding to the error code threshold, so that it can be determined that the SerDes link group is in the normal operating state.
Further, as shown in fig. 7, in the case where it is determined that the SerDes link group is in the abnormal operation state according to step 321, there are further included, but not limited to, step S400 and step S500.
Step S400, acquiring working parameters of the SerDes link group and working parameters of the second device;
and step S500, determining the reason of the SerDes link group in the abnormal working state according to the working parameters of the SerDes link group and the working parameters of the second device.
In an embodiment, when it is determined that the SerDes link group is in the abnormal operating state, the working parameters of the SerDes link group and the working parameters of the second device may be obtained, and the obtained parameters may be analyzed accordingly, so as to further determine the reason that the SerDes link group is in the abnormal operating state, and further facilitate a worker to adjust or update the SerDes link group according to the determined reason, so as to finally return the SerDes link group to the normal operating state.
In one embodiment, the operational parameters of the SerDes link set include, but are not limited to: the transmission data parameters of the first SerDes link and the transmission data parameters of the second SerDes link, etc., specifically, the transmission data parameters may be transmission rate, transmission range, total amount of transmission data, eye width and eye height of an eye pattern, etc., and the operating parameters of the second device include, but are not limited to: the hardware environment parameters (e.g., including temperature, humidity, etc.) and the hardware internal parameters (e.g., including heat dissipation capacity, throughput, etc.) of the second device are not limited in this embodiment.
In one embodiment, if the cause of the SerDes link group in the abnormal operating state can be determined by one of the operating parameters of the SerDes link group and the operating parameters of the second device, another parameter may not be acquired, that is, only the operating parameters of the SerDes link group or the operating parameters of the second device need to be acquired, which can reduce the execution difficulty of the step flow of this embodiment in the corresponding situation.
As shown in fig. 8, fig. 8 is a flowchart of a link state testing method according to another embodiment of the present invention, which may be applied to the second device in the testing platform according to the embodiment shown in fig. 2, where the testing method includes, but is not limited to:
step S600, acquiring a test signal transmitted by the first device through the first SerDes link;
step S700, a feedback signal is sent to the first device through the second SerDes link, so that the first device determines the operating state of the SerDes link group according to the test signal and the feedback signal, where the feedback signal is homologous to the test signal.
In an embodiment, when a test signal is obtained, a feedback signal is directly sent to a first device, and in this case, the feedback signal is obtained by the test signal passing through a first SerDes link, a second device and a second SerDes link, so that the first device directly determines the working state of the SerDes link group through the test signal and the feedback signal, thereby finding out a problem hidden trouble corresponding to the SerDes link group, so as to perform performance improvement on the SerDes link group and corresponding hardware equipment according to the found problem hidden trouble, and does not need to gradually find a problem cause from a corresponding service logic layer after the SerDes link group has a problem, thereby reducing a burden of a worker on finding the problem.
In an embodiment, the feedback signal may also be obtained by passing a test signal through the first SerDes link, the second device, the third SerDes link, the third device, the fourth SerDes link, the second device, and the second SerDes link in sequence, so that the working state of a SerDes link group composed of the first SerDes link, the second SerDes link, the third SerDes link, and the fourth SerDes link can be determined through the test signal and the feedback signal, thereby finding out a problem and a hidden danger corresponding to the SerDes link group, and further facilitating improvement of the service performance of the second device corresponding to the whole SerDes link group.
As shown in fig. 9, step S700 includes, but is not limited to:
step S710, sending a feedback signal to the first device through the second SerDes link, so that the first device obtains a first error code parameter according to the test signal and the feedback signal, and the first device determines a working state of the SerDes link group according to the first error code parameter.
In one embodiment, the error parameter is used to indicate the accuracy of data transmission within the SerDes link group over a certain time period, so that the first device can determine the error parameter through the test signal and the feedback signal, i.e., can determine the data transmission status of the SerDes link group, and further determine the operating status thereof accurately and reliably by determining the data transmission status.
Furthermore, as shown in fig. 10, after step S600, the test method further includes, but is not limited to:
step S800, determining a second error code parameter corresponding to the first SerDes link according to the test signal and a preset test reference signal;
and step S900, determining the working state of the first SerDes link according to the second error code parameter.
In an embodiment, since the second device has a programmable logic function, for example, the second device is provided with an FPGA chip, after the test signal sent by the first device through the first SerDes link is obtained, the second error code parameter can be further determined according to the test signal and the preset test reference signal, and the working state of the first SerDes link is determined based on the second error code parameter, that is, the second device can determine the working state of the first SerDes link, which is equivalent to that a test is performed for a plurality of times on the basis of the test performed by the first device.
It should be noted that, if the SerDes links corresponding to the ports of the second device are adapted to different chips, the link tests for specific ports may be performed in a corresponding manner, for example, if the first port and the second port of the second device are adapted to the FPGA chip and the timer chip, the working state of the SerDes link may be determined by the second device and the first device at the same time for the SerDes link of the first port, while the working state of the SerDes link may not be determined by the second device itself but only by the first device for the SerDes link of the second port.
In an embodiment, the test reference signal may be preset by a user, or may be set by the second apparatus according to an actual test signal, or set in other similar manners, which is not limited in this embodiment.
Specifically, step S900 further includes, but is not limited to:
step S910, determining that the first SerDes link is in an abnormal working state when the second error code parameter is greater than the error code threshold.
And, step S900 further includes, but is not limited to:
step S920, determining that the first SerDes link is in a normal working state when the second error code parameter is less than or equal to the error code threshold.
Further, in the event that it is determined from step 910 that the first SerDes link is in an abnormal operating state, the testing method further includes, but is not limited to:
step S1000, acquiring working parameters of the first SerDes link and working parameters of the second device;
step S1100, determining the reason why the first SerDes link is in an abnormal operating state according to the operating parameters of the first SerDes link and the operating parameters of the second device.
It should be noted that, since the embodiments shown in steps 910, 920 and 1000 to 1100 belong to the same inventive concept as the embodiments shown in steps S321, S322 and S400 to S500, the specific embodiments of the embodiments shown in steps 910, 920 and 1000 to 1100 may refer to the specific embodiments of the embodiments shown in steps S321, S322 and S400 to S500, and the specific embodiments of the embodiments shown in steps 910, 920 and 1000 to 1100 are not repeated herein to avoid redundancy.
In addition, referring to fig. 11, an embodiment of the present invention provides a first apparatus 100, the first apparatus 100 including: a first memory 110, a first processor 120, and a computer program stored on the first memory 110 and executable on the first processor 120.
The first processor 120 and the first memory 110 may be connected by a first bus or other means.
It should be noted that the first apparatus 100 in this embodiment may be applied to the test platform in the embodiment shown in fig. 1 or fig. 2, and the first apparatus 100 in this embodiment can form a part of the test platform in the embodiment shown in fig. 1 or fig. 2, and these embodiments all belong to the same inventive concept, so these embodiments have the same implementation principle and technical effect, and are not described in detail here.
Non-transitory software programs and instructions required to implement the link state testing method of the above-described embodiment are stored in the first memory 110, and when executed by the first processor 120, perform the link state testing method of the above-described embodiment, for example, performing the above-described method steps S100 to S300 in fig. 3, method steps S310 to S320 in fig. 4, method step S321 in fig. 5, method step S322 in fig. 6, or method steps S400 to S500 in fig. 7.
In addition, referring to fig. 12, an embodiment of the present invention provides a second apparatus 200, the second apparatus 200 including: a second memory 210, a second processor 220, and a computer program stored on the second memory 210 and executable on the second processor 220.
The second processor 220 and the second memory 210 may be connected by a second bus or other means.
It should be noted that the second apparatus in this embodiment may be applied to the test platform in the embodiment shown in fig. 1 or fig. 2, the first apparatus in this embodiment can form a part of the test platform in the embodiment shown in fig. 1 or fig. 2, and these embodiments all belong to the same inventive concept, so these embodiments have the same implementation principle and technical effect, and will not be described in detail here.
Non-transitory software programs and instructions required to implement the link state testing method of the above-described embodiment are stored in the second memory 210, and when executed by the second processor 220, perform the link state testing method of the above-described embodiment, for example, performing the above-described method steps S600 to S700 in fig. 8, method step S710 in fig. 9, method steps S800 to S900 in fig. 10, method steps S910 to S920, or method steps S1000 to S1100.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions, which are executed by a processor or a controller, for example, by a processor in the node embodiment, and can enable the processor to execute the link status testing method in the node embodiment, for example, execute the method steps S100 to S300 in fig. 3, the method steps S310 to S320 in fig. 4, the method step S321 in fig. 5, the method step S322 in fig. 6, the method steps S400 to S500 in fig. 7, the method steps S600 to S700 in fig. 8, the method step S710 in fig. 9, the method steps S800 to S900 in fig. 10, the method steps S910 to S920, or the method steps S1000 to S1100 described above.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as is well known to those skilled in the art.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.
Claims (13)
1. A link-state testing method applied to a first device connected to a second device by a serially deserializing SerDes link set, the SerDes link set comprising a first SerDes link and a second SerDes link, the method comprising:
transmitting a test signal to the second device over the first SerDes link;
acquiring a feedback signal from the second device over the second SerDes link, wherein the feedback signal is homologous to the test signal;
determining an operating state of the SerDes link set based on the test signal and the feedback signal.
2. The link state testing method of claim 1, wherein determining the operational state of the SerDes link group from the test signal and the feedback signal comprises:
determining error code parameters corresponding to the SerDes link group according to the test signal and the feedback signal;
and determining the working state of the SerDes link group according to the error code parameter.
3. The method according to claim 2, wherein said determining the operational status of the SerDes link group based on the error parameter comprises:
determining that the SerDes link group is in an abnormal working state under the condition that the error code parameter is greater than an error code threshold value;
determining that the SerDes link group is in a normal operating state if the error parameter is less than or equal to an error threshold.
4. The link state testing method of claim 3, wherein if it is determined that the SerDes link group is in an abnormal state, the method further comprises:
acquiring working parameters of the SerDes link group and working parameters of the second device;
according to the operating parameters of the SerDes link group and the second device
Determining a cause of the SerDes link group being in an abnormal operating state.
5. The method according to claim 1, wherein the SerDes link set further comprises a third SerDes link and a fourth SerDes link, the second device is connected to a third device through the third SerDes link and the fourth SerDes link, and the feedback signal is obtained after the test signal passes through the first SerDes link, the second device, the third SerDes link, the third device, the fourth SerDes link, the second device and the second SerDes link in sequence.
6. A link status testing method applied to a second device connected with a first device through a SerDes link set including a first SerDes link and a second SerDes link, the method comprising:
obtaining a test signal transmitted by the first device over the first SerDes link;
sending a feedback signal to the first device over the second SerDes link to cause the first device to determine an operational status of the set of SerDes links from the test signal and the feedback signal, wherein the feedback signal is homologous to the test signal.
7. The method according to claim 6, wherein the sending a feedback signal to the first device over the second SerDes link to cause the first device to determine an operational status of the set of SerDes links from the test signal and the feedback signal comprises:
sending a feedback signal to the first device through the second SerDes link, so that the first device obtains a first error code parameter according to the test signal and the feedback signal, and the first device determines the working state of the SerDes link group according to the first error code parameter.
8. The method according to claim 6, further comprising, after obtaining the test signal transmitted by the first apparatus over the first SerDes link:
determining a second error code parameter corresponding to the first SerDes link according to the test signal and a preset test reference signal;
determining an operating state of the first SerDes link based on the second error code parameter.
9. The method according to claim 8, wherein determining the operational status of the first SerDes link based on the second error parameter comprises:
determining that the first SerDes link is in an abnormal working state under the condition that the second error code parameter is larger than an error code threshold value;
determining that the first SerDes link is in a normal operating state if the second error parameter is less than or equal to an error threshold.
10. The link state testing method of claim 9, wherein in the event that it is determined that the first SerDes link is in an abnormal operating state, the method further comprises:
obtaining operating parameters of the first SerDes link and operating parameters of the second device;
determining a cause of the first SerDes link being in an abnormal operating state based on the operating parameters of the first SerDes link and the operating parameters of the second device.
11. A first device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the link state testing method according to any of claims 1 to 5 when executing the computer program.
12. A second apparatus, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the link state testing method according to any one of claims 6 to 10 when executing the computer program.
13. A computer-readable storage medium storing computer-executable instructions for performing the link state testing method of any one of claims 1 to 5, or performing the link state testing method of any one of claims 6 to 10.
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| CN202110377293.5A CN115208782A (en) | 2021-04-08 | 2021-04-08 | Link state testing method and device and computer readable storage medium |
| PCT/CN2022/075681 WO2022213719A1 (en) | 2021-04-08 | 2022-02-09 | Link state test method and apparatus therefor, and computer-readable storage medium |
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| CN116070560A (en) * | 2022-12-30 | 2023-05-05 | 成都电科星拓科技有限公司 | Chip small batch limit condition construction and verification architecture |
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| CN107844390A (en) * | 2016-09-19 | 2018-03-27 | 乐视控股（北京）有限公司 | A kind of method and device of automatic test feedback |
| CN108737204A (en) * | 2017-04-18 | 2018-11-02 | 阿里巴巴集团控股有限公司 | A kind of acquisition method and communication terminal of network performance information |
| CN107528631B (en) * | 2017-08-31 | 2019-12-10 | 武汉虹信通信技术有限责任公司 | link error code detection and diagnosis method and device based on digital optical fiber distribution system |
| CN112585927A (en) * | 2020-04-30 | 2021-03-30 | 深圳市大疆创新科技有限公司 | Communication link detection method, device and system and movable platform |
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| CN116070560A (en) * | 2022-12-30 | 2023-05-05 | 成都电科星拓科技有限公司 | Chip small batch limit condition construction and verification architecture |
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