CN115208516A - Data storage and verification method based on CRC (Cyclic redundancy check) code - Google Patents
Data storage and verification method based on CRC (Cyclic redundancy check) code Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention discloses a data storage and check method based on CRC check codes, belonging to the technical field of data, wherein the storage method comprises the following steps: sequentially storing the information data in the information bits of each storage word length; respectively calculating the information data stored in the information bits in each storage word length, and respectively storing the generated inner check codes in the inner check bits; and calculating the information data in the data block, and storing the generated outer check code in the outer check bit. The checking method comprises the following steps: reading information data and an outer check code in the data block and performing CRC (cyclic redundancy check); judging whether the verification passes, if so, ending, otherwise, executing error correction processing; reading information data of each storage word length and an inner side check code in a data block and carrying out CRC (cyclic redundancy check); judging whether the check is passed, if so, reading the next storage word length, and otherwise, correcting errors; and carrying out error correction processing according to a preset error correction table. The invention effectively improves the checking efficiency in the information data transmission through the setting of the double checking codes.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a data storage and verification method based on a CRC (Cyclic redundancy check) code.
Background
With the development of information technology, the storage and transmission requirements of various industries for data are exponentially increased. In the control field, the requirements on data storage accuracy, integrity and safety are particularly high. Based on the increase of the MCU data processing capacity and the data space, various verification methods appear in the industry, but the requirements cannot be met accurately.
The conventional CRC check is mostly used for error detection and error correction of 1-bit data errors, and also used for 2-bit CRC data error correction in data transmission, but generally used for low-bit error detection and error correction. The transmission data uses cyclic redundancy (n, k) codes, error detection is easy to realize, but error correction capability is not easy to realize and multi-bit error correction is more difficult to realize due to n > > k. By looking up the table for error correction, the multi-bit error table is very large and the computer needs to spend space and time processing the error data.
Disclosure of Invention
Aiming at the problem that a computer needs to consume more time and space to check information data in the data storage and transmission process in the prior art, the invention aims to provide a data storage and check method based on a CRC check code.
In order to realize the purpose, the technical scheme of the invention is as follows:
in a first aspect, the present invention provides a data storage method based on CRC check codes, where the method is used to store information data in a data block in a storage unit, where the data block includes an outer check bit and a plurality of storage word lengths that are set in sequence, and each storage word length includes an information bit for storing the information data and an inner check bit for storing an inner check code; the method comprises the following steps:
s1, sequentially storing information data in information bits of each storage word length;
s2, calculating the information data stored in the information bits in each storage word length respectively based on a first operation rule, and storing the inner check codes generated by calculation in the inner check bits of each storage word length respectively;
and S3, calculating the information data stored in the data block based on a second operation rule, and storing an outer check code generated by calculation in the outer check bit.
Preferably, the information bits and the inner parity bits have the same number of bits.
Preferably, the memory word is 8 bits, 16 bits or 32 bits in length.
Preferably, the outer parity bit is arranged at the tail of the data block.
Preferably, the storage unit is a flash EEPROM memory.
Preferably, the first operation rule and the second operation rule are CRC16_ XMODEM, CRC16_ USB, or CRC16_ MODBUS.
In a second aspect, the present invention further provides a data checking method based on CRC check codes, configured to check information data read from a data block of a storage unit, where the information data is stored in the data block according to the method described above, and the method includes the following steps:
s10, reading information data and an outer check code stored in a data block, and performing CRC (cyclic redundancy check) on the data block based on a second operation rule;
and S20, judging whether the check is passed or not, if so, ending, and otherwise, executing error correction processing.
Further, the error correction process includes the steps of:
s30, sequentially reading the information data and the inner check code stored in each storage word length in the data block, and performing CRC (cyclic redundancy check) on the storage word lengths based on a first operation rule after each storage word length is read;
s40, judging whether the check is passed, if so, reading the next storage word length, and otherwise, correcting the current storage word length;
and S50, carrying out error correction processing on the information data stored in the information bits in the current storage word length according to a preset error correction table.
Preferably, the error correction table is a 1-bit error correction table or a multi-bit error correction table.
By adopting the technical scheme, the invention has the beneficial effects that: the invention realizes the error detection and correction of long-byte information by increasing the check digit based on the CRC method, and realizes the double check of long-byte information by adding a new CRC check digit at the tail part of the data block; and a corresponding verification strategy is formulated aiming at the double verification mode, so that the calculation efficiency is ensured, and the high-efficiency execution of the verification is ensured.
Drawings
FIG. 1 is a flow chart of a data storage method based on CRC codes according to the present invention;
FIG. 2 is a schematic structural diagram of a flash EEPROM memory according to an embodiment of the present invention;
fig. 3 is a flowchart of a data checking method based on CRC check codes according to the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
It should be noted that, in the description of the present invention, the terms "upper", "lower", "left", "right", "front", "rear", and the like indicate orientations or positional relationships that are used for explaining structures of the present invention based on the drawings, and are only for convenience of describing the present invention, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the technical scheme, the terms "first" and "second" are only used for referring to the same or similar structures or corresponding structures with similar functions, and are not used for ranking the importance of the structures, or comparing the sizes or other meanings.
In addition, unless expressly stated or limited otherwise, the terms "mounted" and "connected" are to be construed broadly, such that a connection may be fixed or removable or integral; can be mechanically or electrically connected; the two structures can be directly connected or indirectly connected through an intermediate medium, and the two structures can be communicated with each other. To those skilled in the art, the specific meanings of the above terms in the present invention can be understood in light of the context of the present application, along with the general concepts of the invention.
Example one
A data storage method based on CRC check code is used for storing information data into a storage unit. The memory unit generally has functions of storing data and reading and writing data, and one memory unit may be 1 byte, 2 bytes, and the like. The storage unit usually includes several storage word lengths, the storage word length is the number of binary code (storage word) bits in the storage unit, the storage word length can be 8 bits, 16 bits, 32 bits, etc., several storage word lengths are sequentially arranged in sequence to form a data block for storing information data, the storage unit usually includes several data blocks, correspondingly, the data blocks also have an order relationship.
In this embodiment, the storage unit is configured as a flash EEPROM memory, the storage word length is configured as 32 bits, and each data block is 256 bytes. Each memory word length is divided into information bits for storing information data and inner check bits for storing an inner check code (CRC code), and the configuration information bits and the inner check bits are each 16 bits. In addition, an outer parity bit for storing an outer parity code (CRC code) is also provided at the end of each data block, and the outer parity bit is also 16 bits, as shown in fig. 2; of course, the outer parity bit may be set at the head of the data block.
As shown in fig. 1, the data storage method proposed in this embodiment includes the following steps:
s1, sequentially storing the information data in the information bits of each storage word length.
That is, for each data block, when information data is required to be stored in the data block, the information data to be stored is sequentially stored in the 16-bit information bits of each storage word length from beginning to end in the order of the storage word lengths in the data block. And when one data block is fully stored, the next data block is stored in sequence.
And S2, calculating the information data stored in the information bits in each storage word length respectively based on the first operation rule, and storing the inner check codes generated by calculation in the inner check bits of each storage word length respectively.
For a single memory word size, the first 16 information bits of the memory word have already stored information data, so that according to a given CRC check rule (the first operation rule, i.e. CRC16, such as CRC16_ XMODEM, CRC16_ USB, or CRC16_ MODBUS) and its determined divisor G (x), an inner check code (CRC code) to be filled in the inner check bits can be generated. Of course, the check rule of CRC16 may also be defined by itself according to the selected G (x), where G (x) needs to satisfy the following characteristics: g (x) is x n One factor of +1, i.e. x n +1= g (x) H (x); g (x) is a polynomial of degree r = n-k with a constant term of 1. It is understood that the CRC16 check rule applied to different memory word lengths may be the same or different, which does not affect the implementation of the method of the present embodiment.
As shown in table 1, which is a 16-bit check code generated when the standard CRC16_ XMODEM check rule is used for each memory word size in the data block.
TABLE 1
And S3, calculating the information data stored in the data block based on the second operation rule, and storing the outer check code generated by calculation in the outer check bit.
Based on the same principle as S2, all data with check in the data block can be calculated by selecting a good CRC check rule (the second operation rule, also referred to as CRC 16), so as to obtain an outer check code (CRC code). It is understood that, compared to S2, the CRC16 check rule applied in S3 may be the same or different, which does not affect the implementation of the method of the present embodiment.
It is understood that, for each storage word length, the number of bits of the information bits and the inner check bits may also be different, and the storage word length may also be 8 bits or 32 bits, etc., and the difference is only the change of the CRC check rule, i.e., the selection of G (x).
After the steps of the method, for each data block in the storage unit, while storing information data, the data block further comprises two CRC codes, namely an outer check code and an inner check code in each storage word length.
Example two
A data verification method based on CRC check codes is applied to computing equipment, such as an MCU (micro control unit) microprocessor (also called Single Chip Microcomputer) or a Single Chip Microcomputer, namely a simplified CPU (central processing unit), which is hereinafter referred to as MCU), and the method is specifically used for the MCU to verify information data read from a data block of a storage unit, wherein the information data is stored in the data block in advance according to a method disclosed by an embodiment, and as shown in FIG. 3, the method comprises the following steps:
and S10, reading the information data and the outer check code stored in the data block, and performing CRC check on the data block based on a second operation rule.
The MCU firstly reads the information data and the outer side check code stored in a certain data block, and then calculates the read information data based on the CRC rule which is the same as the CRC rule of S3 to obtain the check code.
And S20, judging whether the check is passed or not, if so, ending, and otherwise, executing error correction processing.
The MCU compares the check code obtained by calculation with the read outer side check code, if the two check codes are the same, the check is passed, the fact that the information data read by the MCU is the same as the information data stored in the data block is shown, and no error occurs when the information data are transmitted is shown; if the two are different, the verification is not passed, which indicates that the information data read by the MCU is inconsistent with the information data stored in the data block, and indicates that an error occurs during information data transmission, and error correction processing is required, and of course, the MCU may also perform re-reading operation on the data block. By the arrangement, unnecessary judgment of the MCU program can be avoided, and especially, time consumption can be effectively reduced under the condition that information data are error-free.
The CRC error detection principle is as follows:
according to m (x) x r ＝p(x)g(x)+q(x)，
Order: s (x) = m (x) x r +q(x)＝p(x)g(x)
r(x)＝s(x)+e(x)。
Wherein m (x) represents an information code without parity bits, m (x) x r Representing the information code left-shifted by r bits (check code length), q (x) representing m (x) x r The remainder of the cyclic code generator polynomial g (x) divided by s (x) represents the information code, e (x) represents the error code, and r (x) represents the information code containing the error bits.
When an error is detected, after the MCU executes the CRC check rule calculation, if e (x) =0, then r (x) = p (x) g (x) may be divided by g (x) to indicate that the information data has no error, otherwise, an error occurs.
EXAMPLE III
In this embodiment, after S20, the MCU performs an error correction processing operation, and it is known that there is an error occurring in the information data during the transmission process in the data block, and when it is not known in which storage word length or storage word lengths the error occurs, based on this, as shown in fig. 2, the error correction processing includes the following steps:
s30, sequentially reading information data and inner check codes stored in each storage word length in the data block, and performing CRC (cyclic redundancy check) on the storage word lengths based on a first operation rule after each storage word length is read;
s40, judging whether the check is passed, if so, reading the next storage word length, and if not, correcting the current storage word length;
and S50, carrying out error correction processing on the information data stored in the information bits in the current storage word length according to a preset error correction table.
In the same principle as the steps in S10 and S20, the MCU checks each storage word length based on the same CRC check rule as in S2, and if the check is passed, it indicates that no error occurs in the information data in the storage word length during transmission, and if the check is not passed, it indicates that an error occurs in the information data in the storage word length during transmission, and thus error correction is required.
And S60, carrying out error correction processing on the information data stored in the information bits in the current storage word length according to a preset error correction table.
The error correction table can be a 1-bit error correction table or a multi-bit error correction table, which is stored in a RAM area or a Flash area of the MCU in advance, and each storage word length corresponds to an error correction table, and the error correction tables corresponding to the storage word lengths may be the same or different, and the CRC check rules used only for the storage word lengths are different.
The CRC error correction principle is as follows:
r(x)modg(x)＝(s(x)+e(x)modg(x)
＝s(x)modg(x)+e(x)modg(x)
＝e(x)modg(x)。
where s (x) represents an information code, e (x) represents an error code, r (x) represents an information code containing erroneous bits, and mod is the modulo-2 operator. For a certain memory word size. When the check of S50 performed on a certain storage word length is failed, the data position where an error occurs in the information bit can be known by comparing r (x) modg (x) with the error correction table value, as shown in table 2, which indicates that the method of establishing the error correction table is described by using information symbol 0xFFFF (16-bit information bit), any other 16-bit information symbol can obtain the same error correction table, and after the error position is determined, correct information data can be obtained by directly correcting the data of the error position, thereby completing the error correction process, for example, if the 16-bit information bit in table 2 has an underline, the position data is erroneous.
TABLE 2
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in the embodiments without departing from the principles and spirit of the invention, and these embodiments are still within the scope of the invention.
Claims (9)
1. A data storage method based on a CRC check code, the method for storing information data in a data block in a memory unit, characterized by: the data block comprises an outer check bit and a plurality of storage word lengths which are sequentially arranged, and each storage word length comprises an information bit for storing information data and an inner check bit for storing an inner check code; the method comprises the following steps:
s1, sequentially storing information data in information bits of each storage word length;
s2, calculating information data stored in the information bits in each storage word length respectively based on a first operation rule, and storing inner check codes generated by calculation in the inner check bits of each storage word length respectively;
and S3, calculating the information data stored in the data block based on a second operation rule, and storing an outer check code generated by calculation in the outer check bit.
2. The data storage method of claim 1, wherein: the information bits and the inner check bits have the same number of bits.
3. The data storage method of claim 2, wherein: the memory word is 8 bits, 16 bits or 32 bits in length.
4. The data storage method of claim 1, wherein: the outer check bit is arranged at the tail part of the data block.
5. The data storage method of claim 1, wherein: the storage unit is a flash EEPROM memory.
6. The data storage method of claim 1, wherein: the first operation rule and the second operation rule are CRC16_ XMODEM, CRC16_ USB or CRC16_ MODBUS.
7. A data checking method based on CRC check code is used for checking information data read from a data block of a storage unit, and is characterized in that: the information data is stored in the data block according to the method of any of claims 1-6, the method comprising the steps of:
s10, reading information data and an outer check code stored in a data block, and performing CRC (cyclic redundancy check) on the data block based on a second operation rule;
and S20, judging whether the check is passed or not, if so, ending, and otherwise, executing error correction processing.
8. The data verification method of claim 7, wherein: the error correction process includes the steps of:
s30, sequentially reading the information data and the inner check code stored in each storage word length in the data block, and performing CRC (cyclic redundancy check) on the storage word lengths based on a first operation rule after each storage word length is read;
s40, judging whether the check is passed, if so, reading the next storage word length, and otherwise, correcting the current storage word length;
and S50, carrying out error correction processing on the information data stored in the information bits in the current storage word length according to a preset error correction table.
9. The data verification method of claim 8, wherein: the error correction table is a 1-bit error correction table or a multi-bit error correction table.
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