CN115208366A - Duobinary four-level pulse amplitude modulation signal processing method and system - Google Patents
Duobinary four-level pulse amplitude modulation signal processing method and system Download PDFInfo
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Abstract
The application provides a PAM4-DB signal processing method and a PAM4-DB signal processing system, wherein a PAM4-DB signal is obtained by coding the PAM4 signal, and the code element correlation of the PAM4 signal is eliminated in the coding process; the PAM4-DB signal is shunted to a plurality of comparison circuits, and the PAM4-DB signal is processed by each comparison circuit respectively to obtain a first logic level signal; respectively carrying out exclusive-OR processing on part of the first logic level signals in all the first logic level signals by using an exclusive-OR circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-OR processing and the first logic level signals not subjected to exclusive-OR processing by using an inversion circuit to obtain second logic level signals; and adding all the second logic level signals by using an adding circuit to obtain a PAM4 signal, decoding the PAM4-DB signal by using a simple circuit, and simplifying the decoding process.
Description
Technical Field
The application belongs to the technical field of high-speed serial communication, and particularly relates to a duobinary four-level pulse amplitude modulation signal processing method and system.
Background
Along with the continuous development of human civilization and scientific technology, the living standard of people is increasingly improved, the demand of high-speed communication is more and more intense, and a point-to-point serial communication technology is developed, wherein the point-to-point serial communication technology is characterized in that a plurality of paths of low-speed parallel signals at a sending end are converted into high-speed serial signals, the high-speed serial signals are transmitted through transmission media such as optical cables or copper wires and then are converted into low-speed parallel signals at a receiving end again, the channel capacity of the transmission media is fully utilized, the number of channels and the number of chip pins are reduced while the signal transmission speed is improved, and further the communication cost and the complexity are remarkably reduced.
Higher and higher transmission speeds also represent more and more challenges, and the PAM4 (fourth order pulse amplitude modulation) signal modulation scheme is gradually replaced by a PAM4-duobinary (duobinary-four order pulse amplitude modulation, abbreviated as PAM 4-DB) signal modulation scheme. After a PAM4-DB signal is obtained through a PAM4-DB signal adjustment mode, how to simplify a decoding process is a problem which needs to be solved urgently at present.
Disclosure of Invention
The application provides a duo-binary four-level pulse amplitude modulation signal processing method and a duo-binary four-level pulse amplitude modulation signal processing system.
In one aspect, the present application provides a duobinary four-level pulse amplitude modulation signal processing method, where the method includes:
obtaining a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal;
the duobinary four-level pulse amplitude modulation signals are divided into a plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signals are processed by each comparison circuit respectively to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits;
respectively carrying out exclusive-or processing on part of the first logic level signals in all the first logic level signals by using an exclusive-or circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-or processing and the first logic level signals not subjected to exclusive-or processing by using an inversion circuit to obtain second logic level signals;
and adding all the second logic level signals by using an adding circuit to obtain the four-level pulse amplitude modulation signal.
Optionally, the encoding the four-level pulse amplitude modulation signal to obtain a duobinary four-level pulse amplitude modulation signal includes:
pre-coding the four-level pulse amplitude modulation signal to eliminate symbol correlation of the four-level pulse amplitude modulation signal;
and carrying out duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.
Optionally, the pre-coding the four-level pulse amplitude modulation signal includes:
with b k ＝(a k +b k-1 ) mod4 precodes the four-level pulse amplitude modulated signal, a k For said four-level pulse amplitude modulated signal, a k The values of (A) include 0, 1, 2 and 3 k For the output of the four-level pulse amplitude modulation signal, b k-1 An output for precoding the four-level pulse amplitude modulation signal for the previous time;
the performing duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal includes:
using c k ＝b k +b k-1 Duobinary modulation of the pre-coded four-level pulse amplitude modulation signal, c k For said duobinary four-level pulse amplitude modulated signal, c k The values of (a) include 0, 1, 2, 3, 4, 5 and 6.
Optionally, the shunting the duobinary four-level pwm signal to a plurality of comparison circuits, wherein the processing the duobinary four-level pwm signal through each comparison circuit respectively to obtain the first logic level signal includes:
dividing the duobinary four-level pulse amplitude modulation signal into eight paths of signals by using a broadband divider, wherein the first path of signals to the eighth path of signals are sequentially input into a first comparison circuit to an eighth comparison circuit;
comparing the level of the input signal with a threshold level by using the first comparison circuit to the eighth comparison circuit to obtain a first logic level signal of each comparison circuit.
Optionally, the first comparing circuit corresponds to a first threshold level, the second comparing circuit, the fourth comparing circuit and the sixth comparing circuit correspond to a fourth threshold level, the third comparing circuit corresponds to a second threshold level, the fifth comparing circuit corresponds to a third threshold level, the seventh comparing circuit corresponds to a fifth threshold level, and the eighth comparing circuit corresponds to a sixth threshold level;
the levels of the duobinary four-level pulse amplitude modulation signal comprise a first level to a seventh level;
the relationship of the first to seventh levels and the first to sixth threshold levels is: the first level is less than a first threshold level, the first threshold level is less than a second level, the second level is less than a second threshold level, the second threshold level is less than a third level, the third level is less than a third threshold level, the third threshold level is less than a fourth level, the fourth level is less than a fourth threshold level, the fourth threshold level is less than a fifth level, the fifth level is less than a fifth threshold level, the fifth threshold level is less than a sixth level, the sixth level is less than a sixth threshold level, and the sixth threshold level is less than a seventh level.
Optionally, the performing, by using an exclusive-or circuit, exclusive-or processing on part of the first logic level signals in all the first logic level signals, and performing, by using an inverter circuit, level inversion processing on the first logic level signals subjected to exclusive-or processing and the first logic level signals that are not subjected to exclusive-or processing to obtain the second logic level signals includes:
performing exclusive-or processing on first logic level signals output by the first comparison circuit and the second comparison circuit by using an exclusive-or gate;
performing exclusive-or processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit by using an exclusive-or gate;
performing exclusive-or processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit by using an exclusive-or gate;
and carrying out level inversion processing on the first logic level signal subjected to the exclusive-OR processing and the first logic level signal which is not subjected to the exclusive-OR processing by using an inverter to obtain a second logic level signal.
In another aspect, the present application provides a duobinary four-level pulse amplitude modulation signal processing system, the system comprising: the circuit comprises a signal obtaining circuit, a shunt circuit, a plurality of comparison circuits, an exclusive OR circuit, an inverter circuit and an addition circuit;
the signal obtaining circuit is used for obtaining a duobinary four-level pulse amplitude modulation signal, the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal;
the shunt circuit is used for shunting the duobinary four-level pulse amplitude modulation signal to the plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signal is processed by each comparison circuit respectively to obtain a first logic level signal, and the number of the first logic level signals is the same as that of the comparison circuits;
the exclusive-or circuit is used for respectively carrying out exclusive-or processing on part of the first logic level signals in all the first logic level signals;
the inverting circuit is used for carrying out level inversion processing on the first logic level signal subjected to the exclusive OR processing and the first logic level signal which is not subjected to the exclusive OR processing to obtain a second logic level signal;
and the addition circuit is used for adding all the second logic level signals to obtain the four-level pulse amplitude modulation signal.
Optionally, the system further includes: the encoding circuit is used for encoding the four-level pulse amplitude modulation signal to obtain a duo-binary four-level pulse amplitude modulation signal;
the encoding circuit encodes the binary four-level pulse amplitude modulation signal to obtain a duobinary four-level pulse amplitude modulation signal, and the encoding circuit comprises: pre-coding the four-level pulse amplitude modulation signal to eliminate symbol correlation of the four-level pulse amplitude modulation signal; and carrying out duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.
Optionally, the shunt circuit is a broadband shunt, the broadband shunt shunts the duobinary four-level pulse amplitude modulation signal into eight paths of signals, and the first path of signal to the eighth path of signal are sequentially input into the first comparison circuit to the eighth comparison circuit; the first comparison circuit to the eighth comparison circuit compare the level of the input signal with a threshold level to obtain a first logic level signal of each comparison circuit;
the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level;
the levels of the duobinary four-level pulse amplitude modulation signal comprise a first level to a seventh level;
the relationship of the first to seventh levels and the first to sixth threshold levels is: the first level is smaller than the first threshold level, the first threshold level is smaller than the second level, the second level is smaller than the second threshold level, the second threshold level is smaller than the third level, the third level is smaller than the third threshold level, the third threshold level is smaller than the fourth level, the fourth level is smaller than the fourth threshold level, the fourth threshold level is smaller than the fifth level, the fifth level is smaller than the fifth threshold level, the fifth threshold level is smaller than the sixth level, the sixth level is smaller than the sixth threshold level, and the sixth threshold level is smaller than the seventh level.
Optionally, the xor circuit is an xor gate, and the inverting circuit is an inverter;
the exclusive-or gate is used for carrying out exclusive-or processing on first logic level signals output by the first comparison circuit and the second comparison circuit; performing exclusive-or processing on first logic level signals output by the third comparison circuit and the fourth comparison circuit; performing exclusive-or processing on first logic level signals output by the fifth comparison circuit and the sixth comparison circuit;
and the inverter is used for carrying out level inversion processing on the first logic level signal subjected to the XOR processing and the first logic level signal which is not subjected to the XOR processing to obtain a second logic level signal.
In another aspect, the present application provides a storage medium, in which computer program codes are stored, and when the computer program codes are executed, the duo-binary four-level pulse amplitude modulation signal processing method is implemented.
The method and the system for processing the duobinary four-level pulse amplitude modulation signal obtain the duobinary four-level pulse amplitude modulation signal, the duobinary four-level pulse amplitude modulation signal is obtained by encoding the four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal; the method comprises the steps that duobinary four-level pulse amplitude modulation signals are divided to a plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signals are processed through each comparison circuit respectively to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits; respectively carrying out exclusive-or processing on part of the first logic level signals in all the first logic level signals by using an exclusive-or circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-or processing and the first logic level signals not subjected to exclusive-or processing by using an inversion circuit to obtain second logic level signals; and the addition circuit is used for adding all the second logic level signals to obtain a four-level pulse amplitude modulation signal, the simple circuits such as the comparison circuit, the exclusive OR circuit, the inverter circuit and the addition circuit are used for decoding the duobinary four-level pulse amplitude modulation signal, and the decoding process is simplified. And the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the coding process of the four-level pulse amplitude modulation signal, and the error code of the previous moment is prevented from being transmitted to the next moment, so that the error code rate is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a duo-binary four-level pulse amplitude modulation signal processing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an encoding provided by an embodiment of the present application;
FIG. 3 is a decoding diagram provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of a duo-binary four-stage pulse amplitude modulation signal processing system according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of another duo-binary four-level pulse amplitude modulation signal processing system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an optional flow of a duobinary four-level pulse amplitude modulation signal processing method provided in an embodiment of the present application is shown, which may include the following steps:
101: and obtaining a PAM4-DB signal, wherein the PAM4-DB signal is obtained by coding the PAM4 signal, the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal, and the error code of the previous moment is prevented from being transmitted to the next moment by eliminating the code element correlation, so that the error rate is reduced.
In this embodiment, a PAM4-DB signal is obtained by a transmitting end by encoding a PAM4 signal, the transmitting end transmits the PAM4-DB signal to a receiving end after encoding the PAM4-DB signal, and the receiving end decodes the received PAM4-DB signal to restore the PAM4 signal, where fig. 1 of this embodiment illustrates a decoding process of the receiving end after receiving the PAM4-DB signal.
One feasible way for the sending end to encode the PAM4 signal to obtain the PAM4-DB signal is as follows: precoding the PAM4 signal to eliminate the code element correlation of the PAM4 signal; and performing duo-binary (DB) modulation on the precoded PAM4 signal to obtain a PAM4-DB signal. The reason why the precoding process is performed before the DB modulation is performed on the signal is that:
if the PAM4 signal without precoding is subjected to DB coding to obtain a PAM4-DB signal, the logic of DB coding is b n ＝a n +a n-1 Signal a for reception decision at the receiving end n ＝b n -a n-1 Is the inverse operation of DB coding, so that the sampling decision value a at the current time n Is the sampled decision value a from the previous moment n-1 Is closely related if the sampled decision value a of the previous time instant n-1 And if misjudgment occurs, error codes also occur at the current moment, and the error codes are transmitted all the time, so that error transmission is caused. The method for solving error transmission is to carry out pre-coding before carrying out DB coding so as to eliminate code element correlation and avoid error transmission.
One way in which the PAM4 signal is precoded includes: with b k ＝(a k +b k-1 ) mod4 precoding PAM4 signals, a k Is a PAM4 signal, a k The values of (A) include 0, 1, 2 and 3 k For the output of the current precoding of PAM4 signals, b k-1 An output for precoding the PAM4 signal for the last time.
One way of obtaining a PAM4-DB signal by performing duo-binary modulation on the precoded PAM4 signal includes: using c k ＝b k +b k-1 Duobinary modulation of the precoded PAM4 signal, c k Is a PAM4-DB signal, c k The values of (a) include 0, 1, 2, 3, 4, 5 and 6.
As shown in the encoding diagram of FIG. 2, a PAM4 signal is a k The values of the levels include 0, 1, 2 and 3. The PAM4 signal after precoding is b k ，bk＝(a k +b k-1 ) mod4, the precoded signal is still a PAM4 signal, and includes four level values, which are 0, 1, 2, and 3, respectively. mod is a remainder function, the application of which is not illustrated.
DB coding the PAM4 signal after precoding to form a PAM4-DB signal, and setting the PAM4-DB signal as c k ，c k ＝b k +b k-1 And converting the original four-level signal into a seven-level signal, namely a PAM4-DB signal.
The truth table for the PAM4-DB signal is as follows:
the four-level signal represents 4 levels of the signal, such as 0, 1, 2 and 3, and the seven-level signal represents 7 levels of the signal, such as 0, 1, 2, 3, 4, 5 and 6. For Delay T in FIG. 2 b Represents the output b of the last preceding PAM4 signal k-1 。
102: and shunting the PAM4-DB signal to a plurality of comparison circuits, wherein the PAM4-DB signal is processed by each comparison circuit respectively to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits.
In which the PAM4-DB signal is input to each comparison circuit simultaneously or sequentially, in the present embodiment, one way of shunting and processing with the comparison circuits is as follows:
dividing the PAM4-DB signal into eight paths of signals by using a broadband divider, wherein the first path of signals to the eighth path of signals are sequentially input into a first comparison circuit to an eighth comparison circuit; then, the levels of the input signals are compared with the threshold level by using the first comparison circuit to the eighth comparison circuit to obtain a first logic level signal of each comparison circuit.
The threshold levels corresponding to the first to eighth comparing circuits may be the same or different, for example, one way is: the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level.
The levels of the PAM4-DB signal include first to seventh levels, such as 0 to 6 described above. The first to seventh levels have a relationship with the first to sixth threshold levels that: the first level is less than a first threshold level, the first threshold level is less than a second level, the second level is less than a second threshold level, the second threshold level is less than a third level, the third level is less than a third threshold level, the third threshold level is less than a fourth level, the fourth level is less than a fourth threshold level, the fourth threshold level is less than a fifth level, the fifth level is less than a fifth threshold level, the fifth threshold level is less than a sixth level, the sixth level is less than a sixth threshold level, and the sixth threshold level is less than a seventh level.
In the present embodiment, the division of the eight signals and the comparison using the above six threshold levels are merely exemplary, and the present embodiment is not limited.
103: and respectively carrying out exclusive-OR processing on part of the first logic level signals in all the first logic level signals by utilizing an exclusive-OR circuit.
104: and carrying out level inversion processing on the first logic level signal subjected to the exclusive-OR processing and the first logic level signal not subjected to the exclusive-OR processing by using an inversion circuit to obtain a second logic level signal.
The exclusive-or circuit is used for judging whether at least two logic level signals input into the exclusive-or circuit are the same or not, if the logic level signals are the same, a low level 0 is output, and if the logic level signals are different, the logic level signals are output, and decoding is carried out through exclusive-or processing. In this embodiment, the two first logic level signals may be subjected to xor processing, for example, the two first logic level signals may be subjected to xor processing by using an xor gate, and the two first logic level signals input by different xor gates are different, so that the plurality of xor gates may simultaneously perform xor processing on the plurality of first logic level signals. The inverter circuit is used for switching the level high and low, 1 to 0 and 0 to 1, and may be implemented by an inverter, for example.
In combination with the eight divided signals and the eight comparison circuits, one way of performing the exclusive-or process and the level inversion process is as follows:
performing exclusive-OR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit by using an exclusive-OR gate; the exclusive OR gate is used for carrying out exclusive OR processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit; performing exclusive-or processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit by using an exclusive-or gate; and carrying out level inversion processing on the first logic level signal subjected to the XOR processing and the first logic level signal which is not subjected to the XOR processing by using an inverter to obtain a second logic level signal.
105: and adding all the second logic level signals by using an adding circuit to obtain a PAM4 signal.
In the following, the decoding process of this embodiment is described with reference to the circuit structure shown in fig. 3, where the PAM4-DB signal is divided into eight signals by the wideband divider, enters the next stage, and is compared with the threshold voltage by eight comparison circuits of the next stage, and is converted into the first logic level signal. Assuming that seven level values included in the AM4-DB signal are denoted as V1, V2, V3, V4, V5, V6, and V7, which are sequentially a first level to a seventh level, and the value may be 0 to 6; the eight comparison circuits correspond to six threshold levels, which are recorded as VA, VB, VC, VD, VE and VF, and sequentially range from a first threshold level to a sixth threshold level, and the relationship between the six threshold levels and the seven levels is as follows:
V1<VA<V2<VB<V3<VC<V4<VD<V5<VE<V6<VF<V7；
the first threshold level to the sixth threshold level can be set through this relationship, and the present embodiment does not limit the values of the six threshold levels, wherein the eight comparison circuits shown in fig. 3 may be eight high-speed comparators to increase the processing speed. The eight high-speed comparators are respectively marked as A, D1, B, D2, C, D3, E and F and are sequentially a first comparison circuit to an eighth comparison circuit; the threshold levels corresponding to the eight comparison circuits are VA, VD, VB, VD, VC, VD, VE, and VF respectively, that is, the description above indicates that "the first comparison circuit corresponds to the first threshold level, the second comparison circuit, the fourth comparison circuit, and the sixth comparison circuit correspond to the fourth threshold level, the third comparison circuit corresponds to the second threshold level, the fifth comparison circuit corresponds to the third threshold level, the seventh comparison circuit corresponds to the fifth threshold level, and the eighth comparison circuit corresponds to the sixth threshold level" and are identical. If the level of the signal input to the eight comparison circuits is st, the truth table after it passes through the eight comparison circuits is as follows:
the outputs of the comparison circuit A and the comparison circuit D1 are integrated into a signal through an exclusive-OR gate again, the outputs of the comparison circuit B and the comparison circuit D2 are integrated into a signal through an exclusive-OR gate again, the outputs of the comparison circuits C and D3 are integrated into a signal through an exclusive-OR gate again, and the signals subjected to exclusive-OR processing and the outputs of the comparison circuits VE and VF are counted into five signals to enter the next stage.
The truth table after the exclusive-or processing is as follows, the XOR in the truth table represents an exclusive-or circuit:
the five signals are respectively converted into high and low levels through an inverter, 1 is converted into 0, and 0 is converted into 1.
The truth table is as follows, where inverter in the truth table represents an inverter circuit:
the signals after level conversion are added through an adding circuit, the obtained signals are PAM4 signals obtained by decoding PAM4-DB signals, and therefore the PAM4 signals subjected to precoding, inter-symbol correlation elimination and DB coding are decoded through simple circuits such as the comparing circuit, the exclusive OR circuit, the inverting circuit and the adding circuit. The truth table after addition by the adder circuit is as follows, SUN in the truth table represents the adder circuit:
the method for processing the duo-binary four-level pulse amplitude modulation signal obtains a PAM4-DB signal, wherein the PAM4-DB signal is obtained by coding the PAM4 signal, and the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal; the PAM4-DB signal is shunted to a plurality of comparison circuits, the PAM4-DB signal is processed by each comparison circuit respectively to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits; respectively carrying out exclusive-or processing on part of the first logic level signals in all the first logic level signals by using an exclusive-or circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-or processing and the first logic level signals not subjected to exclusive-or processing by using an inversion circuit to obtain second logic level signals; and the PAM4 signal is obtained by adding all the second logic level signals by using an adding circuit, the decoding of the PAM4-DB signal is completed by using simple circuits such as a comparison circuit, an exclusive OR circuit, an inverter circuit and an adding circuit, and the decoding process is simplified. And the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal, and the error code of the previous moment is prevented from being transmitted to the next moment, so that the error code rate is reduced.
Corresponding to the above method embodiment, the present application further provides a duo-binary four-level pulse amplitude modulation signal processing system, whose structure is shown in fig. 4, and may include: the signal obtaining circuit 10, the shunt circuit 20, the plurality of comparison circuits 30 (the comparison circuits 30 may be plural in fig. 4 indicated by an ellipsis), the exclusive or circuit 40, the inverter circuit 50, and the adder circuit 60.
And the signal obtaining circuit 10 is used for obtaining a PAM4-DB signal, wherein the PAM4-DB signal is obtained by coding the PAM4 signal, the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal, and the error code of the previous moment is prevented from being transmitted to the next moment by eliminating the code element correlation, so that the error rate is reduced.
In this embodiment, the PAM4-DB signal is obtained by encoding the PAM4 signal by the transmitting end, the PAM4-DB signal is transmitted to the receiving end after the transmitting end encodes the PAM4-DB signal, and the receiving end decodes the received PAM4-DB signal to restore the PAM4 signal, where the duo-binary four-level pulse amplitude modulation signal processing system shown in fig. 4 may be integrated at the receiving end, and the receiving end decodes the PAM4-DB signal by using the system shown in fig. 4. One feasible way for the sending end to encode the PAM4 signal to obtain the PAM4-DB signal is as follows: precoding the PAM4 signal to eliminate the code element correlation of the PAM4 signal; and performing duo-binary (DB) modulation on the precoded PAM4 signal to obtain a PAM4-DB signal. The reason why the precoding process is performed before the DB modulation is performed on the signal is that:
if the non-precoded PAM4 signal is DB-coded to obtain a PAM4-DB signal, the logic of the DB-coding is b n ＝a n +a n-1 Signal a for reception decision at the receiving end n ＝b n -a n-1 Is the inverse operation of DB coding, therefore, the sampling decision value a at the current time n Is the sampled decision value a from the previous moment n-1 Is closely correlated if the sampled decision value a of the previous time instant n-1 And if misjudgment occurs, error codes also occur at the current moment, and the error codes are transmitted all the time, so that error transmission is caused. The method for solving error transmission is to carry out pre-coding before carrying out DB coding so as to eliminate code element correlation and avoid error transmission.
One way in which to precode PAM4 signals includes: with b k ＝(a k +b k-1 ) mod4 precodes PAM4 signals, a k Is a PAM4 signal, a k The values of (A) include 0, 1, 2 and 3 k For the output of the current precoding of PAM4 signals, b k-1 An output for precoding the PAM4 signal for the last time. One way of obtaining a PAM4-DB signal by performing duo-binary modulation on the precoded PAM4 signal includes: by using c k ＝b k +b k-1 Duobinary modulation of the precoded PAM4 signal, c k Is a PAM4-DB signal, c k The values of (a) include 0, 1, 2, 3, 4, 5 and 6.
And a shunt circuit 20 for shunting the PAM4-DB signal to the plurality of comparison circuits 30, wherein the pam4-DB signal is processed by each comparison circuit 30 to obtain a first logic level signal, and the number of the first logic level signals is the same as that of the comparison circuits. The shunt circuit 20 may be a broadband shunt, which shunts the PAM4-DB signal into eight signals, and the first to eighth signals are sequentially input to the first to eighth comparison circuits; the first to eighth comparison circuits compare the level of the input signal with a threshold level to obtain a first logic level signal of each comparison circuit.
The first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level.
The levels of the PAM4-DB signal include first to seventh levels; the relationship of the first to seventh levels and the first to sixth threshold levels is: the first level is less than a first threshold level, the first threshold level is less than a second level, the second level is less than a second threshold level, the second threshold level is less than a third level, the third level is less than a third threshold level, the third threshold level is less than a fourth level, the fourth level is less than a fourth threshold level, the fourth threshold level is less than a fifth level, the fifth level is less than a fifth threshold level, the fifth threshold level is less than a sixth level, the sixth level is less than a sixth threshold level, and the sixth threshold level is less than a seventh level.
And an exclusive-or circuit 40 for exclusive-oring some of all the first logic level signals.
And an inverter circuit 50, configured to perform level inversion on the first logic level signal subjected to the exclusive or processing and the first logic level signal not subjected to the exclusive or processing, so as to obtain a second logic level signal.
The exclusive or circuit 40 may be an exclusive or gate, and the inverter circuit 50 may be an inverter; the exclusive-OR gate is used for carrying out exclusive-OR processing on the first logic level signals output by the first comparison circuit and the second comparison circuit; performing exclusive-or processing on first logic level signals output by the third comparison circuit and the fourth comparison circuit; and performing exclusive-OR processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit. In this embodiment, the duobinary four-stage pulse amplitude modulation signal processing system may include a plurality of xor gates, and each xor gate performs xor processing on two paths of the first logic level signals. And the inverter is used for carrying out level inversion processing on the first logic level signal subjected to the XOR processing and the first logic level signal which is not subjected to the XOR processing to obtain a second logic level signal.
And an adding circuit 60 for adding all the second logic level signals to obtain a PAM4 signal.
In the present embodiment, please refer to the above embodiments for the descriptions of the shunting circuit 20, the plurality of comparing circuits 30, the xor circuit 40, the inverter circuit 50 and the adder circuit 60, which will not be described herein again.
Referring to fig. 5, an alternative structure of a duobinary four-level pulse amplitude modulation signal processing system is shown, which may further include: the coding circuit 70 is used for coding the PAM4 signal to obtain a PAM4-DB signal; the PAM4-DB signal coded by the coding circuit comprises the following steps: precoding the PAM4 signal to eliminate the code element correlation of the PAM4 signal; the precoded PAM4 signal is subjected to duo-binary modulation to obtain a PAM4-DB signal, and the detailed process thereof can be referred to the above description.
The PAM4 signal can be coded by the coding circuit to obtain a PAM4-DB signal, the PAM4-DB signal is sent to a receiving end to be decoded, the PAM4 signal can be coded by the duo-binary four-level pulse amplitude modulation signal processing system, the PAM4 signal can be decoded and restored by the PAM4-DB signal, any device is integrated with the duo-binary four-level pulse amplitude modulation signal processing system, and the device can be used as a sending end of the PAM4-DB signal and a receiving end of the PAM4-DB signal.
The duo-binary four-level pulse amplitude modulation signal processing system obtains a PAM4-DB signal, wherein the PAM4-DB signal is obtained by coding the PAM4 signal, and the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal; the PAM4-DB signals are shunted to a plurality of comparison circuits, the PAM4-DB signals are respectively processed by each comparison circuit to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits; respectively carrying out exclusive-OR processing on part of the first logic level signals in all the first logic level signals by using an exclusive-OR circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-OR processing and the first logic level signals not subjected to exclusive-OR processing by using an inversion circuit to obtain second logic level signals; and the PAM4 signal is obtained by adding all the second logic level signals by using an adding circuit, the decoding of the PAM4-DB signal is completed by using simple circuits such as a comparison circuit, an exclusive OR circuit, an inverter circuit and an adding circuit, and the decoding process is simplified. And the code element correlation of the PAM4 signal is eliminated in the coding process of the PAM4 signal, and the error code of the previous moment is prevented from being transmitted to the next moment, so that the error rate is reduced.
The embodiment of the application also provides a storage medium, wherein a computer program code is stored in the storage medium, and when the computer program code is executed, the duobinary four-level pulse amplitude modulation signal processing method is realized.
It should be noted that, each embodiment in the present specification may be described in a progressive manner, and features described in each embodiment in the present specification may be replaced or combined with each other, each embodiment focuses on differences from other embodiments, and similar parts between each embodiment may be referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. A duobinary four-level pulse amplitude modulation signal processing method, the method comprising:
obtaining a duobinary four-level pulse amplitude modulation signal, wherein the duobinary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal;
the duobinary four-level pulse amplitude modulation signals are divided into a plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signals are processed by each comparison circuit respectively to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits;
respectively carrying out exclusive-OR processing on part of the first logic level signals in all the first logic level signals by using an exclusive-OR circuit, and carrying out level inversion processing on the first logic level signals subjected to exclusive-OR processing and the first logic level signals not subjected to exclusive-OR processing by using an inversion circuit to obtain second logic level signals;
and adding all the second logic level signals by using an adding circuit to obtain the four-level pulse amplitude modulation signal.
2. The method of claim 1, wherein encoding the four-level pulse amplitude modulated signal to obtain a duobinary four-level pulse amplitude modulated signal comprises:
pre-coding the four-level pulse amplitude modulation signal to eliminate symbol correlation of the four-level pulse amplitude modulation signal;
and carrying out duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.
3. The method of claim 2, wherein the pre-coding the four-level pulse amplitude modulated signal comprises:
with b k ＝(a k +b k-1 ) mod4 precodes the four-level pulse amplitude modulated signal, a k For said four-level pulse amplitude modulated signal, a k The values of (A) include 0, 1, 2 and 3 k For the output of the four-level pulse amplitude modulation signal, b k-1 An output for precoding the four-level pulse amplitude modulation signal for the previous time;
the performing duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal includes:
by using c k ＝b k +b k-1 Duobinary modulation of the precoded four-level pulse amplitude modulation signal, c k For said duobinary four-level pulse amplitude modulated signal, c k The values of (c) include 0, 1, 2, 3, 4, 5 and 6.
4. The method according to any one of claims 1 to 3, wherein the shunting the duobinary four-level pulse amplitude modulated signal to a plurality of comparison circuits, the duobinary four-level pulse amplitude modulated signal being processed by each comparison circuit to obtain a first logic level signal comprises:
the duobinary four-level pulse amplitude modulation signal is divided into eight paths of signals by a broadband shunt, wherein the first path of signal to the eighth path of signal are sequentially input into a first comparison circuit to an eighth comparison circuit;
comparing the level of the input signal with a threshold level by using the first comparison circuit to the eighth comparison circuit to obtain a first logic level signal of each comparison circuit.
5. The method of claim 4, wherein the first comparison circuit corresponds to a first threshold level, the second, fourth, and sixth comparison circuits correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level;
the levels of the duo-binary four-level pulse amplitude modulation signal comprise a first level to a seventh level;
the relationship of the first to seventh levels and the first to sixth threshold levels is: the first level is less than a first threshold level, the first threshold level is less than a second level, the second level is less than a second threshold level, the second threshold level is less than a third level, the third level is less than a third threshold level, the third threshold level is less than a fourth level, the fourth level is less than a fourth threshold level, the fourth threshold level is less than a fifth level, the fifth level is less than a fifth threshold level, the fifth threshold level is less than a sixth level, the sixth level is less than a sixth threshold level, and the sixth threshold level is less than a seventh level.
6. The method of claim 4, wherein the exclusive-or circuit exclusive-ors some of all the first logic level signals, and the inverter circuit level-inverts the exclusive-or processed first logic level signal and the exclusive-or unprocessed first logic level signal to obtain the second logic level signal comprises:
performing exclusive-or processing on the first logic level signals output by the first comparison circuit and the second comparison circuit by using an exclusive-or gate;
performing exclusive-or processing on the first logic level signals output by the third comparison circuit and the fourth comparison circuit by using an exclusive-or gate;
performing exclusive-or processing on the first logic level signals output by the fifth comparison circuit and the sixth comparison circuit by using an exclusive-or gate;
and carrying out level inversion processing on the first logic level signal subjected to the XOR processing and the first logic level signal which is not subjected to the XOR processing by using an inverter to obtain a second logic level signal.
7. A duobinary four-level pulse amplitude modulated signal processing system, the system comprising: the circuit comprises a signal obtaining circuit, a shunt circuit, a plurality of comparison circuits, an exclusive OR circuit, an inverter circuit and an addition circuit;
the signal obtaining circuit is used for obtaining a duo-binary four-level pulse amplitude modulation signal, wherein the duo-binary four-level pulse amplitude modulation signal is obtained by encoding a four-level pulse amplitude modulation signal, and the code element correlation of the four-level pulse amplitude modulation signal is eliminated in the encoding process of the four-level pulse amplitude modulation signal;
the shunt circuit is used for shunting the duobinary four-level pulse amplitude modulation signals to the plurality of comparison circuits, the duobinary four-level pulse amplitude modulation signals are respectively processed by each comparison circuit to obtain first logic level signals, and the number of the first logic level signals is the same as that of the comparison circuits;
the exclusive-OR circuit is used for respectively carrying out exclusive-OR processing on part of the first logic level signals in all the first logic level signals;
the inverting circuit is used for carrying out level inversion processing on the first logic level signal subjected to the exclusive OR processing and the first logic level signal which is not subjected to the exclusive OR processing to obtain a second logic level signal;
and the addition circuit is used for adding all the second logic level signals to obtain the four-level pulse amplitude modulation signal.
8. The system of claim 7, further comprising: the encoding circuit is used for encoding the four-level pulse amplitude modulation signal to obtain a duo-binary four-level pulse amplitude modulation signal;
the encoding circuit encodes the obtained duobinary four-level pulse amplitude modulation signal and comprises the following steps: pre-coding the four-level pulse amplitude modulation signal to eliminate the code element correlation of the four-level pulse amplitude modulation signal; and carrying out duobinary modulation on the pre-coded four-level pulse amplitude modulation signal to obtain the duobinary four-level pulse amplitude modulation signal.
9. The system according to claim 7 or 8, wherein the shunt circuit is a broadband shunt, the broadband shunt shunts the duo-binary four-level pulse amplitude modulation signal into eight paths of signals, and the first path of signal to the eighth path of signal are sequentially input into the first comparison circuit to the eighth comparison circuit; the first comparison circuit to the eighth comparison circuit compare the level of the input signal with a threshold level to obtain a first logic level signal of each comparison circuit;
the first comparison circuit corresponds to a first threshold level, the second comparison circuit, the fourth comparison circuit and the sixth comparison circuit correspond to a fourth threshold level, the third comparison circuit corresponds to a second threshold level, the fifth comparison circuit corresponds to a third threshold level, the seventh comparison circuit corresponds to a fifth threshold level, and the eighth comparison circuit corresponds to a sixth threshold level;
the levels of the duobinary four-level pulse amplitude modulation signal comprise a first level to a seventh level;
the relationship of the first to seventh levels and the first to sixth threshold levels is: the first level is less than a first threshold level, the first threshold level is less than a second level, the second level is less than a second threshold level, the second threshold level is less than a third level, the third level is less than a third threshold level, the third threshold level is less than a fourth level, the fourth level is less than a fourth threshold level, the fourth threshold level is less than a fifth level, the fifth level is less than a fifth threshold level, the fifth threshold level is less than a sixth level, the sixth level is less than a sixth threshold level, and the sixth threshold level is less than a seventh level.
10. The system of claim 9, wherein the xor circuit is an xor gate and the inverting circuit is an inverter;
the exclusive-or gate is used for carrying out exclusive-or processing on first logic level signals output by the first comparison circuit and the second comparison circuit; performing exclusive-or processing on first logic level signals output by the third comparison circuit and the fourth comparison circuit; performing exclusive-or processing on first logic level signals output by the fifth comparison circuit and the sixth comparison circuit;
and the inverter is used for carrying out level inversion processing on the first logic level signal subjected to the XOR processing and the first logic level signal which is not subjected to the XOR processing to obtain a second logic level signal.
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