CN115206903A - Packaging structure and preparation method thereof - Google Patents

Packaging structure and preparation method thereof Download PDF

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Publication number
CN115206903A
CN115206903A CN202110393914.9A CN202110393914A CN115206903A CN 115206903 A CN115206903 A CN 115206903A CN 202110393914 A CN202110393914 A CN 202110393914A CN 115206903 A CN115206903 A CN 115206903A
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China
Prior art keywords
heat dissipation
chip
substrate
exposed
exposed chip
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CN202110393914.9A
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Chinese (zh)
Inventor
杨丹凤
林耀剑
徐晨
何晨烨
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Changdian Technology Management Co ltd
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Changdian Technology Management Co ltd
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Priority to CN202110393914.9A priority Critical patent/CN115206903A/en
Publication of CN115206903A publication Critical patent/CN115206903A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a packaging structure and a preparation method thereof, wherein the packaging structure comprises a substrate, a first substrate and a second substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged; the chips are positioned on the first surface and comprise at least one back-exposed chip and at least one non-back-exposed chip; the heat dissipation structure is attached to the back surface of the non-back-exposed chip; and the back surface of the heat dissipation structure and the back surface of the back exposed chip are exposed outwards through the sealing structure. The packaging structure of the invention selectively exposes the back of part of the chip, and embeds the part of the chip in the middle or at the edge without exposing the back, but sticks the radiating fin on the back of the chip, thereby enhancing the radiating effect and simultaneously reducing or avoiding the problem of cracking of the packaging material between the chips.

Description

Packaging structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a packaging structure capable of efficiently dissipating heat and keeping high reliability and a preparation method thereof.
Background
Consumer electronic products are gradually pursuing light, thin, short and small appearance, and artificial intelligence and high-speed operation architecture evolution are simultaneously pursued, so that semiconductor packaging gradually evolves from 2D packaging to 2.5D and 3D stacking technologies.
The multi-chip 2.5D packaging field adopts a mode that the back surface of a chip is exposed, so that the heat management performance of the chip packaging can be improved on the whole. However, the way of exposing the chips from the back can face the problem of cracking of the encapsulating material between the chips; if the chip is not exposed, the heat dissipation performance of the package structure is affected.
In view of the above, there is a need for an improved package structure and a method for manufacturing the same to solve the above problems.
Disclosure of Invention
The invention aims to provide a packaging structure and a preparation method thereof.
In order to realize one of the purposes of the invention, the invention adopts the following technical scheme:
a package structure, comprising:
the device comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
the chips are positioned on the first surface and comprise at least one back exposed chip and at least one non-back exposed chip;
the heat dissipation structure is attached to the back surface of the non-back-exposed chip;
and the back surface of the heat dissipation structure and the back surface of the back exposed chip are exposed outwards through the sealing structure.
Further, the heat loss of the non-back-exposed chip is less than or equal to the heat loss of the back-exposed chip.
Further, the non-back-exposed chip is located at an edge or in the middle of the substrate.
Furthermore, the heat dissipation structure is attached to the back surface of the non-back-exposed chip through a heat dissipation interface bonding material.
Further, when any side of the non-back-exposed chip has other chips, the edge of the heat dissipation structure facing the side does not exceed the edge of the non-back-exposed chip facing the side.
Furthermore, stress grooves and/or stress holes are/is arranged on the heat dissipation structure.
Further, the heat dissipation structure comprises a top heat dissipation fin and a side supporting portion, and the stress groove and/or the stress hole are/is formed in the connection position of the top heat dissipation fin or the top heat dissipation fin and the side supporting portion.
Further, the heat dissipation structure comprises a top heat sink thermally connected with the back surface of the non-back-exposed chip, and the top heat sink can be in a flat sheet shape or a partial cap shape.
Further, the heat dissipation structure comprises a top heat dissipation sheet in heat conduction connection with the back surface of the non-back-exposed chip, and at least one end of the top heat dissipation sheet is provided with a heat dissipation fin.
Further, the heat dissipation structure further includes a side support portion that is in contact with the redistribution layer stack layer through a heat dissipation interface bonding material.
Further, the heat dissipation interface bonding material comprises at least one of heat dissipation glue, silver or alloy sintering glue and soldering tin.
Further, the substrate is one of a redistribution stack layer, a fan-out redistribution interposer with embedded chips, and a silicon interposer with passive and active devices.
Furthermore, the packaging structure further comprises a heat dissipation cover plate or a plurality of metal deposition layers, wherein the heat dissipation cover plate is connected with one side of the heat dissipation structure, which is far away from the non-back-exposed chip, and the back of the back-exposed chip in a soaking and conducting mode.
Further, the heat-dissipating cover plate or the plurality of metal deposition layers may be a flat sheet or a partial cap type.
Furthermore, the heat dissipation structure and the heat dissipation cover plate are both electrically connected with the grounding wire of the substrate; or the heat dissipation structure and the multiple metal deposition layers are electrically connected with the grounding wire of the substrate.
A preparation method of a packaging structure comprises the following steps:
flip-chip or surface mount at least two chips on a first surface of a substrate;
the heat dissipation structure is attached to the back surface of at least one chip through heat dissipation interface bonding materials such as heat dissipation glue, silver or alloy sintering glue thereof, soldering tin and the like;
carrying out wafer or plate-level plastic package to form an injection molding piece;
exposing the back surface of the heat dissipation structure and the back surface of the chip of which the back surface is not pasted with the heat dissipation structure out of the injection molding piece;
and forming a solder ball or a plurality of layers of metal bumps on the second surface of the substrate.
Further, when any side of the chip mounted with the heat dissipation structure is provided with other chips, the edge of the heat dissipation structure facing the side does not exceed the edge of the chip facing the side;
and/or stress grooves and/or stress holes are/is arranged on the heat dissipation structure;
and/or the heat dissipation structure comprises a top heat dissipation sheet in heat conduction connection with the back surface of the non-back-exposed chip, and the top heat dissipation sheet can be in a flat sheet shape or a partial cap shape;
and/or the heat dissipation structure comprises a top heat dissipation fin in heat conduction connection with the back surface of the non-back-exposed chip, and at least one end of the top heat dissipation fin is provided with a heat dissipation fin;
and/or the heat dissipation structure further comprises a side support part, wherein the side support part is contacted with the substrate through a heat dissipation interface bonding material;
and/or the heat dissipation interface bonding material comprises at least one of heat dissipation glue, silver or silver alloy sintering glue and soldering tin;
and/or the substrate is a rewiring stack layer, or the substrate is a fan-out rewiring interposer with embedded chips, or the substrate is a silicon interposer with passive and active devices.
Furthermore, the heat dissipation structure and the heat dissipation cover plate are both electrically connected with the grounding wire of the substrate; or the heat dissipation structure and the multiple metal deposition layers are electrically connected with the grounding wire of the substrate; preferably, the substrate is a redistribution stack layer, or the substrate is a fan-out redistribution interposer with embedded chips, or the substrate is a silicon interposer with passive and active devices.
Furthermore, a heat dissipation cover plate or a plurality of metal deposition layers are attached to the back surface of the back exposed chip and the back surface of the heat dissipation structure.
Furthermore, the heat dissipation structure and the heat dissipation cover plate are both electrically connected with the grounding wire of the substrate; or the heat dissipation structure and the multiple metal deposition layers are electrically connected with the grounding wire of the substrate; preferably, the substrate is one of a redistribution stack layer, a fan-out redistribution interposer with embedded chips, and a silicon interposer with passive and active devices.
Compared with the prior art, the invention has the beneficial effects that: the packaging structure of the invention selectively exposes the back of part of the chip, and the part of the chip positioned in the middle or at the edge is embedded but not exposed, but the back of the chip is pasted with the radiating fin, thereby enhancing the radiating effect and simultaneously reducing or avoiding the problem of cracking of the packaging material between the chips.
Drawings
FIG. 1 is a diagram of a package structure according to a preferred embodiment of the present invention;
FIG. 2 isbase:Sub>A cross-sectional view taken along A-A of FIG. 1;
FIG. 3 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 6 is a cross-sectional view taken along line B-B of FIG. 5;
FIG. 7 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 8 is a cross-sectional view taken along the line C-C of FIG. 7;
FIG. 9 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 10 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 11 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 12 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 13 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
FIG. 14 is a schematic diagram of a package structure according to another preferred embodiment of the present invention;
fig. 15a to 15f are schematic flow charts of a method for manufacturing a package structure according to a preferred embodiment of the invention.
The packaging structure comprises a packaging structure 100, a substrate 1, a first surface 11, a second surface 12, a first solder bump 13, a solder ball array 14, a chip 2, a back exposed chip 2a, a back non-exposed chip 21, a second solder bump or a bump 22, a back gold layer 3, a heat dissipation structure 31, a top heat dissipation sheet 32, a heat dissipation fin 33, a stress groove 34, a stress hole 35, a side support part 35, a heat dissipation block 36, a sealing structure 4, a underfill 41, a second underfill 41, an injection molding material part 42, a heat dissipation cover plate or a metal deposition layer 5, a grounding column 51, a local cap 52, a passive element 6, a transfer plate 7 or a temporary bonding support plate 8, a substrate 9 and a reinforcing rib 9.
Detailed Description
The present application will now be described in detail with reference to specific embodiments thereof as illustrated in the accompanying drawings. These embodiments are not intended to limit the present application, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present application.
In the various illustrations of the present application, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for ease of illustration and, thus, are provided to illustrate only the basic structure of the subject matter of the present application.
In addition, "and/or" as used herein means "or" and ", such as" M and/or N ", means M, or N, or three cases of M and N.
Referring to fig. 1 to 14, a package structure 100 according to a preferred embodiment of the invention includes a substrate 1, at least two chips 2 located on the substrate 1, a heat dissipation structure 3, and a sealing structure 4.
The substrate 1 is preferably a redistribution layer stack, or the substrate 1 is a fan-out redistribution interposer with embedded chips, or a silicon interposer with passive and active devices on the substrate 1. And the substrate 1 has a first surface 11 and a second surface 12 which are oppositely arranged. The first surface 11 has a plurality of first bumps 13 for electrically connecting with the chip 2, and the second surface 12 has an array of solder balls 14, such as copper bumps or solder balls.
The front surface of the chip 2 is provided with a second welding bump 21 used for being connected with the first welding bump 13, the second welding bump is packaged on the substrate 1 in a flip chip or surface mounting mode, and the back surface of the chip 2 is back to the substrate 1.
The at least two chips 2 include at least one back-exposed chip 2a and at least one non-back-exposed chip 2b depending on whether or not the back surfaces of the chips 2 are exposed outward through the sealing structure 4. The back surface of the back-exposed chip 2a is not encapsulated by the sealing structure 4, and is exposed outwards and directly radiates outwards. The non-back-exposed chip 2b is embedded in the sealing structure 4 but not exposed to the outside, and radiates heat to the outside through the heat radiation structure 3 attached to the back surface of the non-back-exposed chip 2b.
In the present invention, it is preferable that the chip 2 having the same or smaller heat loss than the other chips 2 is used as the non-back-exposed chip 2b, and the chip 2 having a larger heat loss is used as the back-exposed chip 2a; that is, the heat loss of the non-backside-exposed chip 2b is lower than or equal to the heat loss of the backside-exposed chip 2a. Specifically, the non-back exposed chip 2b may be located at the edge of the bottom, also called edge chip 2; it may also be located at an intermediate position of the chip 2, also called intermediate chip 2. In a special design case, 2b may have a higher heat loss than 2a.
In addition, a back gold layer 22 may be provided on the back surface of a part of the chip 2, and such a chip 2 may also be used as the non-exposed back chip 2b. At this time, the top heat sink 31 is located on the side of the back gold layer 22 away from the non-exposed back chip 2b.
The back gold layer 22 is a metal stack of Ti/Ni/Ag or Ti/Ni/Au or Ti/Cu. The adhesion of the back gold layer 22 to the back surface of the non-exposed back chip 2b is enhanced by a thin layer of Ti, the thermal diffusion aging resistance is improved by a Ni layer with a moderate thickness, and finally the Ni layer is protected by Ag or Au to improve the bonding wettability. Further, the back gold layer 22 is arranged in a cutting pattern shape, so that subsequent laser segmentation is facilitated, or stress is dispersed, and the back gold layer 22 is not easy to damage.
According to the invention, the back surface of the back exposed chip 2a is exposed outwards, the back of the non-back exposed chip 2b is embedded but not exposed, but the heat dissipation effect is enhanced by sticking the heat dissipation structure 3 on the back surface of the non-back exposed chip 2b, so that the problem of cracking of the sealing material between the chips 2 can be reduced or avoided while the heat dissipation effect is ensured.
The heat dissipation structure 3 comprises a top heat sink 31, and the top heat sink 31 is in heat conduction connection with the back surface of the non-back-exposed chip 2b through a heat dissipation interface bonding material, so as to enhance top heat dissipation. In the invention, the heat dissipation interface bonding material comprises at least one of heat dissipation glue, silver or silver alloy sintering glue and soldering tin.
The top heat sink 31 may be a flat sheet or a partial cap, which can effectively improve heat dissipation efficiency.
Preferably, at least one end of the top heat sink 31 is provided with a heat dissipating fin 32, further improving heat dissipating efficiency. The heat dissipation fins 32 are located around the non-back-exposed chip 2b, so that the heat dissipation area of the top heat dissipation fin 31 is enlarged, and the heat dissipation of the adjacent other chips 2 is not affected.
When any side of the non-back-exposed chip 2b has other chips 2, the edge of the heat dissipation structure 3 facing the side does not exceed the edge of the non-back-exposed chip 2b facing the side, so that the heat dissipation structure 3 is prevented from influencing the heat dissipation effect of the adjacent chip 2. For example, as shown in fig. 1, when a chip 2 is further disposed on the right side of the non-back-exposed chip 2b, the right edge of the heat dissipation structure 3 does not exceed the right edge of the non-back-exposed chip 2b. For example, as shown in fig. 5 and 7, when a chip 2 is further disposed on both left and right sides of the non-back-exposed chip 2b, the left edge of the heat dissipation structure 3 does not exceed the left edge of the non-back-exposed chip 2b, and the right edge of the heat dissipation structure 3 does not exceed the right edge of the non-back-exposed chip 2b. However, in the embodiment having the heat dissipation fins 32, as shown in fig. 7, the edges of the heat dissipation fins 32 may extend beyond the non-exposed chip 2b to be close to the edges of the other chips 2 adjacent thereto.
Further, stress grooves 33 and/or stress holes 34 are/is arranged on the heat dissipation structure 3 to reduce warpage; meanwhile, the stress groove 33 or the stress hole 34 also plays a role in exhausting air, and can help the plastic package material to be filled.
Optionally, the heat dissipation structure 3 further includes a side supporting portion 35, and the side supporting portion 35 is in contact with the substrate 1 through a heat dissipation interface bonding material such as polymer adhesive, silver or alloy sintering glue thereof, solder, and the like, so as to achieve a side heat dissipation effect. The side support portions 35 are generally located around all the chips 2, and are in contact with the edge of the substrate 1, and also function as electromagnetic shields.
The heat dissipation structure 3 is in contact with the substrate 1 by several sides depending on the number of the side supports 35. The heat dissipation structure 3 may be in contact with the substrate 1 through one, two, or three sides. Contact may be made by electrical connection without electrical bonding or bonding with a grounded metal in the substrate 1. As shown in fig. 1 to 3, when the non-back-exposed chip 2b is located at the edge of the substrate 1, the heat dissipation structure 3 may contact the substrate 1 through three sides; as shown in fig. 4, when the non-back-exposed chip 2b is located at the edge of the substrate 1, the heat dissipation structure 3 may also contact the substrate 1 through one edge. Referring to fig. 5 to 8, when the non-back-exposed chip 2b is located in the middle of the substrate 1, the heat dissipation structure 3 is usually in contact with the substrate 1 through one side, but may be in contact with the substrate 1 through two sides.
In the embodiment with the side support portions 35, the stress grooves 33 or stress holes 34 are opened at the top fin 31 or the connection of the top fin and the side support portions 35.
Based on any of the above embodiments, as shown in fig. 9 to 14, the package structure 100 further includes a heat-dissipating cover plate or a metal deposition layer 5 in heat-soaking conduction connection with a side of the heat-dissipating structure 3 away from the non-back-exposed chip 2b and a back surface of the back-exposed chip 2a, where the heat-dissipating cover plate 5 is a multi-layer metal, such as Ti/Cu/Ti or SuS/Cu/SuS, for enhancing back-surface heat dissipation. Preferably, the heat dissipation cover plate 5 is an integrated cover plate capable of covering the back surface of the whole package structure 100, and has a large heat dissipation area and a good heat dissipation effect.
Preferably, the heat dissipation cover plate 5 is electrically connected with a ground wire of the substrate 1, so as to achieve an electromagnetic shielding effect. Specifically, the heat dissipation cover plate 5 is electrically connected to the heat dissipation structure 3, and the heat dissipation structure 3 is in contact with the substrate 1, so that the heat dissipation cover plate 5 is electrically connected to the substrate 1 indirectly through the heat dissipation structure 3 to achieve grounding. Or the heat-radiating cover plate 5 is in contact with the substrate 1 through a grounding post 51 positioned outside the chip 2 to realize grounding.
The sealing structure 4 comprises an underfill 41 after the flip chip or surface mounting is completed and an injection molding part or plastic molding material 42 after the heat dissipation structure 3 is mounted. After the chip 2 is flipped or surface mounted, underfill 41 is performed, specifically, the underfill 41 is filled in a gap between the substrate 1 and the chip 2, at least a part of the side wall of the chip 2 is covered by the underfill 41, and the back surface of all the chips 2 is exposed outwards. And attaching the heat dissipation structure 3 to the back surface of the non-back-exposed chip 2b, then carrying out wafer or plate-level plastic package to form an injection molding piece 42, and then processing the injection molding piece 42 to expose the heat dissipation structure 3 and the back surface of the back-exposed chip 2a. Specifically, at least one of thinning the injection molding 42, plasma or laser processing may be employed to expose the backside of chip 2 and heat dissipation structure 3.
The package structure 100 further includes a passive element 6, the passive element 6 is located on the first surface 11 of the substrate 1, the passive element 6 is located around the chip 2, and the passive element 6 is sealed in the injection molding 42 of the sealing structure 4. Or the passive component 6 is located at the second surface 12 of the substrate 1.
The package structure 100 is a fan-out package structure 100. And packaging the fan-out type packaging structure on a single-grain substrate 8 or an integral substrate 8, filling a gap between the fan-out type packaging structure 100 and the substrate 8 by using a second underfill 41', and performing optional second partial or complete plastic packaging before or after mounting the reinforcing ribs. For example, the second local plastic package is carried out before the reinforcing ribs are installed; or a second plastic molding (not shown) may be performed after the reinforcing ribs are mounted.
The package structure 100 of the present invention will be described in the following with reference to specific illustrative embodiments.
Referring to fig. 1 and fig. 2, a package structure 100 according to a preferred embodiment of the invention includes a substrate 1, a non-back-exposed chip 2b and a back-exposed chip 2a on a first surface 11 of the substrate 1, an optional back gold layer 22 on a back surface of the non-back-exposed chip 2b, a heat dissipation structure 3 attached to a side of the back gold layer 22 away from the non-back-exposed chip 2b, a passive component 6 on the first surface 11 of the substrate 1 and around the chip 2, an underfill 41 between the chip 2 and the substrate 1, an injection molding or molding compound 42 around the chip 2 and around the passive component, and a solder ball 11 on a second surface 12 of the substrate 1. One side of the heat dissipation structure 3 departing from the non-back-exposed chip 2b and the back of the back-exposed chip 2a are exposed outwards, and other structures are sealed in the injection molding part 42.
The non-back-exposed chip 2b is the edge chip 2 located at the thorough edge, the passive element 6 is located at one side of the back-exposed chip 2a departing from the non-back-exposed chip 2b, and a space for installing the heat dissipation structure 3 is reserved at the side of the non-back-exposed chip 2b.
The heat dissipation structure 3 includes a top heat sink 31 in a flat sheet shape and three side support portions 35, and the heat dissipation structure 3 is in contact with the substrate 1 through 3 sides. The top heat sink 31 and the side support portions 35 do not extend beyond the edge of the non-back-exposed chip 2b adjacent to the back-exposed chip 2a.
The heat dissipation structure 3 is provided with a stress slot 33, and the stress slot 33 is located at the connection position of the top heat dissipation plate 31 and the side supporting part 35.
Referring to fig. 3 in detail, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 1 only in that: the heat dissipation structure 3 is provided with stress holes 34, and the stress holes 34 are distributed at the top heat dissipation plate 31 and the connection between the top heat dissipation plate 31 and the side support part 35.
Referring to fig. 4, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 1 only in that: the heat dissipation structure 3 only includes one side support portion 35 and contacts the substrate 1 through a single side, and the side support portion 35 is located on a side of the non-back-exposed chip 2b departing from the back-exposed chip 2a. The heat dissipation structure 3 is provided with stress grooves 33, and the stress grooves 33 are distributed at the connection position of the top heat dissipation sheet 31 and the side supporting portion 35.
Referring to fig. 5 and fig. 6 in particular, a package structure 100 according to another preferred embodiment of the invention is shown, which is different from the embodiment shown in fig. 1 only in that: the substrate 1 is provided with 3 chips 2 arranged side by side, one chip 2 in the middle is a non-back-exposed chip 2b, and two chips at the edge are back-exposed chips 2a. The heat dissipation structure 3 includes a top heat sink 31 and a side supporting portion 35, wherein the side supporting portion 35 is located at a side of the non-backside exposed chip 2b not adjacent to the backside exposed chip 2a. The heat dissipation structure is provided with stress holes 34 located on the top heat dissipation fins 31 and stress grooves 33 located at the connection positions of the top heat dissipation fins 31 and the side supporting portions 35. The passive element 6 is disposed on one side of one back exposed chip 2a away from the non-back exposed chip 2b and one side of the non-back exposed chip 2b away from the side supporting portion 35.
Referring to fig. 7 and fig. 8 in particular, a package structure 100 according to another preferred embodiment of the invention is shown, which is different from the embodiment shown in fig. 5 only in that: the two ends of the radiating fin are provided with radiating fins 32, and the radiating fins 32 exceed the edges of the non-back-exposed chip 2b adjacent to the other chips 2, so that the radiating area is enlarged.
Referring to fig. 9 in detail, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 1 only in that: the solar cell module further comprises a flat-plate-shaped heat dissipation cover plate or a plurality of metal deposition layers 5, wherein the heat dissipation cover plate 5 is in heat conduction connection with the heat dissipation structure 3 and the back surface of the back exposed chip 2a.
Referring to fig. 10, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 9 only in that: the heat dissipation cover 5 has a partial cap 52 protruding to a side away from the substrate 1, and the partial cap 52 is in contact with the back surface and a part of the side wall of the back exposed chip 2a, so that the heat dissipation performance of the back exposed chip 2a is improved. In addition, the heat dissipation structure 3 is provided with a bump protruding toward the heat dissipation cover plate 5 for heat conduction connection with the heat dissipation cover plate 5.
Referring to fig. 11, a package structure 100 according to another preferred embodiment of the invention is shown, which is different from the embodiment shown in fig. 9 only in that: the heat dissipation cover plate 5 has a protruding portion protruding toward the side of the substrate 1, and the protruding portion contacts with the heat dissipation structure 3, so that the thermal contact area between the heat dissipation cover plate and the heat dissipation structure is enlarged, and the heat dissipation performance of the non-exposed chip 2b is improved.
Referring to fig. 12, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 9 only in that: the heat dissipation cap realizes heat conduction with the back surface of the back exposed chip 2a through a plurality of heat dissipation blocks through a heat dissipation block 36.
Referring to fig. 13, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 7 only in that: the heat dissipation structure further comprises a flat-plate-shaped heat dissipation cover plate 5, and the heat dissipation cover plate 5 is in heat conduction connection with the heat dissipation structure 3 and the back surface of the back exposed chip 2a.
Referring to fig. 14 in particular, a package structure 100 according to another preferred embodiment of the invention is different from the embodiment shown in fig. 13 only in that: the heat dissipation cover 5 has a partial cap 52 protruding to a side away from the substrate 1, and the partial cap 52 is in contact with the back surface and a part of the side wall of the back exposed chip 2a, so that the heat dissipation performance of the back exposed chip 2a is improved. And, the heat-radiating cover plate 5 is grounded by contacting with the substrate 1 through a grounding post 51.
The invention also provides a preparation method of the packaging structure 100, which comprises the following steps: flip-chip or surface mount at least two chips 2 on the first surface 11 of the substrate 1; the heat dissipation structure 3 is attached to the back surface of at least one chip 2 through heat dissipation glue, silver or alloy sintering glue thereof, soldering tin and the like; performing wafer or plate level plastic package to form an injection molding piece 42; exposing the injection molding parts 42 from the back surface of the heat dissipation structure 3 and the back surface of the chip 2 of which the back surface is not attached with the heat dissipation structure 3; and planting balls on the second surface 12 of the substrate 1.
In the preparation method, besides the steps related to the front and the back in the process, the sequence of other steps can be inter-modulated, for example, the injection molding 42 can be exposed on the back surface of the heat dissipation structure 3 and the back surface of the chip 2 without the heat dissipation structure 3 attached to the back surface before and after ball mounting.
In addition, the substrate 1, the chip 2, the heat dissipation structure 3, the plastic package process, and the like refer to the foregoing description, and are not described herein again.
In a reference embodiment, please refer to fig. 15a to 15f, the method for manufacturing the package structure 100 includes the following steps:
referring to fig. 15a to 15b, at least one non-backside exposed chip 2b and at least one backside exposed chip 2a are flip-chip mounted or surface-mounted on the first surface 11 of the substrate 1, and a first underfill 41 is performed between the chip 2 and the substrate 1 to enhance stability; of course, underfilling may not be performed.
This step further includes mounting at least one passive component 6 on the first surface 11 of the substrate 1. And a transfer board or a temporary bonding carrier board 7 is attached to the second surface 12 of the substrate 1 for supporting and protecting the same.
Referring to fig. 15c, the heat dissipation structure 3 is attached to the back surface of the non-back-exposed chip 2b by using heat dissipation glue, silver or its alloy sintering glue, solder, etc.; specifically, the top heat sink 31 of the heat dissipation structure 3 is attached to the back surface of the non-back-exposed chip 2b, and the side support portion 35 of the heat dissipation structure 3 is attached to the first surface 11 by polymer adhesive, silver or its alloy sintering adhesive, solder, or the like.
Referring to fig. 15d, a wafer or board level plastic package is performed to form the injection molding member 42. The process adopts injection molding or hot-press plastic package, and specifically can adopt a back full-covering type packaging method, namely, the back surfaces of the heat dissipation structure 3 and the back exposed chip 2a are completely covered, so that backflow warping can be avoided; the back of the back-exposed chip 2a and the back of the heat dissipation structure 3 are then exposed using at least one of thinning the injection molded part 42, plasma or laser processing. Certainly, when there is no problem of reflow warpage, a local plastic package method of backside film protection may also be adopted, that is, the back exposed chip 2a and the heat dissipation structure 3 which are exposed to the outside through the injection molding package structure 100 are protected by the film in the subsequent process, and then injection molding package is performed, and the back exposed chip 2a and the heat dissipation structure 3 can be exposed by simply removing the film in the subsequent process.
Wherein, the step of exposing the back exposed chip 2a and the heat dissipation structure 3 after the injection molding in this step may also be arranged after the step of fig. 15 c.
Referring to fig. 15e, the transfer board or the temporary bonding carrier is removed, and the second surface 12 of the substrate 1 is formed by ball-planting or selective electroplating of bumps, specifically, copper bumps or solder balls are produced on the second surface 12.
Referring to fig. 15f, the fan-out package structure 100 obtained in the above step is mounted on a single substrate 8, and a second underfill 41' is performed to fill a gap between the fan-out package structure 100 and the substrate 8. In this step, the reinforcing ribs 9 may be further attached to the peripheral region of the substrate 8, and/or the heat dissipation cover may be attached to the side of the fan-out package structure 100 away from the substrate 8, and then the second injection molding is performed to form the second injection molded part.
Of course, the fan-out package 100 may be attached to the large substrate 8 and then cut into individual products after the second injection molding.
In summary, in the package structure 100 of the present invention, by selectively exposing a portion of the chips 2, the portion of the chips 2 located in the middle or at the edge is embedded without being exposed, but the heat sink is attached to the back of the chip 2, so as to enhance the heat dissipation effect and reduce or avoid the cracking of the encapsulating material between the chips 2.
It should be understood that although the specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it will be appreciated by those skilled in the art that the specification as a whole may be appropriately combined to form other embodiments as will be apparent to those skilled in the art.
The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.

Claims (19)

1. A package structure, comprising:
the device comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
the chips are positioned on the first surface and comprise at least one back exposed chip and at least one non-back exposed chip;
the heat dissipation structure is attached to the back surface of the non-back-exposed chip;
and the back surface of the heat dissipation structure and the back surface of the back exposed chip are exposed outwards through the sealing structure.
2. The package structure of claim 1, wherein: the heat consumption of the non-back-exposed chip is less than or equal to that of the back-exposed chip.
3. The package structure of claim 1, wherein: the non-back-exposed chip is located at the edge or in the middle of the substrate.
4. The package structure of claim 1, wherein: the heat dissipation structure is attached to the back surface of the non-back-exposed chip through a heat dissipation interface bonding material.
5. The package structure of claim 1, wherein: when any side of the non-back-exposed chip is provided with other chips, the edge of the heat dissipation structure facing the side does not exceed the edge of the non-back-exposed chip facing the side.
6. The package structure of claim 1, wherein: and stress grooves and/or stress holes are/is arranged on the heat dissipation structure.
7. The package structure of claim 6, wherein: the heat dissipation structure comprises a top heat dissipation sheet and a side supporting portion, and the stress groove and/or the stress hole are/is formed in the top heat dissipation sheet or the joint of the top heat dissipation sheet and the side supporting portion.
8. The package structure of claim 1, wherein: the heat dissipation structure comprises a top heat dissipation sheet in heat conduction connection with the back surface of the non-back-exposed chip, and the top heat dissipation sheet can be in a flat sheet shape or a partial cap shape.
9. The package structure of claim 1, wherein: the heat dissipation structure comprises a top heat dissipation sheet in heat conduction connection with the back surface of the non-back-exposed chip, and at least one end of the top heat dissipation sheet is provided with a heat dissipation fin.
10. The package structure of claim 1, wherein: the heat dissipation structure further includes a side support portion that is in contact with the substrate through a heat dissipation interface bonding material.
11. The package structure according to claim 4 or 10, wherein: the heat dissipation interface bonding material comprises at least one of heat dissipation glue, silver or silver alloy sintering glue and soldering tin.
12. The package structure of claim 1, wherein: the packaging structure further comprises a heat dissipation cover plate or a plurality of metal deposition layers, wherein the heat dissipation cover plate or the plurality of metal deposition layers are in soaking conduction connection with one side of the heat dissipation structure, which deviates from the non-back-exposed chip, and the back of the back-exposed chip.
13. The package structure of claim 12, wherein: the heat-radiating cover plate or the multiple metal deposition layers can be in a flat sheet shape or a partial cap shape.
14. The package structure according to claim 12 or 13, wherein: the heat dissipation structure and the heat dissipation cover plate are electrically connected with the grounding wire of the substrate; or the heat dissipation structure and the multiple metal deposition layers are electrically connected with the grounding wire of the substrate.
15. The package structure of claim 1, wherein: the substrate is a rewiring stack layer, or the substrate is a fan-out rewiring interposer with embedded chips, or the substrate is a silicon interposer with passive and active devices.
16. A preparation method of a packaging structure is characterized by comprising the following steps: the method comprises the following steps:
flip-chip or surface mount at least two chips on a first surface of a substrate;
attaching a heat dissipation structure to the back surface of at least one chip through a heat dissipation interface bonding material;
carrying out wafer or plate-level plastic package to form an injection molding piece;
exposing the injection molding parts on the back surface of the heat dissipation structure and the back surface of the chip of which the back surface is not pasted with the heat dissipation structure;
and forming a solder ball or a plurality of layers of metal bumps on the second surface of the substrate.
17. The method for manufacturing a package structure according to claim 16, wherein: when any side of the chip of the mounting heat dissipation structure is provided with other chips, the edge of the heat dissipation structure facing the side does not exceed the edge of the chip facing the side;
and/or stress grooves and/or stress holes are/is arranged on the heat dissipation structure;
and/or the heat dissipation structure comprises a top heat dissipation sheet in heat conduction connection with the back surface of the non-back-exposed chip;
and/or the heat dissipation structure comprises a top heat dissipation fin in heat conduction connection with the back surface of the non-back-exposed chip, and at least one end of the top heat dissipation fin is provided with a heat dissipation fin;
and/or the heat dissipation structure further comprises a side support part, wherein the side support part is contacted with the substrate through a heat dissipation interface bonding material;
and/or the heat dissipation interface bonding material comprises at least one of heat dissipation glue, silver or silver alloy sintering glue and soldering tin;
and/or the substrate is one of a redistribution stack layer, a fan-out redistribution interposer with embedded chips, and a silicon interposer with passive and active devices.
18. The method for manufacturing a package structure according to claim 16, wherein: and a heat dissipation cover plate or a plurality of metal deposition layers are attached to the back surface of the back exposed chip and the back surface of the heat dissipation structure.
19. The method for manufacturing a package structure according to claim 18, wherein: the heat dissipation structure and the heat dissipation cover plate are electrically connected with the grounding wire of the substrate; or the heat dissipation structure and the multiple metal deposition layers are electrically connected with the grounding wire of the substrate; preferably, the substrate is one of a redistribution stack, a fan-out redistribution interposer with embedded chips, and a silicon interposer with passive and active devices.
CN202110393914.9A 2021-04-13 2021-04-13 Packaging structure and preparation method thereof Pending CN115206903A (en)

Priority Applications (1)

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CN202110393914.9A CN115206903A (en) 2021-04-13 2021-04-13 Packaging structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110393914.9A CN115206903A (en) 2021-04-13 2021-04-13 Packaging structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN115206903A true CN115206903A (en) 2022-10-18

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Country Link
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