CN115201525A - Anti-condensation device for semi-closed silicon optical chip low-temperature test - Google Patents
Anti-condensation device for semi-closed silicon optical chip low-temperature test Download PDFInfo
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- CN115201525A CN115201525A CN202210854262.9A CN202210854262A CN115201525A CN 115201525 A CN115201525 A CN 115201525A CN 202210854262 A CN202210854262 A CN 202210854262A CN 115201525 A CN115201525 A CN 115201525A
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- 238000012360 testing method Methods 0.000 title claims abstract description 89
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 32
- 239000010703 silicon Substances 0.000 title claims abstract description 32
- 230000003287 optical effect Effects 0.000 title claims abstract description 31
- 238000009833 condensation Methods 0.000 title claims abstract description 19
- 239000000523 sample Substances 0.000 claims abstract description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 230000005494 condensation Effects 0.000 claims abstract description 9
- 230000008878 coupling Effects 0.000 claims abstract description 8
- 238000010168 coupling process Methods 0.000 claims abstract description 8
- 238000005859 coupling reaction Methods 0.000 claims abstract description 8
- 239000011521 glass Substances 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 3
- 239000013307 optical fiber Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2877—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to cooling
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses an anti-condensation device for a semi-closed silicon optical chip low-temperature test, which comprises: the chip testing device comprises a chip bearing platform base, an outer plate assembly and a chip bearing platform, wherein the outer plate assembly is provided with a coupling adjusting port, a testing probe extending port and a gas inlet for filling nitrogen into a chip testing space. The wafer bearing table base and the outer plate assembly are jointly enclosed to form a semi-closed chip testing space, an operation position is reserved, nitrogen is continuously introduced into the chip testing space, a positive pressure environment is formed in a limited space, the water vapor outside the device can be effectively guaranteed to be incapable of entering the device, the testing operation is convenient, the moisture condensation can be effectively prevented, and the testing accuracy is guaranteed.
Description
Technical Field
The invention relates to the technical field of photoelectric chip packaging and testing, in particular to a condensation preventing device for a semi-closed silicon optical chip low-temperature test.
Background
At present, the main mode for realizing the low-temperature test of the silicon optical chip is to fill nitrogen or other inert gases in a totally enclosed low-temperature test device so as to ensure that the chip is not contacted with water vapor. Although the mode can ensure that water vapor is not contacted with the chip, the positions of the probe and the optical fiber in the totally enclosed low-temperature testing device are relatively fixed, and the probe and the optical fiber which can be flexibly moved are required for evaluating various different types of silicon optical chips, but the totally enclosed low-temperature testing device is not easy to change the positions of the probe or the optical fiber for testing. The fully open type test apparatus can freely move the probe and the optical fiber, but cannot solve the problem of dew condensation of the silicon optical chip at low temperature.
Disclosure of Invention
In order to solve the technical problem, the invention provides a semi-closed anti-condensation device for a silicon optical chip for low-temperature test. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The invention adopts the following technical scheme:
the invention provides a semi-closed anti-condensation device for a silicon optical chip for low-temperature test, which comprises:
the wafer bearing table base is connected with an external temperature control device;
the outer plate assembly is arranged on the wafer bearing table base and surrounds the wafer bearing table base to form a chip testing space;
the chip bearing platform is used for bearing a silicon optical chip and is positioned in the chip testing space;
and the outer plate assembly is provided with a coupling adjusting port, a test probe extending port and a gas inlet for filling nitrogen into the chip test space.
Further, the chip carrying table comprises: the chip testing device comprises a lower supporting table and an upper testing table, wherein a chip bearing table surface is formed on the upper surface of the upper testing table; an air exhaust channel is formed in the lower supporting table, a plurality of fixing channels communicated with the air exhaust channel are formed in the upper testing table, and an upper opening of each fixing channel is located on the chip bearing table.
Furthermore, a temperature measuring probe fixing hole is formed in the upper test board.
Further, the outer panel assembly includes: a front panel and two side panels; the test probe extending port is formed in the top end of the front panel, the air inlet is formed in the front panel, and an air extraction equipment connecting port is formed in the position, corresponding to the air extraction channel, of the front panel; the coupling adjusting opening is formed in the side plate, and a temperature measuring probe extending hole is formed in the position, corresponding to the temperature measuring probe fixing hole, of the side plate.
Further, the outer panel assembly further includes: a back plate and a cover plate; the back plate is hinged with the wafer bearing table base, and the cover plate is hinged with the back plate; and the cover plate is provided with an expansion port communicated with the test probe extending inlet.
Furthermore, the material of planking subassembly is organic glass.
Furthermore, the wafer bearing platform base and the chip bearing platform are made of alloy.
The invention has the following beneficial effects: the wafer bearing table base and the outer plate assembly are jointly enclosed to form a semi-closed chip testing space, an operation position is reserved, nitrogen is continuously introduced into the chip testing space, a positive pressure environment is formed in a limited space, the water vapor outside the device can be effectively guaranteed to be incapable of entering the device, the testing operation is convenient, the moisture condensation can be effectively prevented, and the testing accuracy is guaranteed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic view showing a closed state of the dew condensation preventing means of the present invention;
FIG. 2 is a schematic view showing the structure of the dewing prevention device of the present invention when it is opened;
FIG. 3 is a schematic view of the structure of the chip carrier base and the chip carrier of the present invention;
FIG. 4 is a schematic view of the front panel of the present invention;
FIG. 5 is a schematic view of the construction of the side panel of the present invention;
FIG. 6 is a schematic structural diagram of a back plate and a cover plate according to the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 6, the present invention provides a condensation preventing device for a semi-enclosed silicon optical chip for low temperature testing, comprising: a wafer stage base 1, an outer plate assembly 2 and a chip wafer stage 3.
And the wafer bearing table base 1 is used for being connected with an external temperature control device to control the temperature and is also used as a fixed support of the outer plate assembly 2. The material of the wafer stage base 1 is an alloy, such as a copper alloy capable of rapid temperature conduction. The external temperature control device is a device capable of adjusting temperature, and any existing temperature control equipment can be adopted, and the external temperature control device has the function of adjusting the temperature of the wafer bearing table base 1 by adjusting the temperature of the energy exchange structure. For example, a refrigerator can be adopted to transmit the cold energy generated by the refrigerator to the wafer bearing table base 1 in an object contact mode, so as to realize the regulation and control of the temperature of the wafer bearing table base 1.
And the chip bearing platform 3 is used for bearing and fixing the silicon optical chip and is connected with the bearing platform base 1 to control the temperature of the silicon optical chip. The material of the chip stage 3 is an alloy, such as a copper alloy capable of rapid temperature conduction. When the external temperature control device controls the temperature of the wafer bearing table base 1, the wafer bearing table base 1 is in contact with the chip bearing table 3 and is made of heat conducting materials, so that the temperature of the chip bearing table 3 can be controlled, and the temperature of the silicon optical chip can be controlled.
Planking subassembly 2 for the steam in isolated environment as far as avoids outside steam and silicon optical chip to contact, forms a semi-enclosed ambient condition simultaneously, and is concrete, and it sets up on wafer bearing platform base 1 and encloses with wafer bearing platform base 1 and establish formation chip test space, and chip wafer bearing platform 3 is located chip test space.
The material of planking subassembly 2 is organic glass, and transparent organic glass is favorable to observing in the test, and the characteristics that conduction temperature performance is poor also can effectually keep warm, improves temperature control's efficiency.
The chip stage 3 includes: a lower support table 301 and an upper test table 302. The upper testing platform 302 is disposed on the top of the lower supporting platform 301, and both are integrally formed.
The upper surface of upper test station 302 forms a chip carrying mesa 303 for placing a silicon optical chip. The lower support platform 301 is provided with an air-extracting channel 304, the upper test platform 302 is provided with a plurality of fixing channels 305 communicated with the air-extracting channel 304, and the upper openings of the fixing channels 305 are located on the chip bearing platform 303. During testing, the silicon optical chip is placed on the chip bearing table 303 and covers the upper opening of the fixed channel 305, so that when external air-extracting equipment extracts air through the air-extracting channel 304, air in the fixed channel 305 is reduced, the pressure is reduced, the silicon optical chip is absorbed, and fixing is completed.
The upper testing platform 302 is further provided with a temperature probe fixing hole 306 for fixing the temperature probe 4 to monitor the temperature of the upper testing platform 302.
The outer panel assembly 2 includes: a front panel 201, two side panels 202, a back panel 203, and a cover panel 204.
The top end of the front panel 201 is provided with a test probe inlet 205, and during testing, the test probe 5 enters the chip testing space through the test probe inlet 205 to perform testing operation. The front panel 201 is further provided with an air inlet 206, the air inlet 206 is connected with an external nitrogen generating device, and nitrogen is filled into the chip testing space through the air inlet 206 so as to ensure that water vapor outside the device does not enter the device. The front panel 201 is further provided with an air extraction device connector 207 at a position corresponding to the air extraction channel 304, and a pipeline of the air extraction device enters the chip test space from the air extraction device connector 207 and is connected with the air extraction channel 304, so that the air in the fixed channel 305 is extracted.
The side plate 202 is further provided with a temperature probe inserting hole 208 at a position corresponding to the temperature probe fixing hole 306, and the temperature probe 4 enters the chip testing space through the temperature probe inserting hole 208 and is finally inserted into the temperature probe fixing hole 306. The side plate 202 is further provided with a coupling adjusting opening 209 for facilitating the optical fiber support 6 to adjust the position of the optical fiber when the optical fiber extends into and couples with the optical fiber.
The back plate 203 is hinged with the wafer bearing table base 1, the cover plate 204 is hinged with the back plate 203, and the part is designed to be a flip cover type, so that the silicon optical chip is convenient to replace during testing. The cover plate 204 is provided with an extension opening 210 communicated with the test probe inlet 205 for facilitating the operation of the test probe 5.
All set up the screw on cushion cap base 1, front panel 201, the curb plate 202, be convenient for pass through the fix with screw with front panel 201 and curb plate 202 on cushion cap base 1. The different functions that are used for satisfying of each organic glass planking shape in the planking subassembly 2, the used organic glass planking of device also can be changed according to different test demands to furthest satisfies the required flexibility of test. Fig. 5 shows typical test requirements of a two-side fiber-in type, and the fiber can be in a single-side mode according to different test requirements.
The organic glass outer plate is manufactured in a machining mode. The test procedure was as follows:
firstly, fixing each organic glass outer plate on a substrate bearing table base 1 through screws, and fixing the substrate bearing table base 1 and a chip substrate bearing table 3 through screws;
then, the silicon optical chip is placed on the chip bearing table 3, and the silicon optical chip is fixed on the chip bearing table 3 in an adsorption manner by air suction;
then, fixing the temperature probe 4;
then, a cover plate 204 in the organic glass outer plate assembly is tightly covered;
then, the gas inlet 206 is filled with nitrogen, and a positive pressure environment is formed in a limited space in the device by continuously introducing the nitrogen into the device, so that water vapor outside the device can be effectively prevented from entering the device;
then, starting an external temperature control device and monitoring the temperature in real time through a temperature probe 4;
finally, a test probe 5 used for testing penetrates through a test probe extending port 205 on the organic glass outer plate to extend into the device, then the test probe is applied to a silicon optical chip to carry out testing, an optical fiber used for testing is fixed on the optical fiber support 6 and extends into the device through a coupling adjusting port 209, and corresponding coupling alignment is carried out in the testing process.
The semi-closed anti-condensation device is used for realizing the low-temperature test of the silicon optical chip, the semi-closed environment provides enough adjusting space for the probe and the optical fiber, and meanwhile, the outer plate assembly of the organic glass can be flexibly assembled and disassembled according to different requirements, so that the low-temperature test of the silicon optical chips with different specifications can be further met.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. The utility model provides a semi-enclosed silicon optical chip anti-condensation device for low temperature test which characterized in that includes:
the wafer bearing table base is connected with an external temperature control device;
the outer plate assembly is arranged on the wafer bearing table base and surrounds the wafer bearing table base to form a chip testing space;
the chip bearing platform is used for bearing a silicon optical chip and is positioned in the chip testing space;
and the outer plate assembly is provided with a coupling adjusting port, a test probe extending port and an air inlet for filling nitrogen into the chip test space.
2. The moisture condensation preventing device for the semi-enclosed silicon optical chip low temperature test according to claim 1, wherein the chip support platform comprises: the chip testing device comprises a lower supporting table and an upper testing table, wherein a chip bearing table surface is formed on the upper surface of the upper testing table;
an air exhaust channel is formed in the lower supporting table, a plurality of fixing channels communicated with the air exhaust channel are formed in the upper testing table, and an upper opening of each fixing channel is located on the chip bearing table.
3. The anti-condensation device for the semi-enclosed silicon optical chip low-temperature test according to claim 2, wherein a temperature probe fixing hole is further formed in the upper test board.
4. The anti-condensation device for the semi-enclosed silicon optical chip low-temperature test according to claim 3, wherein the outer plate assembly comprises: a front panel and two side panels;
the test probe extending port is formed in the top end of the front panel, the air inlet is formed in the front panel, and an air extraction equipment connecting port is formed in the position, corresponding to the air extraction channel, of the front panel;
the coupling adjusting opening is formed in the side plate, and a temperature measuring probe inserting hole is further formed in the position, corresponding to the temperature measuring probe fixing hole, of the side plate.
5. The moisture condensation preventing device for the semi-enclosed silicon optical chip low temperature test according to claim 4, wherein the outer plate assembly further comprises: a back plate and a cover plate;
the back plate is hinged with the wafer bearing table base, and the cover plate is hinged with the back plate;
and the cover plate is provided with an expansion port communicated with the test probe extending inlet.
6. The anti-condensation device for the semi-closed silicon photonic chip low-temperature test according to claim 5, wherein the outer plate component is made of organic glass.
7. The moisture condensation preventing device for the semi-enclosed silicon optical chip low temperature test according to claim 6, wherein the material of the wafer bearing table base and the material of the chip bearing table are alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210854262.9A CN115201525A (en) | 2022-07-14 | 2022-07-14 | Anti-condensation device for semi-closed silicon optical chip low-temperature test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210854262.9A CN115201525A (en) | 2022-07-14 | 2022-07-14 | Anti-condensation device for semi-closed silicon optical chip low-temperature test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115201525A true CN115201525A (en) | 2022-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210854262.9A Pending CN115201525A (en) | 2022-07-14 | 2022-07-14 | Anti-condensation device for semi-closed silicon optical chip low-temperature test |
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| CN (1) | CN115201525A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220277A (en) * | 1991-03-26 | 1993-06-15 | Erich Reitinger | Arrangement for testing semiconductor wafers or the like |
| US20030137317A1 (en) * | 2002-01-07 | 2003-07-24 | Samsung Electronics Co., Ltd. | Test systems for semiconductor devices |
| US20040070415A1 (en) * | 2002-10-02 | 2004-04-15 | Stefan Schneidewind | Test apparatus for testing substrates at low temperatures |
| US20080143365A1 (en) * | 2006-11-08 | 2008-06-19 | Suss Micro Tec Test Systems Gmbh | Probe station and method for measurements of semiconductor devices under defined atmosphere |
| CN203287484U (en) * | 2013-04-26 | 2013-11-13 | 东莞市福地电子材料有限公司 | Flip LED chip tester |
| CN107030022A (en) * | 2017-04-15 | 2017-08-11 | 江苏怡通控制系统有限公司 | The temperature sorting and pressure-resistant automatic test machine of a kind of 17AM temperature protectors |
| CN209264789U (en) * | 2018-12-07 | 2019-08-16 | 苏州苏纳光电有限公司 | It is capable of the test probe station of Cryogenic Temperature Swing test |
| US20200355740A1 (en) * | 2019-05-06 | 2020-11-12 | One Test Systems | Testing apparatus |
| EP3830590A1 (en) * | 2018-07-30 | 2021-06-09 | Microtest S.r.l. | Built-in machinery to carry out temperature- dependent tests on electronic components such as chips |
| CN113465735A (en) * | 2021-07-11 | 2021-10-01 | Nano科技(北京)有限公司 | Concave structure anti-dewing device for low-temperature measurement of photoelectric detector chip |
-
2022
- 2022-07-14 CN CN202210854262.9A patent/CN115201525A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220277A (en) * | 1991-03-26 | 1993-06-15 | Erich Reitinger | Arrangement for testing semiconductor wafers or the like |
| US20030137317A1 (en) * | 2002-01-07 | 2003-07-24 | Samsung Electronics Co., Ltd. | Test systems for semiconductor devices |
| US20040070415A1 (en) * | 2002-10-02 | 2004-04-15 | Stefan Schneidewind | Test apparatus for testing substrates at low temperatures |
| US20080143365A1 (en) * | 2006-11-08 | 2008-06-19 | Suss Micro Tec Test Systems Gmbh | Probe station and method for measurements of semiconductor devices under defined atmosphere |
| CN203287484U (en) * | 2013-04-26 | 2013-11-13 | 东莞市福地电子材料有限公司 | Flip LED chip tester |
| CN107030022A (en) * | 2017-04-15 | 2017-08-11 | 江苏怡通控制系统有限公司 | The temperature sorting and pressure-resistant automatic test machine of a kind of 17AM temperature protectors |
| EP3830590A1 (en) * | 2018-07-30 | 2021-06-09 | Microtest S.r.l. | Built-in machinery to carry out temperature- dependent tests on electronic components such as chips |
| CN209264789U (en) * | 2018-12-07 | 2019-08-16 | 苏州苏纳光电有限公司 | It is capable of the test probe station of Cryogenic Temperature Swing test |
| US20200355740A1 (en) * | 2019-05-06 | 2020-11-12 | One Test Systems | Testing apparatus |
| CN113465735A (en) * | 2021-07-11 | 2021-10-01 | Nano科技(北京)有限公司 | Concave structure anti-dewing device for low-temperature measurement of photoelectric detector chip |
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