CN115188842A - Ge avalanche photodiode on Si substrate and manufacturing method thereof - Google Patents
Ge avalanche photodiode on Si substrate and manufacturing method thereof Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 101
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- 229910052732 germanium Inorganic materials 0.000 claims abstract description 71
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 71
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Abstract
The invention relates to a Ge avalanche photodiode on a Si substrate and a manufacturing method thereof. A Ge avalanche photodiode on a Si substrate comprises, stacked from bottom to top in sequence: a lower doped silicon region, an intrinsic silicon multiplication layer, a middle doped silicon layer, an intrinsic germanium absorption layer, an upper doped germanium layer, wherein at least the upper doped germanium layer of the intrinsic germanium absorption layer and the upper doped germanium layer is black germanium; the lower doped silicon layer and the upper doped germanium layer are also respectively connected with electrodes. The invention solves the problem that the existing APDs have low absorption coefficient and absorptivity for the wavelength of more than 1.4 mu m.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a Ge avalanche photodiode on a Si substrate and a manufacturing method thereof.
Background
The core components of laser radar (LiDAR, light Detection and Ranging) include: a transmitting system, a signal processing system, a receiving system and the like. Currently, the emitting and receiving ends of commercial LiDAR are typically low cost 0.9 μm infrared semiconductor laser arrays and silicon Avalanche Photodiodes (APDs), but they do not meet the "eye safety" requirements. In order to solve the problem of eye safety, the working wavelength of the infrared laser needs to be expanded to more than 1.4 μm. Therefore, short-wave Infrared (SWIR) APDs are required to be equipped at the receiving system side. The commercialized InGaAs/InP SWIR APDs have problems of expensive manufacturing process, small wafer size, high post-pulse effect, long dead time, high dark count rate, and the like. The Ge semiconductor material as the four-family Ge semiconductor material has the advantages of adjustable band gap, high absorption coefficient (up to 1.55 mu m), large wafer size, low manufacturing cost, compatibility with a Si CMOS process, easiness in batch production and the like, and is widely concerned by scientific researchers at home and abroad.
In conventional Ge/Si SWIR APDs, a Si layer and a Ge epilayer are employed as a multiplication region and an absorption region, respectively. Due to the intrinsic absorption characteristics of Ge epilayers, the performance of the device is much weaker than 1.31 μm at operating wavelengths longer than 1.4 μm, making it difficult to meet the requirements of "eye-safe" LiDAR chips. Therefore, improving the absorption efficiency of the Ge absorbing layer is the basis for developing high-performance Ge/Si SWIR APDs and is one of the important research contents for realizing low-cost LiDAR.
The invention is therefore set forth.
Disclosure of Invention
The invention mainly aims to provide a Ge avalanche photodiode on a Si substrate and a manufacturing method thereof, which solve the problems of low absorption coefficient and low absorption rate of APDs for wavelengths of more than 1.4 mu m.
In order to achieve the above object, the present invention provides the following technical solutions.
The first aspect of the invention provides a Ge avalanche photodiode on a Si substrate, comprising, stacked in order from bottom to top:
a lower region of doped silicon is provided,
an intrinsic silicon multiplication layer is provided on the substrate,
a middle layer of doped silicon is provided,
an intrinsic germanium-absorbing layer is provided,
an upper portion of the doped germanium layer,
wherein at least the upper doped germanium layer of the intrinsic germanium absorption layer and the upper doped germanium layer is black germanium;
the lower doped silicon layer and the upper doped germanium layer are also respectively connected with electrodes.
The invention improves the structure of the uppermost germanium-doped layer of the avalanche photodiode, so that the germanium absorption layer below the avalanche photodiode has a black effect, and the light wave absorption rate of 1.4 mu m or more reaches more than 90 percent, even more than 99 percent, therefore, the avalanche photodiode can also be called as a black Ge avalanche photodiode on a Si substrate. The black germanium is a material with a rough surface, and includes but is not limited to a nano-sized bur shape, a random tapered bur shape, a grass shape, a pyramid shape, a nano-wire, a porous structure and the like, and the shapes can reach the intrinsic germanium absorption layer.
The doping type for the regions and layers depends on the use of the diode, for example on the type of electron multiplication or hole multiplication, electron multiplication being the most widely used at present.
When an electron-multiplying diode is employed, the doping of the lower doped silicon region is n-doped and the doping of the middle doped silicon layer and the upper doped germanium layer is p-doped.
When the diode with hole multiplication is adopted, the types of all doped layers of the diode with electron multiplication are replaced, specifically, n doping is changed into p doping, and p doping is changed into n doping.
In some embodiments, the intrinsic silicon multiplication layer has a recessed region on an upper surface thereof, and the middle doped silicon layer is located in the recessed region.
By adopting the structure, the problem of edge leakage or edge breakdown can be effectively reduced.
In some embodiments, the black germanium has a depth of 0.01 to 4 μm and a diameter of 0.01 to 1 μm to significantly improve the absorption at wavelengths in the range of 1.4 to 2.0 μm.
In some embodiments, the lower doped silicon region is a doped silicon substrate or a structure with a doped silicon layer on an undoped silicon substrate. The two types of diodes have the advantages that the cost is low, and the thickness of the doped silicon layer is controllable.
In some embodiments, the electrode is a transparent electrode.
In some embodiments, the thicknesses of the intrinsic silicon multiplication layer, the middle doped silicon layer, the intrinsic germanium absorption layer and the upper doped germanium layer are 0.5-2 μm, 80-120 nm, 0.5-3 μm and 80-120 nm, respectively.
In some embodiments, the lower doped silicon region is a doped silicon layer on an undoped silicon substrate, and the doped silicon layer has a thickness of 0.5-2 μm.
A second aspect of the present invention provides a method of manufacturing the Ge avalanche photodiode on a Si substrate described above, including the steps of:
firstly, the following structures are formed and stacked from bottom to top in sequence: a lower doped silicon region, an intrinsic silicon multiplication layer, an intermediate doped silicon layer, an epitaxial germanium layer,
doping the shallow surface layer of the epitaxial germanium layer to form an upper doped germanium layer, wherein the residual germanium layer below is an intrinsic germanium absorption layer;
etching the upper doped germanium layer or the upper doped germanium layer and the intrinsic germanium absorption layer to form black germanium;
electrodes are drawn from the lower doped silicon layer and the upper doped germanium layer.
The compatibility of the process and the existing APDs is good, and the product upgrading difficulty is reduced.
In some embodiments, the intrinsic silicon multiplication layer and the intermediate doped silicon layer are formed using the following method:
a silicon film is formed over the lower doped silicon region, and then the central region of the shallow surface of the silicon film is doped to form a middle doped silicon layer, with the remaining silicon film acting as an intrinsic silicon multiplication layer.
Or, the intrinsic silicon multiplication layer and the middle doped silicon layer are formed by the following method:
forming a silicon film as an intrinsic silicon multiplication layer over the lower doped silicon region;
a doped silicon layer is then deposited over the intrinsic silicon multiplication layer as an intermediate doped silicon layer.
In some embodiments, the means for etching the upper doped germanium layer is one or more of the following in combination:
SF 6 inFemtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (Cl) 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
In some embodiments, before the extraction electrode, further comprising:
forming a mesa that exposes at least a portion of a surface of the lower doped silicon region and at least a surface of the upper doped germanium layer;
then forming a passivation layer covering the surface of the mesa;
and etching the passivation layer to form a contact hole for leading out an electrode.
In summary, compared with the prior art, the invention achieves the following technical effects:
(1) The invention can realize the high-efficiency absorption of the black Ge absorption layer to the laser with the wavelength of more than 1.4 mu m by means of the ultralow reflection characteristic of the black Ge absorption layer, effectively expands the detection wavelength range to 2.0 mu m, has the advantage of low scattering, and simultaneously meets the requirement of LiDAR eye safety.
(2) The invention provides a preparation scheme of black Ge/Si SWIR APDs, which is beneficial to promoting the rapid development of low-cost eye-safe LiDAR chips and has great research significance and economic benefit.
Drawings
Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 to 5 are schematic structural diagrams obtained at steps of a method for manufacturing a Ge avalanche photodiode on a Si substrate according to embodiment 1 of the present invention;
fig. 6-10 are schematic structural diagrams obtained by steps of a method for manufacturing a Ge avalanche photodiode on a Si substrate according to embodiment 2 of the present invention;
fig. 11 to 15 are schematic structural diagrams obtained at respective steps of a method for manufacturing a Ge avalanche photodiode on a Si substrate according to embodiment 3 of the present invention;
fig. 16 to 20 are schematic structural diagrams obtained in steps of the method for manufacturing a Ge avalanche photodiode on a Si substrate according to embodiment 4 of the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
As mentioned in the background art, the Ge absorption layer of the existing APDs has low absorption coefficient and absorption efficiency when the working wavelength is more than 1.4 μm, and the device performance is poor. Therefore, the invention improves the shapes of the germanium absorption layer and the contact layer on the germanium absorption layer to improve the absorptivity and absorption coefficient of the wavelength of more than 1.4 μm, especially 1.4 μm-2.0 μm.
The germanium in the Ge avalanche photodiode on the Si substrate has the structural characteristic of 'black germanium', and the method is as follows.
A Ge avalanche photodiode on a Si substrate comprises, stacked from bottom to top in sequence:
a lower region of doped silicon is provided,
an intrinsic silicon multiplication layer is formed on the silicon substrate,
a middle doped silicon layer is arranged between the silicon substrate and the silicon substrate,
an intrinsic germanium-absorbing layer is formed on the substrate,
an upper portion of the doped germanium layer,
wherein at least the upper doped germanium layer of the intrinsic germanium absorption layer and the upper doped germanium layer is black germanium;
the lower doped silicon layer and the upper doped germanium layer are also respectively connected with electrodes.
The invention just utilizes the black germanium to improve the absorptivity and broaden the wavelength range, and experiments prove that the absorptivity of the black germanium on the wavelength of more than 1.4 mu m reaches more than 90 percent, even more than 99 percent.
On the basis, parameters such as the material type, the shape and the thickness of each layer of the diode can be optimized, so that the light absorption rate or the sensitivity can be further improved.
For example, optimizing the relationship of the intrinsic silicon multiplication layer and the intermediate doped silicon layer: the upper surface of the intrinsic silicon multiplication layer is provided with a sunken area, and the middle doped silicon layer is positioned in the sunken area. This reduces edge leakage or breakdown problems.
The size of the black germanium is optimized, the depth of the black germanium is 0.01-4 mu m, and the diameter of the black germanium is 0.01-1 mu m.
The material of the electrode is optimized, and a transparent electrode is adopted.
The thicknesses of all the layers are optimized, and the thicknesses of the intrinsic silicon multiplication layer, the middle doped silicon layer, the intrinsic germanium absorption layer and the upper doped germanium layer are preferably 0.5-2 mu m, 80-120 nm, 0.5-3 mu m and 80-120 nm respectively. Further, the lower doped silicon region is a structure in which a doped silicon layer is disposed on an undoped silicon substrate, and the thickness of the doped silicon layer is preferably 0.5 to 2 μm.
Optimizing a doping type, the doping of the lower doped silicon region being n-doped and the doping of the middle doped silicon layer and the upper doped germanium layer being p-doped.
The invention also provides a manufacturing method of the Ge avalanche photodiode on the Si substrate, which mainly comprises three main stages of substrate manufacturing, black Ge forming, table top and electrode manufacturing and the like.
The fabrication process of the present invention is described below by way of example for an electron-multiplying avalanche photodiode.
Example 1
(1) And (3) manufacturing a Ge/Si substrate:
providing an n + -Si substrate 101 as a starting material, forming an i-Si avalanche layer with a thickness of 0.5-2 μm, namely an i-Si multiplication layer 102, extending a p-Si charge layer 103 with a thickness of 100nm on the i-Si multiplication layer 102, extending a Ge absorption layer 104 with a thickness of 0.5-3 μm on the p-Si charge layer 103, and doping to form a p + -Ge contact layer 105 with a thickness of 100nm, thereby obtaining the structure shown in FIG. 1. The above dimensions are merely exemplary and do not limit the scope of the invention, e.g., the thickness of the p + -Ge layer can be adjusted between 80nm and 120nm. In addition, the means for forming each layer may employ various typical deposition methods such as PECVD, LPCVD, ALD, CVD, and the like, in addition to epitaxy. The type of element to be doped is also not limited, and the same element is preferably used for the same type of doping. The doping concentration is adjusted as required.
(2) Manufacturing a black Ge/Si substrate:
the p + -Ge contact layer 105 shown in fig. 1 is etched to form a nano-sized burr 107 as shown in fig. 2. The etching means is one or more of the following combinations:
SF 6 in femtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (1), cl 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
The burr size can be controlled to be 0.01-4 μm in depth and 0.01-1 μm in diameter. The burrs may also penetrate deep into the Ge-absorbing layer.
The burr shape in this embodiment is merely an example, and actually, it may be replaced with a random tapered spike, a grass shape, a pyramid shape, a nanowire, a porous structure, or the like.
(3) Leading out an electrode:
forming a table top: exposing at least a portion of a surface of the p + -Ge contact layer 105 and at least an upper surface of the n + -Si substrate, as shown in FIG. 3; this step can be achieved by means of contact masking and etching.
Forming a passivation layer 108: an insulating material passivation layer such as silicon oxide is formed on the surface where the mesa is formed in the previous step, as shown in fig. 4.
Etching a contact hole and filling an electrode: contact holes are etched in the passivation layer and filled with electrode material to form n-type ohmic contacts 109 and p-type ohmic contacts 110, as shown in fig. 5.
In other embodiments, the mesa shape is not limited to that shown in fig. 3, as long as the extraction electrodes can meet practical requirements of high integration level, low resistance, and the like.
Example 2
(1) Ge/Si substrate fabrication
Providing an i-Si substrate 206 as a starting material, epitaxially growing a 0.5-2 μm thick n + -Si layer 201 on the i-Si substrate 206 to form a 0.5-2 μm thick i-Si multiplication layer 202, epitaxially growing a 100nm thick p-Si charge layer 203 on the i-Si multiplication layer 202, epitaxially growing a 0.5-3 μm thick Ge absorption layer 204 on the p-Si charge layer 203, and forming a 100nm thick p + -Ge contact layer 205 to obtain the structure shown in FIG. 6. In other embodiments, the thickness, formation means, and dopant element type and concentration of each layer may be adjusted.
(2) Manufacturing a black Ge/Si substrate:
the p + -Ge contact layer 205 shown in fig. 6 is etched to form a nano-sized burr 207 shape as shown in fig. 7. The etching means is one or more of the following combinations:
SF 6 femtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (1), cl 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
The burr size can be controlled to be 0.01-4 μm in depth and 0.01-1 μm in diameter. The burrs may also reach deep into the Ge-absorbing layer.
The burr shape in this embodiment is merely an example, and may be replaced with a random tapered spike, a grass shape, a pyramid shape, a nanowire, a porous structure, or the like. (3) leading out electrodes:
forming a table top: exposing at least a portion of a surface of the p + -Ge contact layer 205 and at least an upper surface of the n + -Si layer 201, as shown in FIG. 8; this step can be achieved by means of contact masking and etching.
Forming a passivation layer 208: a passivation layer of an insulating material such as silicon oxide is formed on the surface of the mesa formed in the previous step, as shown in fig. 9.
Etching a contact hole and filling an electrode: contact holes are etched in the passivation layer 208 and filled with electrode material to form n-type ohmic contacts 209 and p-type ohmic contacts 210, as shown in fig. 10.
In other embodiments, the mesa shape is not limited to that shown in fig. 8, as long as the extraction electrodes can meet practical requirements of high integration level, low resistance, and the like.
Example 3
(1) Ge/Si substrate fabrication
An i-Si substrate 306 is provided as a starting material, a 0.5-2 μm thick n + -Si layer 301 is epitaxially formed on the i-Si substrate 306, a 0.5-2 μm thick i-Si multiplication layer 302 is formed, a 100nm thick p-Si charge layer 303 is formed in the i-Si multiplication layer 302, a 0.5-3 μm thick Ge absorption layer 304 is epitaxially formed on the p-Si charge layer, and a 100nm thick p + -Ge contact layer 305 is formed, resulting in the structure shown in FIG. 11.
(2) Manufacturing a black Ge/Si substrate:
the p + -Ge contact layer 305 shown in fig. 11 is etched to form a nano-sized burr 307 shape as shown in fig. 12. The etching means is one or more of the following combinations:
SF 6 femtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (Cl) 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
The burr size can be controlled to be 0.01-4 μm in depth and 0.01-1 μm in diameter. The burrs may also reach deep into the Ge-absorbing layer.
The burr shape in this embodiment is merely an example, and actually, it may be replaced with a random tapered spike, a grass shape, a pyramid shape, a nanowire, a porous structure, or the like. (3) leading out electrodes:
forming a table top: exposing at least a portion of a surface of the p + -Ge contact layer 305 and at least an upper surface of the n + -Si layer 301, as shown in FIG. 13; this step can be achieved by means of contact masking and etching.
Forming a passivation layer 308: a passivation layer of an insulating material such as silicon oxide is formed on the surface where the mesa is formed in the previous step, as shown in fig. 14.
Etching a contact hole and filling an electrode: contact holes are etched in the passivation layer 308 and filled with electrode material to form n-type ohmic contacts 309 and p-type ohmic contacts 310, as shown in fig. 15.
In other embodiments, the mesa shape is not limited to that shown in fig. 13, as long as the extraction electrodes can satisfy practical requirements such as high integration and low resistance.
Example 4
(1) Ge/Si substrate fabrication
An n + -Si substrate 401 is provided as a starting material, an i-Si multiplication layer 402 with a thickness of 0.5-2 μm is epitaxial, a p-Si charge layer 403 with a thickness of 100nm is formed in the i-Si multiplication layer 402, a Ge absorption layer 404 with a thickness of 0.5-3 μm is epitaxial on the p-Si charge layer 403, and a p + -Ge contact layer 405 with a thickness of 100nm is formed, resulting in the structure shown in FIG. 16.
(2) Manufacturing a black Ge/Si substrate:
the p + -Ge contact layer 405 shown in fig. 16 is etched to form a shape of a burr 407 of a nano size as shown in fig. 17. The etching means is one or more of the following combinations:
SF 6 femtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (Cl) 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
The burr size can be controlled to be 0.01-4 μm in depth and 0.01-1 μm in diameter. The burrs may also reach deep into the Ge-absorbing layer.
The burr shape in this embodiment is merely an example, and actually, it may be replaced with a random tapered spike, a grass shape, a pyramid shape, a nanowire, a porous structure, or the like.
(3) Leading out an electrode:
forming a table top: exposing at least a portion of a surface of the p + -Ge contact layer 405, as shown in FIG. 18; this step can be achieved by means of contact masking and etching.
Forming a passivation layer 408: a passivation layer of an insulating material such as silicon oxide is formed on the surface where the mesa is formed in the previous step, as shown in fig. 19.
Etching a contact hole and filling an electrode: contact holes are etched in the passivation layer 408 and filled with electrode material to form p-type ohmic contacts 410, while the back side of the n + -Si substrate 401 is metallized to form n-type ohmic contacts 409, as shown in fig. 20.
In other embodiments, the mesa shape is not limited to that shown in fig. 18, as long as the extraction electrodes can satisfy practical requirements such as high integration and low resistance.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (12)
1. A Ge avalanche photodiode on a Si substrate is characterized by comprising the following components which are stacked in sequence from bottom to top:
a lower region of doped silicon is provided,
an intrinsic silicon multiplication layer is formed on the silicon substrate,
a middle layer of doped silicon is provided,
an intrinsic germanium-absorbing layer is formed on the substrate,
an upper portion of the doped germanium layer,
wherein at least the upper doped germanium layer of the intrinsic germanium absorption layer and the upper doped germanium layer is black germanium;
the lower doped silicon layer and the upper doped germanium layer are also respectively connected with electrodes.
2. The Ge avalanche photodiode on a Si substrate of claim 1, wherein an upper surface of said intrinsic silicon multiplication layer is provided with a recessed region, said intermediate doped silicon layer being located in said recessed region.
3. The Ge avalanche photodiode on a Si substrate according to claim 1, wherein the black germanium has a depth of 0.01 to 4 μm and a diameter of 0.01 to 1 μm.
4. The Ge avalanche photodiode on a Si substrate of claim 1 wherein the lower doped silicon region is a doped silicon substrate or a structure with a doped silicon layer on an undoped silicon substrate.
5. The Ge avalanche photodiode on a Si substrate of any one of claims 1 to 4 wherein the doping of the lower doped silicon region is n-doped and the doping of the intermediate doped silicon layer and the upper doped germanium layer is p-doped.
6. The Ge avalanche photodiode on a Si substrate of claim 1, wherein the electrode is a transparent electrode.
7. The Ge avalanche photodiode on a Si substrate as claimed in claim 1, wherein the thicknesses of said intrinsic silicon multiplication layer, intermediate doped silicon layer, intrinsic germanium absorption layer, upper doped germanium layer are 0.5-2 μm, 80-120 nm, 0.5-3 μm, 80-120 nm, respectively.
8. The Ge avalanche photodiode on a Si substrate of claim 7 wherein the lower doped silicon region is a doped silicon layer on an undoped silicon substrate, the doped silicon layer having a thickness of 0.5 to 2 μm.
9. The method of fabricating a Ge avalanche photodiode on a Si substrate as claimed in any one of claims 1 to 8, comprising the steps of:
firstly, the following structures are formed and stacked from bottom to top in sequence: a lower doped Si region, an intrinsic Si multiplication layer, an intermediate doped Si layer, an epitaxial Ge layer,
doping the shallow surface layer of the epitaxial germanium layer to form an upper doped germanium layer, wherein the residual germanium layer below is an intrinsic germanium absorption layer;
etching the upper doped germanium layer or the upper doped germanium layer and the intrinsic germanium absorption layer to form black germanium;
extracting electrodes from the lower doped silicon layer and the upper doped germanium layer.
10. The method of manufacturing of claim 9 wherein the intrinsic silicon multiplication layer and the intermediate doped silicon layer are formed by:
a silicon film is formed over the lower doped silicon region, and then the central region of the shallow surface of the silicon film is doped to form a middle doped silicon layer, with the remaining silicon film acting as an intrinsic silicon multiplication layer.
Or, the intrinsic silicon multiplication layer and the middle doped silicon layer are formed by the following method:
forming a silicon film as an intrinsic silicon multiplication layer over the lower doped silicon region;
a doped silicon layer is then deposited over the intrinsic silicon multiplication layer as an intermediate doped silicon layer.
11. The method of manufacturing of claim 9, wherein the means of etching the upper doped germanium layer is one or more of the following in combination:
SF 6 in femtosecond laser irradiation based on SF 6 Inductively coupled plasma etching of (1), cl 2 Radical reactive ion etching based on SF 6 The ICP-RIE process of (1), metal assisted chemical etching.
12. The manufacturing method according to claim 9, further comprising, before the extraction electrode:
forming a mesa that exposes at least a portion of a surface of the lower doped silicon region and at least a surface of the upper doped germanium layer;
then forming a passivation layer covering the surface of the mesa;
and etching the passivation layer to form a contact hole for leading out an electrode.
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