CN115188802A - Structure and manufacturing method of floating ring and electronic equipment - Google Patents

Structure and manufacturing method of floating ring and electronic equipment Download PDF

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Publication number
CN115188802A
CN115188802A CN202211095172.2A CN202211095172A CN115188802A CN 115188802 A CN115188802 A CN 115188802A CN 202211095172 A CN202211095172 A CN 202211095172A CN 115188802 A CN115188802 A CN 115188802A
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Prior art keywords
layer
ring
floating
annular
dielectric
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CN202211095172.2A
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张枫
刘杰
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Shenzhen Xiner Semiconductor Technology Co Ltd
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Shenzhen Xiner Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring

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Abstract

A structure, a manufacturing method and electronic equipment of a floating ring belong to the technical field of semiconductors, and the structure comprises an epitaxial layer, a dielectric layer and a plurality of sub-floating rings which are nested layer by layer; the dielectric layer is arranged on the upper surface of the epitaxial layer; the sub-floating ring comprises an annular floating junction, an annular groove, a first conducting ring, a second conducting ring and a dielectric ring; the annular floating junction is buried in the epitaxial layer; the annular groove is positioned on the upper surface of the annular floating joint; the first conducting ring is positioned on the inner side wall of the annular groove; the second conducting ring is positioned on the outer side wall of the annular groove; the dielectric ring is filled between the first conductive ring and the second conductive ring; therefore, a plurality of embedded super-junction structures are formed by the embedded annular floating junctions and the epitaxial layers which are nested layer by layer, the depth of the super-junction structures is deeper, the longitudinal electric field distribution is improved, and the longitudinal voltage-resisting capacity of the device is improved; meanwhile, a capacitor is formed between the first conductive ring and the second conductive ring, and the transverse voltage resistance of the device is improved.

Description

Structure and manufacturing method of floating ring and electronic equipment
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a structure and a manufacturing method of a floating ring and electronic equipment.
Background
Silicon carbide has been widely used in industrial control, power electronics, and automotive electronics as a main force of the third generation semiconductor, and the terminal withstand voltage of silicon carbide has been a critical issue due to the characteristics of the material itself.
The conventional silicon carbide voltage-resistant terminal generally adopts a floating ring form, as shown in fig. 1, but due to the characteristics of silicon carbide, the junction depth can only be about 1um, and the characteristics affect the voltage-resistant capability and reliability of silicon carbide.
Disclosure of Invention
The present application aims to provide a structure of a floating ring, a manufacturing method thereof, and an electronic device, and aims to solve the problems of weak pressure resistance and poor reliability of the related floating ring.
The embodiment of the application provides a structure of floating ring, includes:
the device comprises an epitaxial layer, a dielectric layer and a plurality of sub floating rings nested layer by layer; the dielectric layer is arranged on the upper surface of the epitaxial layer;
the sub-floating ring includes:
a ring-shaped floating junction buried in the epitaxial layer;
the annular groove is positioned on the upper surface of the annular floating junction;
the first conducting ring is positioned on the inner side wall of the annular groove;
the second conducting ring is positioned on the outer side wall of the annular groove;
a dielectric ring filled between the first conductive ring and the second conductive ring.
In one embodiment, the upper surface of the groove is higher than the upper surface of the epitaxial layer and lower than the upper surface of the dielectric layer.
In one embodiment, the inner side wall of the annular groove and the inner side wall of the annular floating junction are located on the same curved surface, and the outer side wall of the annular groove and the outer side wall of the annular floating junction are located on the same curved surface.
In one embodiment, the width of the sub-floating ring at the periphery is smaller than the width of the sub-floating ring at the inner part, and the width of the sub-floating ring is the distance between the inner side wall of the annular floating junction and the outer side wall of the annular floating junction.
In one embodiment, the first and second conductive rings are polysilicon, the dielectric layer and the dielectric ring are silicon dioxide, the floating junction is a P-type floating junction, and the epitaxial layer is an N-type epitaxial layer.
In one embodiment, the system further comprises a cellular; the unit cell is located at a central region of the plurality of sub floating rings.
The embodiment of the present application further provides a manufacturing method of a floating ring, where the manufacturing method includes:
forming an epitaxial layer;
forming a mask layer on the upper surface of the epitaxial layer; the mask layer comprises a plurality of first annular grooves;
removing a part of the epitaxial layer to form a plurality of second annular grooves;
forming a conductive layer on an upper surface of the epitaxial layer and an upper surface of the plurality of second annular trenches;
removing an upper surface of the conductive layer and leaving the conductive layer of side surfaces of the plurality of second annular trenches to form a composite layer; the composite layer has a plurality of third annular grooves;
ion implantation is carried out on the upper surface of the composite layer to form an annular floating junction;
filling a plurality of the third annular grooves to form a dielectric ring, and forming a first dielectric layer on the upper surface of the composite layer;
the mask layer and the first dielectric layer are made of the same material, and the mask layer of the first dielectric layer and the mask layer form a dielectric layer together.
In one embodiment, the forming a mask layer on the upper surface of the epitaxial layer includes:
forming a silicon dioxide layer on the upper surface of the epitaxial layer;
and removing part of the silicon dioxide layer to form the mask layer.
In one embodiment, the method further comprises the following steps:
forming a cell in a central region of the plurality of third annular trenches.
The embodiment of the application also provides electronic equipment, and the electronic equipment comprises the structure of the floating ring.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the structure of the floating ring comprises an epitaxial layer, a dielectric layer and a plurality of sub-floating rings which are nested layer by layer, wherein each sub-floating ring comprises an annular floating junction, an annular groove, a first conducting ring, a second conducting ring and a dielectric ring; meanwhile, as the dielectric ring is filled between the first conductive ring and the second conductive ring, a capacitor is formed between the first conductive ring and the second conductive ring, and the transverse voltage resistance of the device is improved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic structural view of a prior art floating ring structure;
FIG. 2 is a schematic structural diagram of a floating ring structure provided in an embodiment of the present application;
FIG. 3 isbase:Sub>A sectional view taken in the direction A-A of the structure of the floating ring shown in FIG. 2;
FIG. 4 is a structural schematic diagram of a structure of a floating ring according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating the formation of an epitaxial layer in a method of fabricating a floating ring according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating the formation of a silicon dioxide layer in the method for fabricating a floating ring according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating the formation of a mask layer in a method for fabricating a floating ring according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram illustrating the formation of a second annular trench in a method of fabricating a floating ring according to an embodiment of the present application;
FIG. 9 is a schematic diagram illustrating the formation of a conductive layer in a method for fabricating a floating ring according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram illustrating the formation of a composite layer in the method for manufacturing a floating ring according to an embodiment of the present application;
FIG. 11 is a schematic diagram illustrating the formation of an annular floating junction in a method of fabricating a floating ring according to an embodiment of the present application;
fig. 12 is a schematic diagram illustrating the formation of a dielectric ring and a first dielectric layer in a method for fabricating a floating ring according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings to facilitate the description of the application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be constructed in operation as a limitation of the application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 2 and 3 illustrate a module structure of a floating ring provided by an embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are illustrated, and detailed descriptions are as follows:
the structure of the floating ring comprises an epitaxial layer 11, a dielectric layer 12 and a plurality of sub floating rings 13 which are nested layer by layer; the dielectric layer 12 is disposed on the upper surface of the epitaxial layer 11.
The sub-floating ring 13 includes an annular floating junction 14, an annular groove 15, a first conductive ring 16, a second conductive ring 17, and a dielectric ring 18.
A ring-shaped floating junction 14 is buried in the epitaxial layer 11; the annular groove 15 is positioned on the upper surface of the annular floating junction 14; the first conductive ring 16 is located on the inner side wall of the annular groove 15; the second conductive ring 17 is positioned on the outer side wall of the annular groove 15; a dielectric ring 18 is filled between the first conductive ring 16 and the second conductive ring 17.
Note that the upper surface of the recess is higher than the upper surface of the epitaxial layer 11 and lower than the upper surface of the dielectric layer 12.
Since the upper surface of the groove is lower than the upper surface of the dielectric layer 12, the first conductive ring 16 and the second conductive ring 17 cover the dielectric layer 12, preventing an external voltage from being connected to the first conductive ring 16 or the second conductive ring 17 and breaking down the device, and improving the reliability and safety of the device.
It is emphasized that the inner sidewall of the annular groove 15 and the inner sidewall of the annular floating junction 14 are located on the same curved surface, and the outer sidewall of the annular groove 15 and the outer sidewall of the annular floating junction 14 are located on the same curved surface. The first conductive ring 16 is located on the inner side wall of the annular floating junction 14, the second conductive ring 17 is located on the outer side wall of the annular floating junction 14, and the dielectric ring 18 is filled between the first conductive ring 16 and the second conductive ring 17, so that the capacitance between the first conductive ring 16 and the second conductive ring 17 is possibly increased, and the voltage endurance capability of the device is improved.
By way of example and not limitation, the width of the outer sub-floating ring 13 is less than the width of the inner sub-floating ring 13, and the width of the sub-floating ring 13 is the distance between the inner sidewall of the annular floating junction 14 and the outer sidewall of the annular floating junction 14.
By way of example and not limitation, first conductive ring 16 and second conductive ring 17 are polysilicon, dielectric layers 12 and 18 are silicon dioxide, annular floating junction 14 is a P-type floating junction, and epitaxial layer 11 is an N-type epitaxial layer 11.
A plurality of annular P-type floating junctions and the N-type epitaxial layer 11 form a plurality of super junction structures, a transverse electric field is generated, pn junctions are depleted, and accordingly breakdown resistance and voltage withstanding capability are improved.
As shown in fig. 4, the structure of the floating ring further includes a cell 19; the unit cell 19 is located in the central region of the plurality of sub-floating rings 13.
The unit cell 19 is disposed in the center region of the plurality of sub-floating rings 13 so that the unit cell 19 forms a lateral electric field to the edge region of the sub-floating rings 13, and since the lateral electric field is applied to a plurality of capacitances formed by the plurality of super junction structures formed by the plurality of annular floating junctions 14 and the epitaxial layer 11, the plurality of first conductive rings 16, and the plurality of second conductive rings 17, the withstand voltage capability of the unit cell 19 is improved.
In accordance with one embodiment of the floating ring, the present invention also provides an embodiment of a method of manufacturing a floating ring.
A method for manufacturing a floating ring comprises steps 401 to 406.
In step 401, as shown in fig. 5, an epitaxial layer 11 is formed. In a specific implementation, the N-type epitaxial layer 11 may be formed.
In step 402, a mask layer 121 is formed on the upper surface of the epitaxial layer 11; the mask layer 121 includes a plurality of first annular trenches 30. The mask layer 121 may be silicon dioxide.
In a specific implementation, step 402 includes step a and step B.
In step a, as shown in fig. 6, a silicon dioxide layer 20 is formed on the upper surface of the epitaxial layer 11.
The silicon dioxide layer 20 may be formed on the upper surface of the epitaxial layer 11 by a vapor deposition or sputtering process.
In step B, as shown in fig. 7, a portion of the silicon dioxide layer 20 is removed to form a mask layer 121;
removing a portion of the silicon dioxide layer 20 by development to form a mask layer 121; the development includes an etching process.
In step 403, as shown in fig. 8, a portion of the epitaxial layer 11 is removed to form a plurality of second ring-shaped trenches 40.
The epitaxial layer 11 is dry etched to form a plurality of second ring-shaped trenches 40.
In step 404, as shown in fig. 9, a conductive layer 50 is formed on the upper surface of the epitaxial layer 11 and the upper surfaces of the plurality of second ring trenches 40. Conductive layer 50 may be polysilicon.
The conductive layer 50 may be formed on the upper surface of the epitaxial layer 11 and the upper surfaces of the plurality of second ring-shaped trenches 40 by a vapor deposition or sputtering process.
In step 405, as shown in fig. 10, the upper surface of the conductive layer 50 is removed and the conductive layer 50 on the side surfaces of the plurality of second annular trenches 40 remains to form the composite layer 60; the composite layer 60 has a plurality of third annular grooves 70.
The composite layer 60 includes silicon dioxide sidewall regions 80 and a mask layer 121.
Maskless etching the upper surface of the conductive layer 50 and remaining the conductive layer 50 on the side surfaces of the plurality of second annular trenches 40 to form a composite layer 60; the composite layer 60 has a plurality of third annular grooves 70.
In step 406, as shown in fig. 11, ion implantation is performed on the upper surface of the composite layer 60 to form the annular floating junction 14.
The composite layer 60 is used as a mask surface for ion implantation to form the P-type ring floating junction 14. The direction of the ion implantation is perpendicular to the lower surface of the third annular trench 70.
In step 407, as shown in fig. 12, the plurality of third annular trenches 70 are filled to form the dielectric ring 18, and the first dielectric layer 122 is formed on the upper surface of the composite layer 60.
The plurality of third annular trenches 70 may be filled by a vapor deposition or sputtering process to form the dielectric ring 18 and form the first dielectric layer 122 on the upper surface of the composite layer 60.
The mask layer 121 and the first dielectric layer 122 are made of the same material, and the mask layer 121 of the first dielectric layer 122 constitutes the dielectric layer 12.
In a specific implementation, step 407 is followed by step 408.
In step 408, a cell 19 is formed in a central region of the plurality of third annular trenches 70.
The embodiment of the invention adopts a structure of the floating ring, which comprises an epitaxial layer, a dielectric layer and a plurality of sub-floating rings nested layer by layer; the dielectric layer is arranged on the upper surface of the epitaxial layer; the sub floating ring comprises an annular floating junction, an annular groove, a first conducting ring, a second conducting ring and a dielectric ring; the annular floating junction is buried in the epitaxial layer; the annular groove is positioned on the upper surface of the annular floating junction; the first conducting ring is positioned on the inner side wall of the annular groove; the second conducting ring is positioned on the outer side wall of the annular groove; the dielectric ring is filled between the first conductive ring and the second conductive ring; because the annular floating junctions are embedded in the epitaxial layer, a plurality of embedded annular floating junctions nested layer by layer and the epitaxial layer form a plurality of super junction structures, and the super junction structures have deeper depth, so that the longitudinal electric field distribution is improved, and the longitudinal voltage resistance of the device is improved; meanwhile, as the dielectric ring is filled between the first conductive ring and the second conductive ring, a capacitor is formed between the first conductive ring and the second conductive ring, and the transverse voltage resistance of the device is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A floating ring structure, comprising:
the device comprises an epitaxial layer, a dielectric layer and a plurality of sub floating rings which are nested layer by layer; the dielectric layer is arranged on the upper surface of the epitaxial layer;
the sub-floating ring includes:
a ring-shaped floating junction buried in the epitaxial layer;
the annular groove is positioned on the upper surface of the annular floating junction;
the first conducting ring is positioned on the inner side wall of the annular groove;
the second conducting ring is positioned on the outer side wall of the annular groove;
a dielectric ring filled between the first conductive ring and the second conductive ring.
2. The structure of a floating ring of claim 1, wherein an upper surface of said recess is higher than an upper surface of said epitaxial layer and lower than an upper surface of said dielectric layer.
3. The structure of a floating ring according to claim 1, wherein the inner sidewall of the annular groove and the inner sidewall of the annular floating junction are located on the same curved surface, and the outer sidewall of the annular groove and the outer sidewall of the annular floating junction are located on the same curved surface.
4. The structure of the floating ring of claim 3, wherein the width of the outer sub-floating ring is smaller than the width of the inner sub-floating ring, the width of the sub-floating ring being the distance between the inner sidewall of the annular floating junction and the outer sidewall of the annular floating junction.
5. The structure of a floating ring in accordance with claim 1, wherein said first conductive ring and said second conductive ring are polysilicon, said dielectric layer and said dielectric ring are silicon dioxide, said floating junction is a P-type floating junction, and said epitaxial layer is an N-type epitaxial layer.
6. The structure of a floating ring in accordance with claim 1, further comprising a cell; the unit cell is located in a central region of the plurality of sub-floating rings.
7. A method of manufacturing a floating ring, the method comprising:
forming an epitaxial layer;
forming a mask layer on the upper surface of the epitaxial layer; the mask layer comprises a plurality of first annular grooves;
removing a part of the epitaxial layer to form a plurality of second annular grooves;
forming a conductive layer on the upper surface of the epitaxial layer and the upper surfaces of the plurality of second annular grooves;
removing an upper surface of the conductive layer and leaving the conductive layer of side surfaces of the plurality of second annular grooves to form a composite layer; the composite layer has a plurality of third annular grooves;
ion implantation is carried out on the upper surface of the composite layer to form an annular floating junction;
filling a plurality of the third annular grooves to form a dielectric ring, and forming a first dielectric layer on the upper surface of the composite layer;
the mask layer and the first dielectric layer are made of the same material, and the mask layer of the first dielectric layer and the mask layer form a dielectric layer together.
8. The method of manufacturing a floating ring according to claim 7, wherein said forming a mask layer on an upper surface of said epitaxial layer comprises:
forming a silicon dioxide layer on the upper surface of the epitaxial layer;
and removing part of the silicon dioxide layer to form the mask layer.
9. The method of manufacturing a floating ring according to claim 7, further comprising:
forming a cell in a central region of the plurality of third annular trenches.
10. An electronic device, characterized in that it comprises a structure of a floating ring according to any one of claims 1 to 6.
CN202211095172.2A 2022-09-08 2022-09-08 Structure and manufacturing method of floating ring and electronic equipment Withdrawn CN115188802A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227152A1 (en) * 2010-03-16 2011-09-22 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
CN104637990A (en) * 2013-11-21 2015-05-20 成都芯源系统有限公司 Field effect transistor, edge structure and related manufacturing method
CN108336152A (en) * 2018-03-20 2018-07-27 重庆大学 Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227152A1 (en) * 2010-03-16 2011-09-22 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
CN104637990A (en) * 2013-11-21 2015-05-20 成都芯源系统有限公司 Field effect transistor, edge structure and related manufacturing method
CN108336152A (en) * 2018-03-20 2018-07-27 重庆大学 Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method

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Application publication date: 20221014