CN115174865A - Video data transmission method, device and system - Google Patents

Abstract

The embodiment of the invention provides a method, a device and a system for transmitting video data, wherein the method comprises the following steps: receiving first video data from M first data interfaces of the N first data interfaces under the condition that the first processor is determined to be in an abnormal state; and transmitting the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state and is used for transmitting the first video data to the storage device. By the method and the device, the problem of video data loss in the related technology is solved, and the effect of completely storing the video data is achieved.

Description

Video data transmission method, device and system

Technical Field

The invention relates to the field of computers, in particular to a video data transmission method, device and system.

Background

Digital Video Recorder (DVR) devices have been developed along with multimedia technology, beginning in the end of the 20 th century, in the early 90 th century. DVR equipment is a computer system that integrates multiple functions of video acquisition, encoding compression, video storage, network transmission, and the like. However, with the high definition of DVR devices, the performance requirement for a Central Processing Unit (CPU) becomes higher and higher, and it is necessary to implement the high definition by cascading two CPUs. When one of the two CPUs fails, the DVR device cannot be started, and if the abnormal period of the DVR device is not found in time, the video in the abnormal period cannot be recorded, so that the video data is lost.

Disclosure of Invention

The embodiment of the invention provides a method, a device and a system for transmitting video data, which are used for at least solving the problem of video data loss in the related technology.

According to an embodiment of the present invention, there is provided a video data transmission method including: receiving first video data from M first data interfaces of N first data interfaces under the condition that a first processor is determined to be in an abnormal state, wherein the first data interfaces are used for transmitting the first video data to the first processor, the first processor is used for transmitting the first video data to a storage device, N is a natural number which is larger than 1, and M is a natural number which is smaller than or equal to N; and transmitting the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state, and the second processor is used for transmitting the first video data to the storage device.

According to still another embodiment of the present invention, there is also provided a video data transmission apparatus including: a first receiving module, configured to receive first video data from M first data interfaces of N first data interfaces when it is determined that a first processor is in an abnormal state, where the first data interfaces are configured to transmit the first video data to the first processor, the first processor is configured to transmit the first video data to a storage device, N is a natural number greater than 1, and M is a natural number less than or equal to N; and a first transmission module, configured to transmit the first video data to a second processor through M second data interfaces, where the second processor is a processor in a normal state, and the second processor is configured to transmit the first video data to the storage device.

In one exemplary embodiment, the apparatus determines that the first processor is in an exception state by: determining that the first processor is in an abnormal state when the communication between the first processor and the complex programmable logic device is abnormal; the first receiving module includes: a first determining unit, configured to determine a data interface in an open state from among the N first data interfaces, obtain M first data interfaces, and receive the first video data from the M first data interfaces.

In an exemplary embodiment, the first determining unit includes: and a first connection subunit, configured to determine, as the data interface in the on state, the first data interface in the data transmission state that is connected to the complex programmable logic device among the N first data interfaces, to obtain M first data interfaces, where connections between the complex programmable logic device and the M first data interfaces are set by the first processor.

In an exemplary embodiment, the apparatus further comprises: a first determining module, configured to determine, before transmitting the first video data to the second processor through M second data interfaces, a second data interface in a high impedance state among P second data interfaces included in the second processor, so as to obtain M second data interfaces, where the high impedance state of the M second data interfaces is set by the second processor, and other ones of the P second data channels except the M second data channels are used to transmit second video data to the second processor, and the second processor is further configured to transmit the second video data to the storage device, where P is a natural number greater than or equal to N; and the first connection module is used for establishing connection with the M second data interfaces.

In an exemplary embodiment, the apparatus further includes: the first sending module is used for sending a starting instruction to the switch equipment after the first video data are transmitted to the second processor through the M second data interfaces so as to control the switching equipment to be started; and a first indicating module, configured to instruct the switch device to send start information to the second processor when the switch device is in a start state, where the start information is used to instruct the second processor to transmit the first video data to the storage device.

According to still another embodiment of the present invention, there is also provided a video data transmission apparatus including: a second receiving module, configured to receive, when it is determined that a first processor is in an abnormal state, first video data from M second data interfaces of P second data interfaces, where the first video data is video data transmitted to the first processor by the M first data interfaces of the first processor, the first processor is configured to transmit the first video data to a storage device, P is a natural number greater than 1, and M is a natural number less than or equal to P; and the second transmission module is used for transmitting the first video data to the storage device.

In an exemplary embodiment, the apparatus further includes: the first setting module is used for setting the data transmission states of M second data interfaces to be in a high impedance state before the first processor is determined to be in an abnormal state and the first video data is received from M second data interfaces in the P second data interfaces.

In an exemplary embodiment, the second transmission module includes: the device comprises a first receiving unit, a second receiving unit and a control unit, wherein the first receiving unit is used for receiving starting information sent by the switch equipment, and the starting information is used for indicating that the switch equipment is in a starting state; and the first response unit is used for responding the starting information and transmitting the first video data to the storage device.

In an exemplary embodiment, the apparatus further comprises: a third receiving module, configured to receive second video data transmitted by other second data interfaces, where the other second data interfaces are data interfaces other than the M second data interfaces in the P second data interfaces; and the third transmission module is used for transmitting the second video data to the storage device.

According to still another embodiment of the present invention, there is also provided a transmission system of video data including: a complex programmable logic device, wherein the complex programmable logic device comprises the video data transmission device; the first processor and the second processor, wherein the second processor comprises the video data transmission device.

In an exemplary embodiment, the system further includes: k pieces of first data acquisition equipment which is connected with the first processor and is used for acquiring the first video data; each of the first data acquisition devices includes a first data interface, where the first data interface is configured to send the first video data to the first processor, or is configured to transmit the first video data to the complex programmable logic device when the first processor is in an abnormal state, the complex programmable logic device is configured to transmit the first video data to the second processor through M first data interfaces, and K is a natural number greater than or equal to 1.

In an exemplary embodiment, the system further includes: k second data acquisition devices connected with the second processor and used for acquiring second video data; each of the second data acquisition devices includes a second data interface, where the second data interface is configured to send the second video data to the second processor, or is configured to transmit the second video data to the complex programmable logic device when the second processor is in an abnormal state, and the complex programmable logic device is configured to transmit the second video data to the first processor through M second data interfaces, where K is a natural number greater than or equal to 1.

In an exemplary embodiment, the system further includes: a first integrated circuit bus for connecting the first processor and the complex programmable logic device and for determining the state of the first data interface when the first processor is in an abnormal state; and the second integrated circuit bus is used for connecting the second processor and the complex programmable logic device and determining the state of the second data interface under the condition that the second processor is in an abnormal state.

In an exemplary embodiment, the system further comprises: and the equipment bus is used for connecting the first processor and the second processor.

According to a further embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to, when executed, perform the steps of any of the method embodiments described above.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the invention, under the condition that the first processor is abnormal and cannot transmit the video data, the first video data are received from M first data interfaces in N first data interfaces, the first video data are transmitted to the second processor through M second data interfaces, and the first video data are transmitted to the storage device in time for storage through the second processor. And video data can not be lost due to the exception of the first processor. Therefore, the problem of video data loss in the related technology is solved, and the effect of completely storing the video data is achieved.

Drawings

FIG. 1 is a diagram illustrating a related art implementation of two cascaded CPUs for storing video data;

fig. 2 is a block diagram of a hardware configuration of a mobile terminal of an image processing method according to an embodiment of the present invention;

fig. 3 is a flowchart (one) of a transmission method of video data according to an embodiment of the present invention;

FIG. 4 is a schematic diagram (one) of the operation of the AD chip according to the embodiment of the invention;

FIG. 5 is a diagram of the operation of the AD chip according to the embodiment of the invention;

fig. 6 is a schematic diagram (iii) of the operation of the AD chip according to the embodiment of the present invention;

fig. 7 is a flowchart (two) of a transmission method of video data according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the normal operation of a master CPU and a slave CPU according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of the abnormal operation of a main CPU according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of the slave CPU operation according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of an abnormal operation of a slave CPU according to an embodiment of the present invention;

FIG. 12 is an implementation flow diagram according to a specific embodiment of the present invention;

fig. 13 is a block diagram (one) of the structure of a transmission apparatus of video data according to an embodiment of the present invention;

fig. 14 is a block diagram (ii) of the configuration of a transmission apparatus of video data according to an embodiment of the present invention;

fig. 15 is a block diagram of a structure of a transmission system of video data according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

First, a related art related to the present invention is explained:

the high definition of the video recording device requires two CPUs to cascade to implement the processing of the video data, for example, a video recording device supporting 16 channels of 1080p @30 frames (supporting 400 ten thousand @30 frames simultaneously) video access and supporting 16 channels of 1080p @30 frames (supporting 400 ten thousand @15 frames simultaneously) encoding capability needs to cascade through two CPUs, as shown in fig. 1, the video recording device is a schematic diagram for implementing the storage of the video data through two CPU cascades, and includes a main CPU and a slave CPU, the slave CPU transmits the acquired video data to the main CPU, and the main CPU transmits the video data acquired from the CPU and the video data acquired from the main CPU to a storage module for storage.

The method embodiments provided in the embodiments of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking the mobile terminal as an example, fig. 2 is a block diagram of a hardware structure of the mobile terminal of an image processing method according to an embodiment of the present invention. As shown in fig. 2, the mobile terminal may include one or more processors 202 (only one is shown in fig. 2) (the processor 202 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 204 for storing data, wherein the mobile terminal may further include a transmission device 206 for communication functions and an input-output device 208. It will be understood by those skilled in the art that the structure shown in fig. 2 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 2, or have a different configuration than shown in FIG. 2.

The memory 204 can be used for storing computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the image processing method in the embodiment of the present invention, and the processor 202 executes various functional applications and data processing by running the computer programs stored in the memory 204, namely, implementing the method described above. Memory 204 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 204 may further include memory located remotely from the processor 202, which may be connected to the mobile terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission means 206 is used for receiving or sending data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 206 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 206 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

Fig. 3 is a flowchart (one) of a method for transmitting video data according to an embodiment of the present invention, and as shown in fig. 3, the flowchart includes the following steps:

step S302, under the condition that the first processor is determined to be in an abnormal state, receiving first video data from M first data interfaces in N first data interfaces, wherein the first data interfaces are used for transmitting the first video data to the first processor, the first processor is used for transmitting the first video data to a storage device, N is a natural number larger than 1, and M is a natural number smaller than or equal to N;

step S304, the first video data is transmitted to a second processor through the M second data interfaces, where the second processor is a processor in a normal state, and the second processor is configured to transmit the first video data to the storage device.

In this embodiment, the first processor and the second processor may be processors that are active and standby each other. For example, the first processor is a master CPU, the second processor is a slave CPU, and the master CPU and the slave CPU may be connected by a Peripheral Component Interconnect Express (PCIE).

In this embodiment, the first data interface may be a View Object interface (VO) provided in the AD chip. The values of N and M may be flexibly set based on the actual reference scene or the performance of the AD chip, for example, two AD chips connected to the first processor include 8 VO interfaces. The second processor can be provided with the same number of AD chips and VO interfaces as the first processor, or can be provided with different numbers of AD chips and VO interfaces as the first processor.

In this embodiment, one AO chip includes 4 analog inputs and 4 digital BT656 outputs. In the case where the outputs of the analog input interface and the VO interface are one-to-one, the video source of 4-way 400m @30 frame or 4-way 800m @15 frame is accessible at the highest, as shown in fig. 4. The scene can be applied to the full opening of the VO interface in the AO chip arranged in the first processor and the second processor under the state that the first processor and the second processor are both in normal operation. When two analog channels are time division multiplexed, and output is performed through the same group of VO interfaces (for example, four VO interfaces included in an AD chip open two VO interfaces for video data transmission), a video source with 4 channels of 1080P is accessible at the highest level, as shown in fig. 5. This scenario may be applied to a case where the first processor or the second processor is operating abnormally, and the VO interface in the AO chip provided in the first processor and the second processor is half-open. When four analog channels are time division multiplexed and output through the same group of VO interfaces (for example, four VO interfaces included in the AD chip open one VO interface for video data transmission), the maximum 4 channels of 720P video sources can be accessed, as shown in fig. 6. The scene can be applied to the situation that one VO interface is opened in the AO chips arranged in the first processor and the second processor to transmit video data under the condition that the first processor or the second processor works abnormally.

The main body of the above steps may be a server, a specific processor provided in a terminal or a server, or a processor or a processing device provided independently from the terminal or the server, for example, a Complex Programmable Logic Device (CPLD), but is not limited thereto.

Through the steps, under the condition that the first processor is abnormal and cannot transmit the video data, the first video data are received from M first data interfaces in the N first data interfaces, the first video data are transmitted to the second processor through M second data interfaces, and the first video data are transmitted to the storage device in time through the second processor for storage. The video data can not be lost due to the exception of the first processor. Therefore, the problem of video data loss in the related technology is solved, and the effect of completely storing the video data is achieved.

In one exemplary embodiment, determining that the first processor is in the exception state includes: determining that the first processor is in an abnormal state under the condition that the communication between the first processor and the complex programmable logic device is abnormal;

in this embodiment, a Complex Programmable Logic Device (CPLD) is connected to the first processor through an Inter-Integrated Circuit (IIC). And when the first processor fails, the IIC interface transmits the failure information of the first processor to the CPLD, and the CPLD learns that the first processor fails from the failure information.

In an exemplary embodiment, receiving the first video data from M first data interfaces of the N first data interfaces includes determining data interfaces in an on state of the N first data interfaces, obtaining the M first data interfaces, and receiving the first video data from the M first data interfaces.

In this embodiment, when M and N are equal, N first data interfaces in the AD chip connected to the first processor are fully opened, and the transmitted video resolution is maximum, for example, as shown in fig. 4, 4 data channels in the analog input interface are in one-to-one correspondence with outputs of 4 VO interfaces, and video data of 4 channels 400m @30 frames or 4 channels 800m @15 frames can be transmitted. It should be noted that, when the VO interface in the first processor is fully open, the second processor needs to correspondingly open N second data interfaces to receive the video data transmitted by the N first data interfaces, and the second processor needs to set P second data interfaces greater than N to transmit the video data in the second processor by using the remaining second data interfaces, so as to achieve the purpose of ensuring the continuity of the video data without reducing the video resolution in the first processor. When M is smaller than N, N first data interfaces in the AD chip connected to the first processor open a portion, for example, as shown in fig. 5, 2 VO interfaces are opened to access 4 channels of 1080P video source. The second processor needs to set N second data interfaces to receive the video data transmitted by the N first data interfaces, and transmit the video data in the second processor by using the remaining second data interfaces. Therefore, the purpose of ensuring the continuity of video data transmission in a mode of reducing the video resolution can be realized.

In an exemplary embodiment, determining the data interface in the on state from among the N first data interfaces to obtain M first data interfaces includes:

s1, connecting the complex programmable logic device in the N first data interfaces, determining the first data interface in a data transmission state as a data interface in an open state, and obtaining M first data interfaces, wherein the connection between the complex programmable logic device and the M first data interfaces is set by a first processor.

In this embodiment, when both the first processor and the second processor are in a normal state, the number of first data interfaces that need to be turned on in the first processor and the number of second data interfaces that need to be turned on in the second processor are negotiated through the PCIE interface when the first processor fails. Or, negotiating the number of the second data interfaces to be opened and the number of the first data interfaces to be opened when the second processor fails through the PCIE interface.

In one exemplary embodiment, before transmitting the first video data to the second processor through the M second data interfaces, the method further comprises:

s1, determining a second data interface in a high impedance state in P second data interfaces included in a second processor to obtain M second data interfaces, wherein the high impedance state of the M second data interfaces is set by the second processor, other second data channels except the M second data channels in the P second data channels are used for transmitting second video data to the second processor, the second processor is also used for transmitting the second video data to a storage device, and P is a natural number which is greater than or equal to N;

and S2, establishing connection with the M second data interfaces.

In this embodiment, P may be greater than N, or less than or equal to N. For example, when P is larger than N, the purpose of ensuring continuity of video data without reducing the video resolution in the first processor can be achieved. When P is less than or equal to N, the purpose of ensuring the continuity of video data transmission by reducing the video resolution can be realized. In addition, after the M second data interfaces are set to the high impedance state, the M second data interfaces do not transmit the second video data transmitted by the data channel in the AD chip in the second processor any more, but receive the first video data transmitted by the CPLD, thereby realizing that the second processor takes over the video data of the first processor.

In one exemplary embodiment, after transmitting the first video data to the second processor through the M second data interfaces, the method further comprises:

s1, sending a starting instruction to a switch device to control the switching device to be started;

and S2, under the condition that the switch device is in the on state, indicating the switch device to send on information to the second processor, wherein the on information is used for indicating the second processor to transmit the first video data to the storage device.

In this embodiment, the CPLD and the storage device are connected through the switch device, and after receiving the first video data from the M first data interfaces, the CPLD sends a turn-on instruction to the switch device to control the turn-on of the switch device. The first processor and the second processor are both connected with the storage device through the switching device, and the first processor and the second processor are allowed to transmit video data to the storage device under the condition that the switching device is turned on. Thereby realizing enhanced control over the transmission of video data by the first processor and the second processor.

In this embodiment, a method for transmitting video data is provided, and fig. 7 is a flowchart (ii) of a method for transmitting video data according to an embodiment of the present invention, where as shown in fig. 7, the flowchart includes the following steps:

step S702, under the condition that a first processor is determined to be in an abnormal state, receiving first video data from M second data interfaces in P second data interfaces, wherein the first video data is video data transmitted to the first processor by the M first data interfaces in the first processor, the first processor is used for transmitting the first video data to a storage device, P is a natural number greater than 1, and M is a natural number less than or equal to P;

step S704, transmitting the first video data to the storage device.

The main body of the above steps may be a specific processor provided in the server, or a processor or a processing device provided relatively independently from the terminal or the server, for example, but not limited to, the second processor in this embodiment.

Through the steps, under the condition that the video data cannot be transmitted due to the abnormality of the first processor, the first video data are received from M first data interfaces in the N first data interfaces, the first video data are transmitted to the second processor through M second data interfaces, the first video data are transmitted to the storage device for storage through the second processor in time, and the video data cannot be lost due to the abnormality of the first processor. Therefore, the problem of video data loss in the related art is solved, and the effect of completely storing the video data is achieved.

In one exemplary embodiment, in the case where it is determined that the first processor is in the abnormal state, the method further includes:

s1, before receiving first video data from M second data interfaces in the P second data interfaces, setting the data transmission states of the M second data interfaces to be high-impedance states.

In one exemplary embodiment, transmitting the first video data to a storage device comprises:

the method comprises the steps of S1, receiving opening information sent by switch equipment, wherein the opening information is used for indicating that the switch equipment is in an opening state;

and S2, responding to the starting information, and transmitting the first video data to the storage device.

In one exemplary embodiment, the method further comprises:

s1, receiving second video data transmitted by other second data interfaces, wherein the other second data interfaces are data interfaces except M second data interfaces in the P second data interfaces;

and S2, transmitting the second video data to the storage device.

In this embodiment, when P is greater than N, M second data interfaces of the P second data interfaces may be set to a high impedance state to transmit the first video data. The purpose of ensuring the continuity of the video data without degrading the video resolution in the first processor and the video resolution in the second processor can be achieved. When P is less than or equal to N, M second data interfaces of the P second data interfaces may be set to a high impedance state to transmit the first video data, and the purpose of ensuring continuity of video data transmission by reducing the video resolution in the first processor and the video resolution in the second processor may be achieved. In addition, after the M second data interfaces are set to the high impedance state, the M second data interfaces do not transmit the second video data transmitted by the data channel in the AD chip in the second processor, but receive the first video data transmitted by the CPLD, so that the second processor takes over the video data of the first processor.

It is to be understood that the above-described embodiments are only a few, and not all, embodiments of the present invention.

The present invention will be described in detail with reference to the following examples:

in this embodiment, a master CPU and a slave CPU are taken as an example for explanation, and when one of the CPUs fails, the other CPU takes over all services of video access and video storage to ensure continuity of video services.

In the present embodiment, the master CPU and the slave CPU both acquire video data through the AD chip, that is, coaxially communicate through the AD chip. Coaxial communication is used to indicate that control signals are transmitted on a coaxial line, and that both video and 485 signals are transmitted on the coaxial line. Coaxial communication is used to enable data communication between a back end device DVR and a front end device Camera, and supports forward communication, which is Camera to DVR, and reverse communication, which is DVR to Camera.

According to the embodiment, under the cooperative work of the dual CPUs according to the AD video access characteristic and the coaxial anti-control characteristic, when one of the CPUs works abnormally, the scheme that the other CPU takes over all core services is realized by reducing the video access resolution. Mainly comprises the following embodiments:

example 1: when the master CPU and the slave CPU are normally operated, the access and storage path of the video data is as shown in fig. 8, and the bold path indicates the transmission path of the video data. At this time, the video maximum access capability and the encoding capability are maintained as the external declaration capability, for example, 16-way 400M @30 video access and 16-way 1080P encoding storage access. In this case, 4 sets of VO interfaces corresponding to the 4 AD chips are all set to output, and 8 sets of digital signals connected to the CPLD are all set to input states.

Example 2: when the master CPU works abnormally and the slave CPU works normally, the video access and storage path is as shown in fig. 9, and the bold path indicates the transmission path of the video data. At this time, the maximum access capability and the coding capability of the video are maintained to be reduced to half of the declared capability, for example, 16-way 1080@30 video access and 8-way 1080P coding storage access are adopted; in this case, the VO3 interface and the VO4 interface of the AD chip under the CPU are synchronously set to an input high impedance state, and the remaining VO interfaces maintain the original output states. The 8 sets of signals of the CPLD have 4 sets connected to the master CPU as inputs and 4 sets connected to the slave CPU as outputs. In this embodiment, the reason why the VO3 interface and the VO4 interface of the AD chip suspended from the CPU are synchronously set to the input high impedance state is described as follows: as shown in fig. 10, the trend of the bold path is that the CPLD outputs to the slave CPU, the AD chip outputs to the slave CPU, and if the state of the VO interface in the AD chip is not set, the VO interfaces are all output to the slave CPU, and a signal will be shelved. In this case, the AD chip is already in the time division multiplexing mode of switching from 4-way output to 2-way output, and the corresponding V03 interface and V04 interface are set to input high impedance, so that the output signal of the CPLD is not affected. Therefore, the normal collection of video data by the AD chip under the main CPU can be realized, and the slave CPU reserves and stores the video data collected by the AD chip under the main CPU as intact as possible.

Example 3: when the slave CPU works abnormally and the master CPU works normally, the video access and storage path is as shown in FIG. 11, the bold path represents the transmission path of the video data, and the maximum access capability and the encoding capability of the video data are maintained to be reduced to half of the declared capability at the moment. For example, 16-way 1080@30 video access, 8-way 1080P encoded storage access; in this case, the VO3 interface and the VO4 interface of the AD chip under the master CPU are synchronously set to an input high impedance state, the remaining VO interfaces maintain the original output state, and 4 sets of signals of 8 sets of the CPLD connected to the master CPU are set as outputs and 4 sets of signals connected to the slave CPU are set as inputs. Therefore, the video data can be normally collected by the AD chip under the slave CPU, and the video data collected by the AD chip under the slave CPU is reserved and stored as intact as possible by the master CPU.

As shown in fig. 12, it is an implementation flowchart in this embodiment, and includes the following steps:

s1201, the device starts to operate according to state 1, where state 1 is used to indicate that the master CPU and the slave CPU in embodiment 1 are both in a normal operation state;

s1202, judging whether the CPLD is normally communicated with the master CPU and the slave CPU and judging whether the normal communication between the master CPU and the slave CPU is normal;

s1203, the CPLD is normally communicated with the master CPU and the slave CPU, and the master CPU and the slave CPU are normally communicated with each other, so that the state 1 is kept to operate;

s1204, judge CPLD and slave CPU communicate unusually;

s1205, under the condition that the communication between the CPLD and the slave CPU is normal, judging whether the communication between the CPLD and the master CPU is abnormal;

s1206, when the CPLD is in communication abnormality with the master CPU, switching to state 2 to operate, and triggering an alarm, where state 2 is used to indicate a state where the master CPU is abnormal and the slave CPU is normal in embodiment 2;

s1207, judging whether the current video access exceeds 1080P resolution;

s1208, switching the camera resolution to 1080P for the channel reverse 485 exceeding the resolution;

s1209, keeping the configuration unchanged;

s1210, judging whether the communication between the CPLD and the main CPU is abnormal;

s1211, keeping the default state 1 to operate, and triggering an alarm;

s1212, switching to the running state 3, and triggering an alarm, where the state 3 is used to indicate a state where the slave CPU is abnormal and the master CPU is normal in embodiment 3;

s1213, judging whether the current video access has a resolution of over 1080P;

s1214, reversing 485 and switching the resolution of the camera to 1080P for the channel with the resolution exceeding;

s1215, the configuration is kept unchanged.

In summary, in this embodiment, when one of the CPUs fails, the other CPU takes over all the video access and video storage core services, and outputs an alarm to prompt the failure, thereby enhancing the reliability of the device.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

In this embodiment, a video data transmission apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and details of which have been already described are not repeated. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 13 is a block diagram (one) of a configuration of a transmission apparatus of video data according to an embodiment of the present invention, as shown in fig. 13, the apparatus including:

a first receiving module 1302, configured to receive first video data from M first data interfaces of N first data interfaces, where the first data interfaces are used to transmit the first video data to a first processor, and the first processor is used to transmit the first video data to a storage device, where N is a natural number greater than 1, and M is a natural number less than or equal to N, if it is determined that the first processor is in an abnormal state;

a first transmission module 1304, configured to transmit the first video data to a second processor through M second data interfaces, where the second processor is a processor in a normal state, and the second processor is configured to transmit the first video data to the storage device.

In an exemplary embodiment, the apparatus determines that the first processor is in an abnormal state by: determining that the first processor is in an abnormal state when the communication between the first processor and the complex programmable logic device is abnormal;

the first receiving module includes:

a first determining unit, configured to determine a data interface in an open state from among the N first data interfaces, obtain M first data interfaces, and receive the first video data from the M first data interfaces.

In an exemplary embodiment, the first determining unit includes:

and a first connection subunit, configured to determine, as a data interface in the on state, a first data interface in the N first data interfaces that is connected to the complex programmable logic device and is in a data transmission state, to obtain M first data interfaces, where connections between the complex programmable logic device and the M first data interfaces are set by the first processor.

In an exemplary embodiment, the apparatus further includes:

a first determining module, configured to determine, before transmitting the first video data to the second processor through M second data interfaces, a second data interface in a high impedance state among P second data interfaces included in the second processor, so as to obtain M second data interfaces, where the high impedance state of the M second data interfaces is set by the second processor, and other ones of the P second data channels except the M second data channels are used to transmit second video data to the second processor, and the second processor is further configured to transmit the second video data to the storage device, where P is a natural number greater than or equal to N;

and the first connection module is used for establishing connection with the M second data interfaces.

In an exemplary embodiment, the apparatus further includes:

the first sending module is used for sending a starting instruction to the switch equipment after the first video data are transmitted to the second processor through the M second data interfaces so as to control the switching equipment to be started;

the first indication module is configured to indicate the switch device to send start information to the second processor when the switch device is in a start state, where the start information is used to indicate the second processor to transmit the first video data to the storage device.

Fig. 14 is a block diagram of a configuration of a video data transmission apparatus according to an embodiment of the present invention (ii), and as shown in fig. 14, the apparatus includes:

a second receiving module 1402, configured to receive, if it is determined that a first processor is in an abnormal state, first video data from M second data interfaces of P second data interfaces, where the first video data is video data transmitted to the first processor by the M first data interfaces of the first processor, the first processor is configured to transmit the first video data to a storage device, P is a natural number greater than 1, and M is a natural number less than or equal to P;

a second transmission module 1404, configured to transmit the first video data to the storage device.

In an exemplary embodiment, the apparatus further comprises: the first setting module is used for setting the data transmission states of M second data interfaces to be in a high impedance state before receiving the first video data from M second data interfaces in the P second data interfaces under the condition that the first processor is determined to be in an abnormal state.

In an exemplary embodiment, the second transmission module includes:

the device comprises a first receiving unit, a second receiving unit and a control unit, wherein the first receiving unit is used for receiving starting information sent by the switch equipment, and the starting information is used for indicating that the switch equipment is in a starting state;

and a first response unit, configured to transmit the first video data to the storage device in response to the start information.

In an exemplary embodiment, the apparatus further comprises:

a third receiving module, configured to receive second video data transmitted by other second data interfaces, where the other second data interfaces are data interfaces other than M second data interfaces in the P second data interfaces;

and the third transmission module is used for transmitting the second video data to the storage device.

Fig. 15 is a block diagram of a configuration of a transmission system of video data according to an embodiment of the present invention, as shown in fig. 15, the system including:

a complex programmable logic device 1502, wherein the complex programmable logic device includes the transmission means of video data in fig. 13;

the first processor 1504 is provided with a first processor,

a second processor 1506, wherein the second processor includes a transmission device of video data in fig. 14.

In an exemplary embodiment, the system further comprises:

k pieces of first data acquisition equipment which is connected with the first processor and is used for acquiring the first video data;

each of the first data acquisition devices includes a first data interface, where the first data interface is configured to send the first video data to the first processor, or is configured to transmit the first video data to the complex programmable logic device when the first processor is in an abnormal state, the complex programmable logic device is configured to transmit the first video data to the second processor through M first data interfaces, and K is a natural number greater than or equal to 1.

In an exemplary embodiment, the system further comprises:

k second data acquisition devices connected with the second processor and used for acquiring second video data;

each of the second data acquisition devices includes a second data interface, where the second data interface is configured to send the second video data to the second processor, or is configured to transmit the second video data to the complex programmable logic device when the second processor is in an abnormal state, and the complex programmable logic device is configured to transmit the second video data to the first processor through M second data interfaces, where K is a natural number greater than or equal to 1.

In an exemplary embodiment, the system further comprises:

a first integrated circuit bus for connecting the first processor and the complex programmable logic device and for determining the state of the first data interface when the first processor is in an abnormal state;

and the second integrated circuit bus is used for connecting the second processor and the complex programmable logic device and determining the state of the second data interface under the condition that the second processor is in an abnormal state.

In an exemplary embodiment, the system further includes:

and the equipment bus is used for connecting the first processor and the second processor.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are located in different processors in any combination.

Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.

In an exemplary embodiment, the computer readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented in a general purpose computing device, they may be centralized in a single computing device or distributed across a network of multiple computing devices, and they may be implemented in program code that is executable by a computing device, such that they may be stored in a memory device and executed by a computing device, and in some cases, the steps shown or described may be executed in an order different from that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps therein may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A method for transmitting video data, comprising:

receiving first video data from M first data interfaces of N first data interfaces under the condition that a first processor is determined to be in an abnormal state, wherein the first data interfaces are used for transmitting the first video data to the first processor, the first processor is used for transmitting the first video data to a storage device, N is a natural number larger than 1, and M is a natural number smaller than or equal to N;

and transmitting the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state and is used for transmitting the first video data to the storage device.

2. The method of claim 1,

determining that the first processor is in an exception state comprises: determining that the first processor is in an abnormal state under the condition that the communication between the first processor and the complex programmable logic device is abnormal;

the method comprises the steps of receiving first video data from M first data interfaces in N first data interfaces, determining the data interfaces in an open state in the N first data interfaces to obtain the M first data interfaces, and receiving the first video data from the M first data interfaces.

3. The method of claim 2, wherein determining the data interface in an on state from among the N first data interfaces to obtain M first data interfaces comprises:

and determining the first data interface in the data transmission state as the data interface in the starting state in the N first data interfaces connected with the complex programmable logic device to obtain M first data interfaces, wherein the connection between the complex programmable logic device and the M first data interfaces is set by the first processor.

4. The method of claim 1, wherein prior to transmitting the first video data to the second processor over the M second data interfaces, the method further comprises:

determining a second data interface in a high impedance state among P second data interfaces included in the second processor to obtain M second data interfaces, wherein the high impedance state of the M second data interfaces is set by the second processor, other second data channels except the M second data channels among the P second data channels are used for transmitting second video data to the second processor, the second processor is further used for transmitting the second video data to the storage device, and P is a natural number greater than or equal to N;

and establishing connection with the M second data interfaces.

5. The method of claim 1, wherein after transmitting the first video data to the second processor over the M second data interfaces, the method further comprises:

sending a starting instruction to the switching equipment to control the switching equipment to be started;

and under the condition that the switching device is in an on state, instructing the switching device to send on information to the second processor, wherein the on information is used for instructing the second processor to transmit the first video data to the storage device.

6. A method for transmitting video data, comprising:

receiving first video data from M second data interfaces of P second data interfaces under the condition that the first processor is determined to be in an abnormal state, wherein the first video data are video data transmitted to the first processor by the M first data interfaces of the first processor, the first processor is used for transmitting the first video data to a storage device, P is a natural number which is greater than 1, and M is a natural number which is less than or equal to P;

transmitting the first video data to the storage device.

7. The method of claim 6, wherein in the event that the first processor is determined to be in an exception state, the method further comprises:

before receiving first video data from M second data interfaces in the P second data interfaces, setting the data transmission states of the M second data interfaces to be high impedance states.

8. The method of claim 6, wherein transferring the first video data to a storage device comprises:

receiving opening information sent by a switch device, wherein the opening information is used for indicating that the switch device is in an opening state;

and responding to the starting information, and transmitting the first video data to the storage device.

9. The method of claim 6, further comprising:

receiving second video data transmitted by other second data interfaces, wherein the other second data interfaces are data interfaces other than the M second data interfaces in the P second data interfaces;

transmitting the second video data to the storage device.

10. A transmission apparatus of video data, comprising:

a first receiving module, configured to receive first video data from M first data interfaces of N first data interfaces when it is determined that a first processor is in an abnormal state, where the first data interfaces are used to transmit the first video data to the first processor, the first processor is used to transmit the first video data to a storage device, N is a natural number greater than 1, and M is a natural number less than or equal to N;

and the first transmission module is used for transmitting the first video data to a second processor through M second data interfaces, wherein the second processor is a processor in a normal state, and the second processor is used for transmitting the first video data to the storage device.

11. A transmission apparatus of video data, comprising:

a second receiving module, configured to receive, if it is determined that a first processor is in an abnormal state, first video data from M second data interfaces of P second data interfaces, where the first video data is video data transmitted to the first processor by the M first data interfaces of the first processor, the first processor is configured to transmit the first video data to a storage device, P is a natural number greater than 1, and M is a natural number less than or equal to P;

and the second transmission module is used for transmitting the first video data to the storage equipment.

12. A system for transmitting video data, comprising:

a complex programmable logic device, wherein the complex programmable logic device comprises the video data transmission apparatus of claim 10;

a first processor for processing the received data, and a second processor for processing the received data,

a second processor, wherein said second processor comprises a transmission device of video data as claimed in claim 11.

13. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5, or which, when being executed by a processor, carries out the steps of the method of any one of claims 6 to 9.

14. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any of claims 1 to 5 when executing the computer program or the steps of the method of any of claims 6 to 9 when executing the computer program.

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