CN115174327A - Signal demodulation method and device based on united one and two bit difference Viterbi - Google Patents

Signal demodulation method and device based on united one and two bit difference Viterbi Download PDF

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CN115174327A
CN115174327A CN202211060950.4A CN202211060950A CN115174327A CN 115174327 A CN115174327 A CN 115174327A CN 202211060950 A CN202211060950 A CN 202211060950A CN 115174327 A CN115174327 A CN 115174327A
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demodulation
bit
viterbi
module
ais
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易中立
王福斋
朱亚辉
张杨
王姗姗
吴益斌
王玮畅
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Transport Planning And Research Institute Ministry Of Transport
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

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Abstract

The invention discloses a signal demodulation method and device based on a united one-bit difference Viterbi and a two-bit difference Viterbi. The method comprises the steps of receiving an AIS signal and processing the AIS signal into two paths; performing one-bit differential Viterbi demodulation and two-bit differential Viterbi demodulation on the two paths of AIS signals respectively, and performing AIS data unpacking processing on the demodulated signals respectively; and performing CRC check on the two paths of unpacked data respectively, preferentially outputting the two-bit differential Viterbi demodulated and unpacked data when the two-bit differential Viterbi demodulated and unpacked data is correct, and outputting the one-bit differential Viterbi demodulated and unpacked data if the one-bit differential Viterbi demodulated and unpacked data is correct when the two-bit differential Viterbi demodulated and unpacked data is incorrect, otherwise, not outputting the one-bit differential Viterbi demodulated and unpacked data. The invention can improve the low signal-to-noise ratio and the high-frequency lower receiving sensitivity of the AIS system.

Description

Signal demodulation method and device based on united one and two bit difference Viterbi
Technical Field
The invention relates to the technical field of AIS signal demodulation methods, in particular to a signal demodulation method and device based on a united-in-one and two-bit differential Viterbi.
Background
The AIS (Automatic Identification System) is a System that is based on global satellite positioning System information and can provide relevant information for shore stations and ship stations to track and monitor marine vessels. The system works in VHF (very high frequency) maritime frequency bands (161.975 MHz and 162.025 MHz), and can send static information, dynamic information, voyage information and the like of a ship, wherein the static information comprises an MMSI (Mobile multimedia subscriber identity) number, a call sign, a ship name, ship length and width information, ship types and the like of the ship; the dynamic information comprises the current navigation position, navigation speed, course and the like of the ship; the voyage information comprises the draft, the cargo type, the destination port and the like of the voyage.
The AIS system uses GMSK modulation mode, because the design of the system is early and the design of the system does not consider channel coding at the beginning, the receiving performance of the whole system completely depends on GMSK demodulator, which results in that the low signal-to-noise ratio and the receiving sensitivity under high frequency offset of the AIS system can not be improved.
Disclosure of Invention
The invention aims to provide a signal demodulation method based on a united one-bit difference Viterbi and a two-bit difference Viterbi aiming at the defects of the prior art.
To achieve the above object, in a first aspect, the present invention provides a method and apparatus for demodulating a signal based on a joint one-bit difference viterbi, including:
receiving an AIS signal and processing the AIS signal into two paths;
performing one-bit differential Viterbi demodulation and two-bit differential Viterbi demodulation on the two paths of AIS signals respectively, and performing AIS data unpacking processing on the demodulated signals respectively;
and respectively performing CRC (cyclic redundancy check) on the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing and the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing to judge whether the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing is correct or not, if so, outputting the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing as a demodulation signal, otherwise, continuously judging whether the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing is correct or not, and if so, outputting the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing as a demodulation signal, otherwise, not outputting the data.
Further, the manner of the one-bit differential viterbi demodulation and the two-bit differential viterbi demodulation is as follows:
calculation Start and initialization
Figure DEST_PATH_IMAGE001
Is 0;
calculating phase information for each received AIS signal;
calculating an actual phase difference for a symbol time interval based on the phase information
Figure 298243DEST_PATH_IMAGE001
Comprises the following steps:
Figure DEST_PATH_IMAGE003
wherein,
Figure 844631DEST_PATH_IMAGE004
for the nth symbol period of the AIS signal
Figure DEST_PATH_IMAGE005
The phase of (a) is determined,
Figure 500740DEST_PATH_IMAGE006
is AIS signal No
Figure DEST_PATH_IMAGE007
One symbol period
Figure 502719DEST_PATH_IMAGE005
N is a natural number greater than 1;
obtaining theoretical phase differences of 8 states according to a pre-made one-bit difference Viterbi code element state table
Figure 738528DEST_PATH_IMAGE008
；
According to the actual phase difference
Figure 77106DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 107379DEST_PATH_IMAGE008
Calculating a one-bit path metric value
Figure DEST_PATH_IMAGE009
Comprises the following steps:
Figure DEST_PATH_IMAGE011
selecting a one bit path metric value
Figure 656040DEST_PATH_IMAGE009
The smallest path is taken as a survivor path and is backtracked and demodulated to obtain a bit differential Viterbi demodulation bit stream;
obtaining theoretical phase difference of 16 states according to a pre-made two-bit difference Viterbi code element state table
Figure 164382DEST_PATH_IMAGE012
；
According to the actual phase difference
Figure 637694DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 838868DEST_PATH_IMAGE012
Calculating two-bit path metric values
Figure DEST_PATH_IMAGE013
Comprises the following steps:
Figure DEST_PATH_IMAGE015
selecting a two-bit path metric value
Figure 343668DEST_PATH_IMAGE013
The smallest as a survivor path and back-demodulating to obtain a two-bit differential viterbi demodulated bit stream.
Further, the depth of the retrospective demodulation is 10 bits.
In a second aspect, the present invention provides a joint one, two bit differential viterbi-based signal demodulation apparatus comprising:
the receiving module is used for receiving the AIS signals and processing the AIS signals into two paths;
the first demodulation module is used for carrying out one-bit differential Viterbi demodulation on one path of AIS signals;
the second demodulation module is used for carrying out two-bit differential Viterbi demodulation on the other path of AIS signals;
the first unpacking module is used for carrying out AIS data unpacking processing on the signal demodulated by the first demodulation module;
the second unpacking module is used for carrying out AIS data unpacking processing on the signal demodulated by the second demodulation module;
the first CRC check module is used for performing CRC check on the data subjected to unpacking processing by the first unpacking module so as to judge whether the data subjected to unpacking processing by the first unpacking module is correct or not;
the second CRC check module is used for performing CRC check on the data subjected to unpacking processing by the second unpacking module so as to judge whether the data subjected to unpacking processing by the second unpacking module is correct or not;
and the demodulation combination output module is used for outputting the data unpacked by the second unpacking module as a demodulation signal when the data unpacked by the second unpacking module is correct, and outputting the data unpacked by the first unpacking module as a demodulation signal if the data unpacked by the first unpacking module is incorrect when the data unpacked by the second unpacking module is incorrect, otherwise, not outputting the data.
Further, the manner of the one-bit differential viterbi demodulation and the two-bit differential viterbi demodulation is as follows:
calculation Start and initialization
Figure 921279DEST_PATH_IMAGE001
Is 0;
calculating phase information for each received AIS signal;
calculating an actual phase difference for a symbol time interval based on the phase information
Figure 968870DEST_PATH_IMAGE001
Comprises the following steps:
Figure 343875DEST_PATH_IMAGE003
wherein,
Figure 211337DEST_PATH_IMAGE004
for the nth symbol period of the AIS signal
Figure 327060DEST_PATH_IMAGE005
The phase of (a) is determined,
Figure 229157DEST_PATH_IMAGE006
is AIS signal No
Figure 37713DEST_PATH_IMAGE007
One symbol period
Figure 658051DEST_PATH_IMAGE005
The phase of (a);
theory for obtaining 8 states according to a prefabricated one-bit difference Viterbi code element state tablePhase difference
Figure 311886DEST_PATH_IMAGE008
；
According to the actual phase difference
Figure 334068DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 50876DEST_PATH_IMAGE008
Calculating a one-bit path metric value
Figure 892930DEST_PATH_IMAGE009
Comprises the following steps:
Figure 84877DEST_PATH_IMAGE011
selecting a one bit path metric value
Figure 961566DEST_PATH_IMAGE009
The smallest path is taken as a survivor path and backtracking demodulation is carried out to obtain a bit difference Viterbi demodulation bit stream;
obtaining theoretical phase difference of 16 states according to a pre-made two-bit difference Viterbi code element state table
Figure 846346DEST_PATH_IMAGE012
；
According to the actual phase difference
Figure 175696DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 436913DEST_PATH_IMAGE012
Calculating two-bit path metric values
Figure 168109DEST_PATH_IMAGE013
Comprises the following steps:
Figure 958210DEST_PATH_IMAGE015
selecting a two-bit path metric value
Figure 43365DEST_PATH_IMAGE013
The smallest one is taken as a survivor path and demodulated back to obtain a two-bit differential viterbi demodulated bit stream.
Further, the depth of the retrospective demodulation is 10 bits.
Has the beneficial effects that: the invention solves the problem that the low signal-to-noise ratio and the high-frequency offset receiving sensitivity of the AIS system can not be improved by jointly using the one-bit difference Viterbi and the two-bit difference Viterbi demodulation method, can ensure that the system can reach the system Packet Error Rate (PER) less than 20 percent under the base band signal-to-noise ratio of 5dB, can reach the system packet error rate less than 0.1 percent under the base band signal-to-noise ratio of 10dB, and can bring the performance improvement of more than 2 dB.
Drawings
FIG. 1 is a flow chart diagram of a method for demodulating a signal based on a combined one-bit and two-bit differential Viterbi;
FIG. 2 is a schematic flow diagram of demodulating a combined output signal;
FIG. 3 is a schematic block diagram of a joint one, two bit differential Viterbi based signal demodulation apparatus;
fig. 4 is a simulation graph of packet error rate as a function of the signal-to-noise ratio of the received signal.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a signal demodulation method based on a combined one-bit difference viterbi and a two-bit difference viterbi, including:
and receiving the AIS signals and processing the received AIS signals into two paths. The AIS signal processing of the receiving type and the digital type is two paths, which are prior art and are not described herein again.
And respectively carrying out one-bit differential Viterbi demodulation and two-bit differential Viterbi demodulation on the received AIS signals, and respectively carrying out AIS data unpacking processing on the demodulated signals. Specifically, the manner of the one-bit differential viterbi demodulation and the two-bit differential viterbi demodulation is as follows:
calculation Start and initialization
Figure 108273DEST_PATH_IMAGE001
Is 0.
The phase information is calculated for each received AIS signal.
Calculating an actual phase difference for a symbol time interval from the phase information
Figure 959555DEST_PATH_IMAGE001
Comprises the following steps:
Figure 451716DEST_PATH_IMAGE016
wherein,
Figure 755658DEST_PATH_IMAGE004
for the nth symbol period of the AIS signal
Figure 358678DEST_PATH_IMAGE005
The phase of (a) is determined,
Figure 798886DEST_PATH_IMAGE006
is AIS signal No
Figure 453160DEST_PATH_IMAGE007
One symbol period
Figure 978819DEST_PATH_IMAGE005
N is a natural number greater than 1.
Obtaining theoretical phase differences of 8 states according to a pre-made one-bit difference Viterbi code element state table
Figure 385530DEST_PATH_IMAGE008
. In particular, a one-bit differential Viterbi symbol state table may be usedSee table 1:
Figure DEST_PATH_IMAGE017
TABLE 1
The one-bit differential viterbi symbol state table is derived and calculated according to the following formula:
Figure DEST_PATH_IMAGE019
the above formula is derived from GMSK modulation characteristics, wherein,
Figure 70458DEST_PATH_IMAGE020
in the form of a circumferential ratio,
Figure DEST_PATH_IMAGE021
for the (n-3) th symbol,
Figure 500827DEST_PATH_IMAGE022
for the (n-2) th symbol,
Figure DEST_PATH_IMAGE023
is the (n-1) th code element, the value of the code element is 1 or-1,
Figure 576099DEST_PATH_IMAGE024
is the modulation waveform parameter of GMSK.
According to the actual phase difference
Figure 786500DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 201301DEST_PATH_IMAGE008
Calculating a one-bit path metric value
Figure 206166DEST_PATH_IMAGE009
Comprises the following steps:
Figure 706418DEST_PATH_IMAGE011
selecting a one bit path metric value
Figure 454931DEST_PATH_IMAGE009
The smallest as a survivor path and back-demodulating to obtain a one-bit differential viterbi demodulated bit stream. The depth of retrospective demodulation here is preferably 10 bits.
Obtaining theoretical phase difference of 16 states according to a pre-made two-bit difference Viterbi code element state table
Figure 727168DEST_PATH_IMAGE012
. The two bit differential viterbi symbol state table can be seen in table 2:
Figure DEST_PATH_IMAGE025
TABLE 2
The two-bit difference viterbi symbol state table is derived and calculated according to the following formula:
Figure DEST_PATH_IMAGE027
the above formula is also derived from GMSK modulation characteristics, wherein,
Figure 558727DEST_PATH_IMAGE020
in the form of a circumferential ratio,
Figure 546274DEST_PATH_IMAGE028
for the (n-4) th symbol,
Figure 832899DEST_PATH_IMAGE021
for the (n-3) th symbol,
Figure 222292DEST_PATH_IMAGE022
for the (n-2) th symbol,
Figure 37801DEST_PATH_IMAGE023
is the (n-1) th code element, the value of the code element is 1 or-1,
Figure 515575DEST_PATH_IMAGE024
is the modulation waveform parameter of GMSK.
According to the actual phase difference
Figure 871470DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 115369DEST_PATH_IMAGE012
Calculating two-bit path metric values
Figure 632938DEST_PATH_IMAGE013
Comprises the following steps:
Figure DEST_PATH_IMAGE029
selecting a two-bit path metric value
Figure 657395DEST_PATH_IMAGE013
The smallest one is taken as a survivor path and demodulated back to obtain a two-bit differential viterbi demodulated bit stream. The depth of retrospective demodulation here is also preferably 10 bits.
Referring to fig. 1 and 2, CRC check is performed on the data subjected to the one-bit differential viterbi demodulation and the packet demodulation, respectively, to determine whether the data subjected to the two-bit differential viterbi demodulation and the packet demodulation is correct, if so, the data subjected to the two-bit differential viterbi demodulation and the packet demodulation is output as a demodulated signal, otherwise, it is continuously determined whether the data subjected to the one-bit differential viterbi demodulation and the packet demodulation is correct, if so, the data subjected to the one-bit differential viterbi demodulation and the packet demodulation is output as a demodulated signal, and otherwise, the data is not output.
Referring to fig. 4, the invention can make the system reach a system Packet Error Rate (PER) < 20% under a baseband signal-to-noise ratio of 5dB, and reach a system packet error rate < 0.1% (system frequency offset 500 Hz) under 10dB, which can bring a performance improvement of more than 2 dB.
Referring to fig. 1 to 3, based on the above embodiments, those skilled in the art can easily understand that the present invention further provides a signal demodulation apparatus based on a joint-in-one, two-bit differential viterbi, which includes a receiving module 1, a first demodulation module 2, a second demodulation module 3, a first unpacking module 4, a second unpacking module 5, a first CRC check module 6, a second CRC check module 7, and a demodulation and output module 8.
The receiving module 1 is configured to receive the AIS signals and process the received AIS signals into two paths.
The first demodulation module 2 is used for performing one-bit differential viterbi demodulation on one path of AIS signals, and the first unpacking module 4 is used for performing AIS data unpacking processing on the signals demodulated by the first demodulation module 2. The second demodulation module 3 is configured to perform two-bit differential viterbi demodulation on the other path of AIS signals, and the second unpacking module 5 performs AIS data unpacking processing on the signals demodulated by the second demodulation module 3.
Specifically, the first demodulation module 2 and the second demodulation module 3 perform one-bit differential viterbi demodulation and two-bit differential viterbi demodulation in the following manner:
calculation Start and initialization
Figure 285822DEST_PATH_IMAGE001
Is 0.
The phase information is calculated for each received AIS signal.
Calculating an actual phase difference for a symbol time interval from the phase information
Figure 930035DEST_PATH_IMAGE001
Comprises the following steps:
Figure 618506DEST_PATH_IMAGE003
wherein,
Figure 802362DEST_PATH_IMAGE004
for the nth symbol period of the AIS signal
Figure 234481DEST_PATH_IMAGE005
The phase of (a) is determined,
Figure 452972DEST_PATH_IMAGE006
is AIS signal No
Figure 312344DEST_PATH_IMAGE007
One symbol period
Figure 983497DEST_PATH_IMAGE005
N is a natural number greater than 1.
Obtaining theoretical phase differences of 8 states according to a pre-made one-bit difference Viterbi code element state table
Figure 953727DEST_PATH_IMAGE008
. Specifically, the one-bit differential viterbi symbol state table can be seen in table 1:
Figure 29655DEST_PATH_IMAGE030
TABLE 1
The one-bit differential viterbi symbol state table is derived and calculated according to the following formula:
Figure DEST_PATH_IMAGE031
the above formula is derived from GMSK modulation characteristics, wherein,
Figure 918982DEST_PATH_IMAGE020
in the form of a circumferential ratio,
Figure 811852DEST_PATH_IMAGE021
for the (n-3) th symbol,
Figure 585773DEST_PATH_IMAGE022
for the (n-2) th symbol,
Figure 513277DEST_PATH_IMAGE023
is the (n-1) th code element, the value of the code element is 1 or-1,
Figure 980031DEST_PATH_IMAGE024
is the modulation waveform parameter of GMSK.
According to the actual phase difference
Figure 628706DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 206317DEST_PATH_IMAGE008
Calculating a one-bit path metric value
Figure 988329DEST_PATH_IMAGE009
Comprises the following steps:
Figure 360404DEST_PATH_IMAGE032
selecting a one bit path metric value
Figure 24604DEST_PATH_IMAGE009
The smallest as a survivor path and back-demodulating to obtain a one-bit differential viterbi demodulated bit stream. The depth of retrospective demodulation here is preferably 10 bits.
Obtaining theoretical phase difference of 16 states according to a pre-made two-bit difference Viterbi code element state table
Figure 140327DEST_PATH_IMAGE012
. The two bit differential viterbi symbol state table can be seen in table 2:
Figure DEST_PATH_IMAGE033
TABLE 2
The two-bit differential viterbi symbol state table is derived and calculated according to the following formula:
Figure 373250DEST_PATH_IMAGE034
the above formula is also derived from GMSK modulation characteristics, wherein,
Figure 181806DEST_PATH_IMAGE020
in the form of a circumferential ratio,
Figure 802143DEST_PATH_IMAGE028
for the (n-4) th symbol,
Figure 455978DEST_PATH_IMAGE021
for the (n-3) th symbol,
Figure 212582DEST_PATH_IMAGE022
for the (n-2) th symbol,
Figure 457618DEST_PATH_IMAGE023
is the (n-1) th code element, the value of the code element is 1 or-1,
Figure 299672DEST_PATH_IMAGE024
is the modulation waveform parameter of GMSK.
According to the actual phase difference
Figure 491619DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 359519DEST_PATH_IMAGE012
Calculating two-bit path metric values
Figure 244299DEST_PATH_IMAGE013
Comprises the following steps:
Figure 573649DEST_PATH_IMAGE015
selecting a two-bit path metric value
Figure 834866DEST_PATH_IMAGE013
The smallest as a survivor path and back-demodulating to obtain a two-bit differential viterbi demodulated bit stream. The depth of retrospective demodulation is also preferably 10 bits here.
The first CRC check module 6 is configured to perform CRC check on the data unpacked by the first unpacking module 4, so as to determine whether the data unpacked by the first unpacking module 4 is correct.
The second CRC check module 7 is configured to perform CRC check on the data unpacked by the second unpacking module 5, so as to determine whether the data unpacked by the second unpacking module 5 is correct.
The demodulation and merging output module 8 is configured to output the data unpacked by the second unpacking module 5 as a demodulation signal when the data unpacked by the second unpacking module 5 is correct, and output the data unpacked by the first unpacking module 4 as a demodulation signal if the data unpacked by the first unpacking module 4 is correct when the data unpacked by the second unpacking module 5 is incorrect, or not output the data.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Numerous modifications and adaptations may be made without departing from the principles of the present invention and such modifications and adaptations are intended to be within the scope of the present invention.

Claims (6)

1. A signal demodulation method based on a united one-bit difference Viterbi is characterized by comprising the following steps:
receiving an AIS signal and processing the AIS signal into two paths;
performing one-bit differential Viterbi demodulation and two-bit differential Viterbi demodulation on the two paths of AIS signals respectively, and performing AIS data unpacking processing on the demodulated signals respectively;
and respectively performing CRC (cyclic redundancy check) on the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing and the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing to judge whether the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing is correct or not, if so, outputting the data subjected to the two-bit differential Viterbi demodulation and the packet demodulation processing as a demodulation signal, otherwise, continuously judging whether the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing is correct or not, and if so, outputting the data subjected to the one-bit differential Viterbi demodulation and the packet demodulation processing as a demodulation signal, otherwise, not outputting the data.
2. The method of claim 1 wherein the one-bit differential viterbi demodulation and the two-bit differential viterbi demodulation are performed in the following manner:
calculation Start and initialization
Figure 383412DEST_PATH_IMAGE001
Is 0;
calculating phase information for each received AIS signal;
calculating an actual phase difference for a symbol time interval based on the phase information
Figure 994522DEST_PATH_IMAGE001
Comprises the following steps:
Figure 144880DEST_PATH_IMAGE002
wherein,
Figure 474230DEST_PATH_IMAGE003
for the nth symbol period of the AIS signal
Figure 204289DEST_PATH_IMAGE004
The phase of (a) is determined,
Figure 201064DEST_PATH_IMAGE005
is AIS signal No
Figure 256745DEST_PATH_IMAGE006
One symbol period
Figure 807812DEST_PATH_IMAGE004
N is a natural number greater than 1;
obtaining theoretical phase differences of 8 states according to a pre-made one-bit difference Viterbi code element state table
Figure 395089DEST_PATH_IMAGE007
；
According to the actual phase difference
Figure 246370DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 269690DEST_PATH_IMAGE007
Calculating a one-bit path metric value
Figure 104791DEST_PATH_IMAGE008
Comprises the following steps:
Figure 707810DEST_PATH_IMAGE009
selecting a one bit path metric value
Figure 413598DEST_PATH_IMAGE008
The smallest path is taken as a survivor path and is backtracked and demodulated to obtain a bit differential Viterbi demodulation bit stream;
obtaining theoretical phase difference of 16 states according to a pre-made two-bit difference Viterbi code element state table
Figure 610749DEST_PATH_IMAGE010
；
According to the actual phase difference
Figure 136408DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 543119DEST_PATH_IMAGE010
Calculating two-bit path metric values
Figure 103413DEST_PATH_IMAGE011
Comprises the following steps:
Figure 406218DEST_PATH_IMAGE012
selecting a two bit path metric value
Figure 684753DEST_PATH_IMAGE011
The smallest as a survivor path and back-demodulating to obtain a two-bit differential viterbi demodulated bit stream.
3. The method of claim 2, wherein the retrospective demodulation is 10 bits deep.
4. A signal demodulation apparatus based on a joint unification, two bit difference Viterbi, comprising:
the receiving module is used for receiving the AIS signals and processing the AIS signals into two paths;
the first demodulation module is used for carrying out one-bit differential Viterbi demodulation on one path of AIS signals;
the second demodulation module is used for carrying out two-bit differential Viterbi demodulation on the other path of AIS signals;
the first unpacking module is used for carrying out AIS data unpacking processing on the signal demodulated by the first demodulation module;
the second unpacking module is used for carrying out AIS data unpacking processing on the signal demodulated by the second demodulating module;
the first CRC check module is used for performing CRC check on the data subjected to unpacking processing by the first unpacking module so as to judge whether the data subjected to unpacking processing by the first unpacking module is correct or not;
the second CRC check module is used for performing CRC check on the data subjected to unpacking processing by the second unpacking module so as to judge whether the data subjected to unpacking processing by the second unpacking module is correct or not;
and the demodulation combination output module is used for outputting the data unpacked by the second unpacking module as a demodulation signal when the data unpacked by the second unpacking module is correct, and outputting the data unpacked by the first unpacking module as a demodulation signal if the data unpacked by the first unpacking module is incorrect when the data unpacked by the second unpacking module is incorrect, otherwise, not outputting the data.
5. The apparatus of claim 4, wherein the one-bit differential viterbi demodulation and the two-bit differential viterbi demodulation are performed in the following manner:
calculation Start and initialization
Figure 629575DEST_PATH_IMAGE001
Is 0;
calculating phase information for each received AIS signal;
calculating an actual phase difference for a symbol time interval based on the phase information
Figure 778797DEST_PATH_IMAGE001
Comprises the following steps:
Figure 786592DEST_PATH_IMAGE013
wherein,
Figure 286843DEST_PATH_IMAGE003
is AIS signal Non symbol periods
Figure 35356DEST_PATH_IMAGE004
The phase of (a) is determined,
Figure 304664DEST_PATH_IMAGE005
is AIS signal No
Figure 480430DEST_PATH_IMAGE006
One symbol period
Figure 733557DEST_PATH_IMAGE004
The phase of (d);
obtaining theoretical phase differences of 8 states according to a pre-made one-bit difference Viterbi code element state table
Figure 20182DEST_PATH_IMAGE007
；
According to the actual phase difference
Figure 678084DEST_PATH_IMAGE001
And theoretical phase difference of 8 states
Figure 24751DEST_PATH_IMAGE007
Calculating a one-bit path metric value
Figure 234016DEST_PATH_IMAGE008
Comprises the following steps:
Figure 324332DEST_PATH_IMAGE014
selecting a one bit path metric value
Figure 833810DEST_PATH_IMAGE008
The smallest path is taken as a survivor path and backtracking demodulation is carried out to obtain a bit difference Viterbi demodulation bit stream;
according to pre-madeObtaining theoretical phase difference of 16 states by two-bit difference Viterbi code element state table
Figure 85800DEST_PATH_IMAGE010
；
According to the actual phase difference
Figure 313519DEST_PATH_IMAGE001
And a theoretical phase difference of 16 states
Figure 941947DEST_PATH_IMAGE010
Calculating two-bit path metric values
Figure 55001DEST_PATH_IMAGE011
Comprises the following steps:
Figure 9050DEST_PATH_IMAGE012
selecting a two bit path metric value
Figure 192907DEST_PATH_IMAGE011
The smallest as a survivor path and back-demodulating to obtain a two-bit differential viterbi demodulated bit stream.
6. The apparatus of claim 5, wherein the traceback demodulation depth is 10 bits.
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US20030118131A1 (en) * 2001-12-20 2003-06-26 Kobylinski Richard A. Joint demodulation using a viterbi equalizer having an adaptive total number of states
CN1710898A (en) * 2005-06-29 2005-12-21 西安电子科技大学 Modulation and demodulation method for continuous phase signals
CN102611457A (en) * 2012-02-29 2012-07-25 西安空间无线电技术研究所 Multidimensional TCM (Trellis Coded Modulation) decoder
WO2015107654A1 (en) * 2014-01-16 2015-07-23 三菱電機株式会社 Receiver and reception method
CN106453178A (en) * 2016-11-06 2017-02-22 中国电子科技集团公司第十研究所 Satellite-based AIS signal intercept and demodulation method
CN112152758A (en) * 2020-10-10 2020-12-29 交通运输部规划研究院 Navigation communication method and device

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US20030118131A1 (en) * 2001-12-20 2003-06-26 Kobylinski Richard A. Joint demodulation using a viterbi equalizer having an adaptive total number of states
CN1710898A (en) * 2005-06-29 2005-12-21 西安电子科技大学 Modulation and demodulation method for continuous phase signals
CN102611457A (en) * 2012-02-29 2012-07-25 西安空间无线电技术研究所 Multidimensional TCM (Trellis Coded Modulation) decoder
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