CN115172390B

CN115172390B - Display panel and manufacturing method thereof

Info

Publication number: CN115172390B
Application number: CN202211070973.3A
Authority: CN
Inventors: 李雍; 瞿澄; 陈文娟
Original assignee: Luohuaxin Display Technology Development Jiangsu Co ltd
Current assignee: Luohuaxin Display Technology Development Jiangsu Co ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2022-12-02
Anticipated expiration: 2042-09-02
Also published as: CN115172390A

Abstract

The invention provides a display panel and a manufacturing method thereof, and relates to the technical field of LED display. It comprises the following steps: the pixel limiting layer is arranged on the interlayer dielectric layer and is provided with at least one opening, and the first pattern and the second pattern are exposed out of the opening; the upper surface of the pixel defining layer has a recess portion having a plurality of sharp needles therein having a height not higher than the upper surface of the pixel defining layer; an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of sharp needles and a connection portion connecting the tip portions and the second pattern; and the cover plate is jointed on the upper surface of the pixel limiting layer and is provided with a transparent conducting layer opposite to the tip part. The structure of the embodiment of the invention utilizes the pixel limiting layer to form the sharp needle and carry out the conformal formation of the electrostatic discharge layer, thereby realizing that the electrostatic discharge path of the active layer is far away from the active layer and ensuring the reliability of the active layer.

Description

Display panel and manufacturing method thereof

Technical Field

The invention relates to the technical field of LED display, in particular to a display panel and a manufacturing method thereof.

Background

In the manufacturing process of the mini-LED or micro-LED display panel, many steps such as mass transfer, packaging, soldering, etc. are often included, and in these steps, some static electricity is always generated and finally remains in the display panel.

Static electricity enters the active layer along the conducting path, and excessive static electricity causes charge accumulation, and once the discharging path occurs, a large current is generated during discharging, and the large current is not favorable for the active layer. In the prior art, although an electrostatic discharge path is provided for electrostatic protection, the electrostatic discharge path is too close to an active layer and is insufficiently discharged, which may cause leakage influence on the active layer of the thin film transistor.

Disclosure of Invention

In order to solve the above problems, the present invention provides a display panel including:

a substrate;

a gate disposed on the substrate;

the grid dielectric layer covers on the grid electrode;

the active layer is arranged on the gate dielectric layer;

the two source and drain electrodes are attached to the active layer and are respectively positioned on two opposite sides of the active layer;

the redundant electrode is attached to the active layer and positioned between the two source drain electrodes;

the interlayer dielectric layer is arranged on the gate dielectric layer and covers the active layer and the two source drain electrodes;

a wiring pattern disposed on the interlayer dielectric layer and including a first pattern electrically connected to one of the two source/drain electrodes and a second pattern electrically connected to the redundant electrode;

the pixel limiting layer is arranged on the interlayer dielectric layer and is provided with at least one opening, and the first pattern and the second pattern are exposed out of the opening; the upper surface of the pixel defining layer has a recess having a plurality of sharp pins therein having a height not higher than the upper surface of the pixel defining layer;

an LED chip bonded to the first pattern;

an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of sharp needles and a connection portion connecting the tip portions and the second pattern;

and the cover plate is jointed on the upper surface of the pixel limiting layer and is provided with a transparent conducting layer opposite to the tip part.

According to the embodiment of the present invention, the tip ends of the plurality of tip portions have a space from the transparent conductive layer.

According to an embodiment of the present invention, further comprising a sealing layer filled in the opening, the sealing layer being filled in the concave portion and the space at the same time.

According to an embodiment of the present invention, the height of the plurality of sharp pins is 0.5-1 μm.

According to the embodiment of the present invention, the area of the concave portion occupies 1 to 10% of the area of the upper surface of the pixel defining layer when viewed from above.

According to the embodiment of the invention, the recessed portion has an overlapping portion with a projection of the active region on the substrate in a plan view.

According to the embodiment of the present invention, the second pattern has an overlapping portion with a projection of the redundant electrode on the substrate when viewed from above.

Further, the present invention also provides a method for manufacturing a display panel, which includes:

(1) Providing a substrate, and forming a grid on the substrate;

(2) Depositing a gate dielectric layer on the substrate, wherein the gate dielectric layer covers the gate;

(3) Forming an active layer on the gate dielectric layer;

(4) Depositing a first conductive layer on the active layer and patterning to form two source drain electrodes and a redundant electrode; the two source and drain electrodes are attached to the active layer and are respectively positioned on two opposite sides of the active layer, and the redundant electrode is attached to the active layer and is positioned between the two source and drain electrodes;

(5) Depositing an interlayer dielectric layer and a second conductive layer on the gate dielectric layer, and patterning the second conductive layer to form a wiring pattern on the interlayer dielectric layer, wherein the wiring pattern comprises a first pattern electrically connected with one of the two source/drain electrodes and a second pattern electrically connected with the redundant electrode;

(6) Forming a pixel defining layer on the interlayer dielectric layer, the pixel defining layer having at least one opening therein formed by an etching process, the opening exposing the first pattern and the second pattern;

(7) Forming a recess on an upper surface of the pixel defining layer by a laser ablation process, the recess having therein a plurality of sharp pins having a height not higher than the upper surface of the pixel defining layer;

(8) Bonding an LED chip in the opening, the LED chip being bonded to the first pattern;

(9) Forming an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of sharp needles and a connection portion connecting the tip portions and the second pattern by using a local deposition process;

(10) A cover plate is bonded to an upper surface of the pixel defining layer, the cover plate having a transparent conductive layer facing the tip portion.

According to the embodiment of the invention, when the laser ablation process is carried out, a laser beam grid-shaped scanning mode is adopted, so that the plurality of tapered sharp needles are obtained.

According to the embodiment of the invention, before the cover plate is jointed, the step of filling the sealing layer in the opening and grinding the opening to enable the pixel defining layer to be flush with the upper surface of the sealing layer is further included.

The invention has the following beneficial effects: the display panel of the present invention includes: the pixel limiting layer is arranged on the interlayer dielectric layer and provided with at least one opening, and the first pattern and the second pattern are exposed out of the opening; the upper surface of the pixel defining layer is provided with a concave part, and the concave part is internally provided with a plurality of sharp needles with the height not higher than the upper surface of the pixel defining layer; an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of sharp needles and a connection portion connecting the tip portions and the second pattern; and the cover plate is jointed on the upper surface of the pixel limiting layer and is provided with a transparent conducting layer opposite to the tip part. The structure of the embodiment of the invention utilizes the pixel limiting layer to form the sharp needle and carry out the conformal formation of the electrostatic discharge layer, thereby realizing that the electrostatic discharge path of the active layer is far away from the active layer and ensuring the reliability of the active layer. Furthermore, in the manufacturing process, the number of the mask layers for forming the wiring layer only needs to be increased by one layer, namely, the mask used when the electrostatic discharge layer is formed is obtained, and in other steps, the number and the structure of the masks are basically consistent with those of the traditional mask, and only the related patterns of a plurality of electrostatic discharge paths are formed.

Meanwhile, in order to ensure a short electrostatic discharge path, the recess portion has an overlapping portion with a projection of the active region on the substrate, and the second pattern has an overlapping portion with a projection of the redundant electrode on the substrate, as viewed from above. Therefore, the electrostatic discharge path can be arranged in the vertical direction of the active layer, the path length is reduced, and the instantaneity and the reliability of electrostatic discharge are ensured.

In addition, the cover plate of the present invention is configured to have a transparent conductive layer (TCO) facing the electrostatic discharge layer, which is electrically connected to a ground or common electrode through an electrical connection structure of the non-display area, thereby implementing tip discharge of static electricity.

Drawings

FIG. 1 is a cross-sectional view of a display panel according to the present invention;

FIG. 2 is a top view of a pixel defining layer of the present invention;

FIG. 3 is a schematic diagram of a thin film transistor formed on a substrate;

FIG. 4 is a schematic view of forming a wiring pattern;

fig. 5 is a schematic view of forming a pixel defining layer;

FIG. 6 is a schematic view of the formation of a plurality of sharp needles;

FIG. 7 is a schematic view after bonding and sealing of the LED;

fig. 8 is a schematic view after joining the cover plates.

Description of reference numerals:

10. a substrate; 11. a buffer layer; 12. a gate electrode; 13. a gate dielectric layer; 14. an active layer; 15. a first source/drain electrode; 16. a second source/drain electrode; 17. a redundant electrode; 18. an interlayer dielectric layer; 19. a first through hole; 20. a second through hole; 21. a first pattern; 22. a second pattern; 23. a pixel defining layer; 24. an opening; 25. a sharp needle; 26. an electrostatic discharge layer; 27. an LED chip; 28. a sealing layer; 29. a transparent conductive layer; 30. and a cover plate.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure.

The embodiment of the invention discloses a display panel which is a mini-LED or micro-LED display panel, and specifically comprises the following components: a substrate; a gate disposed on the substrate; the grid dielectric layer covers the grid electrode; the active layer is arranged on the gate dielectric layer; the two source drain electrodes are attached to the active layer and are respectively positioned on two opposite sides of the active layer; the redundant electrode is attached to the active layer and positioned between the two source drain electrodes; the interlayer dielectric layer is arranged on the gate dielectric layer and covers the active layer and the two source drain electrodes; a wiring pattern disposed on the interlayer dielectric layer and including a first pattern electrically connected to one of the two source-drain electrodes and a second pattern electrically connected to the redundant electrode; the pixel limiting layer is arranged on the interlayer dielectric layer and is provided with at least one opening, and the first pattern and the second pattern are exposed out of the opening; the upper surface of the pixel defining layer has a recess having a plurality of sharp pins therein having a height not higher than the upper surface of the pixel defining layer; an LED chip bonded to the first pattern; an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of pointed needles and a connection portion connecting the tip portions and the second pattern; and the cover plate is jointed on the upper surface of the pixel limiting layer and is provided with a transparent conducting layer opposite to the tip part.

Referring to fig. 1, the display panel of the present invention is formed on a base plate 10, and the base plate 10 serves to block oxygen and moisture, prevent diffusion of moisture or impurities through a substrate, and provide a flat surface on an upper surface of the substrate. The substrate 10 may be made of an inorganic material such as silicon or silicon nitride, or may be made of a polymer material such as glass, polycarbonate (PC), polyether sulfone (PES), polyethylene terephthalate (PET), polyarylate (PAR), or glass Fiber Reinforced Plastic (FRP). In the present invention, the substrate 10 may be transparent or translucent, or may be opaque. In particular, the substrate 10 may have a certain flexibility.

A buffer layer 11 is formed on the substrate 10, and the buffer layer 11 has a slightly thinner adhesive layer structure. The buffer layer 11 may cover the entire upper surface of the substrate 10. For example, the buffer layer 11 may be made of a material selected from inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SioxNy), aluminum oxide (AlOx), or aluminum nitride (AlNx). Of course, in other alternative embodiments of the present invention, the buffer layer may be formed of a material selected from organic materials such as acryl, polyimide (PI), or polyester. The buffer layer 11 may include a single layer or a plurality of layers. The buffer layer 11 serves as an adhesion layer for the subsequent gate electrode 12, and can block impurities in the substrate from diffusing to other film layers.

The gate electrode 12 is a discrete plurality and is formed on the buffer layer 11, and the gate electrode 12 is formed by conventional sputtering or the like, and may be further formed by etching processes such as exposure and development. The material of the gate electrode 12 is preferably Al, cu, ag, or the like. In an embodiment of the present invention, the gate electrode 12 is formed directly below the active layer 14.

A gate dielectric layer 13 overlies the gate electrode 12, and the gate dielectric layer 13 includes an inorganic layer such as silicon oxide, silicon nitride, and may include a single layer or multiple layers that separate the gate electrode 12 and the active layer 14 of the thin film transistor above and below.

An active layer 14 is formed on the gate dielectric layer 13, and the active layer 14 has a plurality of rectangular patterns with the same pitch. The active layer 14 is formed by deposition and may be a silicon material, a germanium material, or a silicon germanium material. The active layer 14 completely covers the gate electrode 12 when viewed from above, and the gate electrode 12 corresponds to a central region of the active layer. Source and drain electrodes, i.e., a first source/drain electrode 15 and a second source/drain electrode 16, are disposed at opposite edge sides of the active layer 14, wherein the first source/drain electrode 15 may be one of a source electrode or a drain electrode, and the second source/drain electrode 16 may be the other of the source electrode or the drain electrode. The first source/drain electrode 15 and the second source/drain electrode 16 overlap on opposite sides of the active layer 14, and have a portion on the active layer 14 and another portion extending onto the gate dielectric layer 13.

A redundancy electrode 17 is further disposed in the middle region on the active layer 14, the redundancy electrode 17 is positioned between the first and second source/

drain electrodes

15 and 16, and the first and second source/

drain electrodes

15 and 16 and the redundancy electrode 17 are arranged in a single row on the active layer 14. On each active layer 14, the end of the redundant electrode 17 is less than 10 microns away from the first source/drain electrode 15 and the second source/drain electrode 16, and the redundant electrode 17 can release electrostatic charges in the active layer 14, so that electrostatic discharge is realized. Wherein the redundancy electrode 17, the first source/drain electrode 15, and the second source/drain electrode 16 may be formed in the same step.

An interlayer dielectric layer 18 is covered on the gate dielectric layer 13, and the interlayer dielectric layer 18 completely covers the active layer 14, the redundancy electrode 17, the first source/drain electrode 15, and the second source/drain electrode 16. The interlayer dielectric layer 18 may be formed of an inorganic layer insulation of silicon oxide, silicon nitride, or the like. Of course, in other alternative embodiments of the present invention, the interlayer dielectric layer 18 may be formed of an organic insulating material. There are also first contact holes 19 in the interlayer dielectric layer 18 to electrically connect the redundancy electrodes 17, and second contact holes 20 in the interlayer dielectric layer 18 to electrically connect the source/drain electrodes (i.e., the first source/drain electrode 15 and the second source/drain electrode 16). The first contact hole 19 and the second contact hole 20 may be formed by etching a via hole in the interlayer dielectric layer 18 and filling a conductive material.

A wiring pattern including at least a first pattern 21 and a second pattern 22 is provided on the interlayer dielectric layer 18. The first pattern 21 and the second pattern 22 are formed in the same deposition step and etching step, and may be made of copper or aluminum. The first pattern 21 is electrically connected to the redundant electrode and the second pattern 22 is electrically connected to one of the first source/connection 15 and the second source/connection 16.

An LED chip 27 is bonded on the second pattern 22, and the LED chip 27 is preferably a mini-LED chip or a micro-LED chip. The LED chips 27 are bonded by using a bulk transfer technique, and a specific bonding method may be a soldering technique. The first pattern 21 has an overlapping portion with a projection of the redundant electrode 17 on the substrate 10, which is to shorten an electrostatic discharge path and reduce an occupancy of a surface.

A pixel defining layer 23 is formed on the interlayer dielectric layer 18, and the pixel defining layer 23 has a grid structure such that each LED chip 27 is spaced apart, which can ensure the alignment of the sub-pixels. The pixel defining layer 23 has a trapezoidal cross section with its top surface higher than the top surface of the LED chip 27. The pixel defining layer 23 may be an organic layer or an inorganic layer of an insulating material, and may include, for example, an organic material such as acryl, polyimide (PI), or benzocyclobutene (BCB), or an inorganic material such as silicon nitride, silicon oxide, which is formed into a grid-like structure having a plurality of openings by etching, each LED chip being disposed in each opening.

In particular, the top 23 of the pixel defining layer with the grid-shaped structure further has the concave portions 24, the concave portions 24 are also formed by the etching process, and the concave portions 24 can be formed on the pixel defining layer 23 in an array manner, for example, a concave portion 24 is formed on two sides of each LED chip 27, or a concave portion 24 is formed on four sides of each LED chip 27. In each recess 24, a plurality of sharp pins 25 are formed simultaneously during the etching process, and the number of the plurality of sharp pins 25 in each recess 24 may be two or more, preferably two. Specifically, the tips of the plurality of sharp pins 25 do not exceed the top surface of the pixel defining layer 23, and the height of the plurality of sharp pins 25 is 0.5 to 1 μm. The plurality of sharp needles 25 are formed by selectively etching the pixel defining layer 23, and may also be formed by a laser ablation process, and the specific manner of formation is not limited herein.

An electrostatic discharge layer 24 is formed on the interlayer dielectric layer 18, one end of the electrostatic discharge layer 24 is connected to the first pattern 21, and the other end extends along the sidewall of the pixel defining layer 23 to the plurality of sharp pins 25, where the electrostatic discharge layer 24 is formed conformally, i.e., has a plurality of sharp point structures formed as discharge points for discharging static electricity at the plurality of sharp pins 25. The electrostatic discharge layer 24 may be a metal material such as aluminum, copper, or the like.

Further, for uniform distribution of the release paths, a plurality of concave portions 24 are uniformly formed in the pixel defining layer 23. And, the area of the recess portion 24 occupies 1-10% of the area of the upper surface of the pixel defining layer 23. When the recess 24 and the projection of the active region 14 on the substrate 10 have an overlapping portion in a top view, this arrangement can minimize the discharge path of static electricity, and ensure the timeliness of static electricity discharge.

The sealing layer 28 is filled in the opening of the pixel defining layer 23, and the sealing layer 28 is also simultaneously filled in the recess 24 to cover the topmost end, i.e., the tip structure, of the electrostatic discharge layer 24. The sealing layer 28 may be a heat-curable or light-curable resin, which may be a modified epoxy resin or polyimide, or the like. The sealing layer 28 also seals the plurality of LED chips 27 at the same time.

A cover plate 30 made of transparent material is bonded to the sealing layer 28, and a transparent conductive layer 29 is further provided on the lower surface of the cover plate 30. The transparent conductive layer 29 is preferably made of an oxide material such as ITO, AZO, FTO, etc., and is disposed opposite to the plurality of sharp pins 25 and spaced apart from the plurality of sharp structures of the electrostatic discharge layer 24 by a certain distance, which is occupied by the sealing layer 28. The transparent conductive layer 29 may be eventually connected to ground or a common electrode for achieving discharge of static electricity.

The display panel of the present invention includes: the pixel limiting layer is arranged on the interlayer dielectric layer and provided with at least one opening, and the first pattern and the second pattern are exposed out of the opening; the upper surface of the pixel defining layer has a recess portion having a plurality of sharp needles therein having a height not higher than the upper surface of the pixel defining layer; an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of sharp needles and a connection portion connecting the tip portions and the second pattern; and the cover plate is jointed on the upper surface of the pixel limiting layer and is provided with a transparent conducting layer opposite to the tip part. According to the structure of the embodiment of the invention, the pixel limiting layer is used for forming the sharp needle and conformal formation of the electrostatic discharge layer, so that the electrostatic discharge path of the active layer is far away from the active layer, and the reliability of the active layer is ensured. Furthermore, in the manufacturing process, the number of the mask layers for forming the wiring layer only needs to be increased by one layer, namely, the mask used when the electrostatic discharge layer is formed is obtained, and in other steps, the number and the structure of the masks are basically consistent with those of the traditional mask, and only the related patterns of a plurality of electrostatic discharge paths are formed.

Based on the display panel, the invention also provides a manufacturing method of the display panel, which comprises the following steps:

(1) Providing a substrate, and forming a grid electrode on the substrate;

(3) Forming an active layer on the gate dielectric layer;

(4) Depositing a first conductive layer on the active layer and patterning to form two source-drain electrodes and a redundant electrode; the two source and drain electrodes are attached to the active layer and are respectively positioned on two opposite sides of the active layer, and the redundant electrode is attached to the active layer and is positioned between the two source and drain electrodes;

Referring first to fig. 3, a driving substrate is formed in advance, and the forming of the driving substrate includes depositing a buffer layer 11 on a substrate 10, and then forming a patterned gate 12 on the buffer layer 11, where the gate 12 is multiple and arranged in an array.

Next, a gate dielectric layer 13 is covered on the gate electrode 12, and the gate dielectric layer 13 may be a single-layer or multi-layer structure formed by layer deposition, such as CVD, ALD, etc. Further, an active layer 14 is deposited on the gate dielectric layer 13, and the active layer 14 has a patterned structure, which corresponds to the pattern of the gate electrode 12 one-to-one. The active layer 14 may be a semiconductor layer, such as silicon, germanium, or alloys thereof.

Depositing a first conductive layer on the active layer 14 and patterning to form two source and drain

electrodes

15 and 16 and a redundant electrode 17; the two source and drain

electrodes

15 and 16 are attached to the active layer 14 and located on two opposite sides of the active layer 14, respectively, and the redundant electrode 17 is attached to the active layer 14 and located between the two source and drain

electrodes

15 and 16.

Then, referring to fig. 4, an interlayer dielectric layer 18 is coated on the gate dielectric layer 13, and a via hole is etched in the interlayer dielectric layer 18 and filled with a conductive material to form a first via hole 19 connecting the source-

drain electrodes

15, 16 and a second via hole 20 connecting the redundancy electrode 17.

And depositing a second conductive layer on the interlayer dielectric layer 18, and patterning the second conductive layer to form a wiring pattern on the interlayer dielectric layer 18, wherein the wiring pattern comprises a first pattern 22 electrically connected with one of the two source/drain electrodes and a second pattern 21 electrically connected with the redundant electrode 17. The first pattern 22 is electrically connected to the source/

drain electrodes

15 and 16 through the second via hole 20, and the second pattern 21 is electrically connected to the redundant electrode 17 through the first via hole 19.

A pixel defining layer 23 is formed on the interlayer dielectric layer 18, and the pixel defining layer has at least one opening formed therein by an etching process, the opening exposing the first pattern 22 and the second pattern 21, and the openings are used for accommodating LED chips, as shown in fig. 5.

Referring then to fig. 6, recesses 24 are formed in the pixel defining layer 23 using an anisotropic etching process or a laser ablation process, the recesses 24 having a square or circular structure with a plurality of sharp needles 25 having a height not higher than the upper surface of the pixel defining layer 23 inside. When the laser ablation process is carried out, a laser beam grid scanning mode is adopted, and therefore the plurality of conical sharp needles 25 are obtained.

Next, referring to fig. 7, a plurality of LED chips 27 are bonded in the openings, and the plurality of LED chips 27 may be mini-LEDs or micro-LEDs. The LED chip 27 is electrically connected to one of the source-

drain electrodes

15, 16. Further, the electrostatic discharge layer 26 is formed by a local deposition process, and the electrostatic discharge layer 26 is a metal layer having a plurality of tip portions conformal to the plurality of sharp pins 25 and a connection portion connecting the tip portions and the second pattern 21.

The openings are filled with a sealing material to form a sealing layer 28, the sealing layer 28 covers the tips of the electrostatic discharge layer 26, and the pixel defining layer 23 is made flush with the upper surface of the sealing layer 28 by grinding the sealing layer 28. A cover plate 30 is bonded to the upper surface of the pixel defining layer 23, the cover plate 30 having a transparent conductive layer 29 facing the tip portions, as shown in fig. 8.

In the manufacturing process, the number of the mask layers for forming the wiring layer only needs to be increased by one layer, namely, the mask used when the electrostatic discharge layer is formed is obtained, and in other steps, the number and the structure of the masks are basically consistent with those of the traditional mask, and only relevant patterns of a plurality of electrostatic discharge paths are formed.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A display panel, comprising:

a substrate;

a gate disposed on the substrate;

the grid dielectric layer covers on the grid electrode;

the active layer is arranged on the gate dielectric layer;

the two source drain electrodes are attached to the active layer and are respectively positioned on two opposite sides of the active layer;

an LED chip bonded to the first pattern;

an electrostatic discharge layer having a plurality of tip portions conformal to the plurality of pointed needles and a connection portion connecting the tip portions and the second pattern;

a cover plate bonded on the upper surface of the pixel defining layer and having a transparent conductive layer facing the tip portion; wherein, there is the interval between the top of a plurality of cusp portions and the transparent conducting layer.

2. The display panel according to claim 1, characterized in that: and a sealing layer filled in the opening, wherein the sealing layer is filled in the concave part and the interval at the same time.

3. The display panel according to claim 1, characterized in that: the height of the plurality of sharp needles is 0.5-1 μm.

4. The display panel according to claim 1, characterized in that: the area of the concave portion occupies 1-10% of the area of the upper surface of the pixel defining layer when viewed from above.

5. The display panel according to claim 1, characterized in that: when viewed from above, the recessed portion and the projection of the active layer on the substrate have an overlapping portion.

6. The display panel according to claim 1, characterized in that: when viewed from above, the second pattern and the redundant electrode have an overlapping part projected on the substrate.

7. A method of manufacturing a display panel, comprising:

(1) Providing a substrate, and forming a grid on the substrate;

(3) Forming an active layer on the gate dielectric layer;

(5) Depositing an interlayer dielectric layer and a second conducting layer on the gate dielectric layer, and patterning the second conducting layer to form a wiring pattern on the interlayer dielectric layer, wherein the wiring pattern comprises a first pattern electrically connected with one of the two source/drain electrodes and a second pattern electrically connected with the redundant electrode;

(7) Forming a recess on an upper surface of the pixel defining layer through a laser ablation process or an anisotropic etching process, the recess having a plurality of sharp pins therein having a height not higher than the upper surface of the pixel defining layer;

(10) Attaching a cover plate on an upper surface of the pixel defining layer, the cover plate having a transparent conductive layer facing the tip portion; wherein a space is provided between the top ends of the plurality of tip portions and the transparent conductive layer.

8. The method for manufacturing a display panel according to claim 7, wherein: when the laser ablation process is implemented, a laser beam grid scanning mode is adopted to realize, so that the plurality of conical sharp needles are obtained.

9. The method for manufacturing a display panel according to claim 7, wherein: before the cover plate is jointed, the method further comprises the steps of filling a sealing layer in the opening and grinding the opening so that the pixel defining layer is flush with the upper surface of the sealing layer.