CN115172257A - Substrate structure on silicon nitride and preparation method thereof - Google Patents

Substrate structure on silicon nitride and preparation method thereof Download PDF

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Publication number
CN115172257A
CN115172257A CN202210821047.9A CN202210821047A CN115172257A CN 115172257 A CN115172257 A CN 115172257A CN 202210821047 A CN202210821047 A CN 202210821047A CN 115172257 A CN115172257 A CN 115172257A
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substrate
dielectric layer
layer
silicon
silicon nitride
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CN202210821047.9A
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亨利·H·阿达姆松
苗渊浩
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Guangzhou Nuoer Optoelectronics Technology Co ltd
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Guangzhou Nuoer Optoelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

The invention relates to a substrate structure on silicon nitride and a preparation method thereof. A method of fabricating a substrate structure on silicon nitride, comprising the steps of: providing a first substrate; forming a first dielectric layer on a first substrate; forming a SiNx layer on the first dielectric layer; etching the SiNx layer to form a plurality of grooves; forming a second dielectric layer covering the SiNx layer and filling the groove; carrying out flattening treatment on the surface of the second dielectric layer to obtain an insulated substrate; processing the insulated substrate in any one of the following modes: depositing a semiconductor material on the second dielectric layer in a first mode; bonding the insulated substrate with a second substrate of which the upper surface is provided with a third dielectric layer, wherein the bonding surface is the third dielectric layer and the second dielectric layer; the second substrate is then optionally thinned. The invention solves the problems of uncontrollable strain quantity of the top semiconductor material, complex process and high cost in the prior art.

Description

Substrate structure on silicon nitride and preparation method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a substrate structure on silicon nitride and a preparation method thereof.
Background
The SOI technology can realize the medium isolation of elements in an integrated circuit, and the substrate eliminates the parasitic latch-up effect in a bulk silicon CMOS circuit. In addition, the technology has the advantages of small parasitic capacitance, high integration level, high speed, simple process, small short channel effect, low voltage, low power consumption, low leakage current, compatibility with the existing silicon process and the like. However, the existing SOI substrate is expensive to manufacture, and the stress control of the top silicon layer is difficult, so that the application scenarios of the SOI technology are limited.
The invention is therefore proposed.
Disclosure of Invention
The invention mainly aims to provide a substrate structure on silicon nitride and a preparation method thereof, and solves the problems of uncontrollable strain of a top semiconductor material, complex process and high cost in the prior art.
In order to achieve the above object, the present invention provides the following technical solutions.
A first aspect of the invention provides a method of fabricating a substrate structure on silicon nitride, comprising the steps of:
providing a first substrate;
forming a first dielectric layer on the first substrate;
forming a SiNx layer on the first dielectric layer;
etching the SiNx layer to form a plurality of grooves;
forming a second dielectric layer covering the SiNx layer and filling the groove;
carrying out flattening treatment on the surface of the second dielectric layer to obtain an insulated substrate;
and (c) subjecting the insulated substrate to any one of the following processes:
depositing a semiconductor material on the second dielectric layer in a first mode;
bonding the insulated substrate with a second substrate with a third dielectric layer formed on the upper surface, wherein the bonding surface is the third dielectric layer and the second dielectric layer; the second substrate is then optionally thinned.
According to the method, the strain quantity of the top semiconductor material or the transferred second substrate can be regulated and controlled through the stacking of the multiple dielectric layers and the SiNx layer and the distribution of the grooves in the SiNx layer, so that the mobility and other electrical characteristics of a device prepared by using the substrate are improved.
In addition, compared with the existing Smart-cut technology, the method has the advantages of simplified process, obviously reduced manufacturing cost and more choices: the semiconductor material can be directly grown, and can also be bonded.
In some embodiments, the first substrate is a silicon substrate, and the first dielectric layer is preferably silicon oxide and is formed by a thermal oxidation method.
Among various typical substrates such as sapphire substrates, silicon carbide substrates, silicon substrates and the like, the silicon substrates have better compatibility and low cost, and are compatible with the existing process equipment.
The process can be further simplified by forming silicon oxide as a dielectric layer on the silicon substrate by thermal oxidation.
In some embodiments, the bonding means is fusion bonding.
In some embodiments, the planarization treatment is performed on the surface of the second dielectric layer by the following method:
firstly grinding and polishing or dry etching, TMAH corrosion and then chemical mechanical polishing treatment.
A second aspect of the invention provides a substrate structure on silicon nitride, prepared by the above method.
In some embodiments, the first dielectric layer, the second dielectric layer and the third dielectric layer are made of at least one of silicon oxide and aluminum oxide independently.
In some embodiments, the first dielectric layer is silicon oxide, the second dielectric layer is silicon oxide, and the third dielectric layer is aluminum oxide.
In some embodiments, the thickness of the SiNx layer is 100-500 nm;
and/or the presence of a gas in the gas,
the thickness of the first dielectric layer reaches 10-500 nm;
and/or the presence of a gas in the atmosphere,
the thickness of the thinned semiconductor material or the second substrate reaches 5-100 nm.
Substrates of the above thicknesses are more suitable for making depletion type devices. Because the thickness of the semiconductor materials such as the buried oxide layer of the fully depleted substrate, the top silicon and the like is thinner, the parasitic capacitance is smaller, the speed is higher, the power consumption is lower, and the radiation resistance is extremely strong, so that the fully depleted substrate is particularly suitable to be used as a channel material of a high-mobility transistor. Compared with FinFETs, the fully depleted insulator-on-substrate technology can effectively inhibit pulse current interference of the substrate, reduce soft errors, is simpler in design and manufacture, can be widely applied to the fields of automotive electronics, IT network infrastructures, servers, consumer electronics, internet of things, radars, power supply batteries, wearable electronics, network machine learning, artificial intelligence, intelligent driving and the like, and has great scientific value and economic benefits.
In some embodiments, the first substrate is a silicon substrate.
In some embodiments, the second substrate and the semiconductor material are one of Si, ge, siGe, geSn, gaAs, inGaAs, inAs.
Compared with the prior art, the invention achieves the following technical effects:
(1) The strain of semiconductor materials such as top Si, ge, siGe, geSn, gaAs, inGaAs, inAs and the like in the substrate structure on the silicon nitride is improved, and the fully depleted device is suitable for being manufactured.
(2) The manufacturing process is simplified, and the manufacturing cost is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 to 5 are schematic structural diagrams obtained in steps of a substrate preparation method according to embodiment 1 of the present invention;
fig. 6 to 7 are schematic structural diagrams obtained in steps of the substrate preparation method provided in embodiment 2 of the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Currently, the mainstream SOI substrate manufacturing technology includes: silicon bonded and reverse side etched BESOI (Bonding-Etchback SOI), SIMOX (Separation by Implanted Oxygen) with Oxygen implant isolation, and Smart Cut SOI with Bonding and implant combined. However, the manufacturing cost of the SOI substrate is expensive, and the stress control of the top silicon layer is difficult, so that the application scenarios of the SOI technology are limited.
FDSOI is taken as an outstanding representative of an SOI system, the thickness of a buried oxide layer (BOX) and the thickness of top silicon of the FDSOI are both thinner, the parasitic capacitance is smaller, the speed is faster, the power consumption is lower, the radiation resistance is extremely strong, and the FDSOI is particularly suitable for being used as a channel material of a high-mobility transistor. Compared with FinFET, the FDSOI technology can effectively inhibit the pulse current interference of the substrate, reduce the occurrence of soft errors and is simpler in design and manufacture. Therefore, increasing the amount of strain in the top Si layer, simplifying the FD (SOI) substrate manufacturing process, and reducing the manufacturing cost of the (FD) SOI substrate are important research contents for realizing a high-performance field effect transistor.
Therefore, the invention provides a preparation method of a substrate structure on silicon nitride, which comprises the following steps.
Firstly, providing a first substrate; the substrate may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as but not limited to bulk silicon (bulk silicon), silicon carbide, germanium, silicon germanium, gallium arsenide, sapphire, etc. Among the above various typical substrates, the silicon substrate has better compatibility, low cost and compatibility with the existing process equipment.
Then forming a first dielectric layer on the first substrate, wherein the thickness can be controlled to be 10-500 nm; the first dielectric layer serves as a buffer layer on the one hand and serves as an insulating layer on the other hand, and silicon oxide, aluminum oxide, oxynitride or the like, preferably silicon oxide, can be used, and the forming means includes but is not limited to thermal oxidation, selective epitaxy, LPCVD, ALD, RTCVD, PECVD or the like.
And forming a SiNx layer on the first dielectric layer, wherein the thickness of the SiNx layer can be controlled to be 100-500 nm. The nitrogen and silicon atoms may be in any molar ratio, x may take the value of 0< -x < -1.33, and the forming means includes, but is not limited to, selective epitaxy, LPCVD, ALD, RTCVD, or PECVD and the like.
Etching the SiNx layer to form a plurality of grooves; the size, distribution and the like of the grooves are generally determined according to the strain requirement, so that the required mask plate is determined for etching. On the other hand, in order to improve the quality of the substrate, the first dielectric layer or the etchant used for etching is preferably a material which enables the etching selectivity ratio of the SiNx layer to the first dielectric layer to be high.
And forming a second dielectric layer covering the SiNx layer and filling the groove. The second dielectric layer may be silicon oxide, aluminum oxide, oxynitride, or the like, preferably silicon oxide, formed by means including, but not limited to, selective epitaxy, LPCVD, ALD, RTCVD, PECVD, or the like, preferably selective epitaxy.
And carrying out flattening treatment on the surface of the second medium layer to obtain the insulated substrate. The surface of the second dielectric layer can be subjected to planarization treatment by adopting the following method: firstly, grinding and polishing or dry etching, TMAH corrosion and then chemical mechanical polishing treatment; or only a chemical mechanical polishing process.
The substrate thus insulated is subjected to any one of the following processes:
depositing a semiconductor material on the second dielectric layer in a first mode; the mode is a non-bonding mode, so that the method is simpler and the quality is more controllable. After deposition, surface planarization treatment such as CMP can be carried out to make the thickness reach 5-100 nm.
Bonding the insulated substrate with a second substrate with a third dielectric layer formed on the upper surface, wherein the bonding surface is the third dielectric layer and the second dielectric layer; and then optionally thinning the second substrate to reach the thickness of 5-100 nm. This manner of linkage may increase the regulation of the corresponding variable. The third dielectric layer may be made of silicon oxide, aluminum oxide, or oxynitride, preferably aluminum oxide, and the forming method thereof includes, but is not limited to, LPCVD, ALD, RTCVD, or PECVD. The bonding means is fusion bonding, for example, high temperature wax, high temperature glue, etc.
And obtaining the final substrate structure on the silicon nitride by adopting one of the two ways. The second substrate or the semiconductor material is used as a semiconductor layer of the top layer manufacturing device, and can be one of Si, ge, siGe, geSn, gaAs, inGaAs and InAs.
According to the method, the strain quantity of the top semiconductor material or the transferred second substrate can be regulated and controlled through the stacking of the multiple dielectric layers and the SiNx layer and the distribution of the grooves in the SiNx layer, so that the mobility and other electrical characteristics of a device prepared by using the substrate are improved.
In addition, the conventional Smart-cut first step is to oxidize a wafer and form SiO with a constant thickness on the wafer surface 2 . The second step is to implant hydrogen ions to a fixed depth of the wafer by using an ion implantation technique. The third step is to bond another wafer to the oxide wafer. And fourthly, forming bubbles by hydrogen ions by using a low-temperature thermal annealing technology, and stripping a part of the silicon wafer. And then the bonding strength is increased by using a high-temperature thermal annealing technology. The fifth step is to planarize the silicon surface. The technical process is very complicated, and the application of the SOI is restricted. Compared with Smart-cut technology, the preparation method of the invention has simpler process and obviously reduced manufacturing cost.
The following describes embodiments in terms of fabrication of an SOI substrate.
Example 1
Process for manufacturing SOI substrate in non-bonding mode
In the first step, 10-500nm SiO is formed on a silicon substrate 101 by means of thermal oxygen 2 Layer 102.
Second, siO is formed by thermal oxidation 2 A 100-500nm SiNx layer 103 is formed on layer 102 as shown in fig. 1.
And thirdly, etching the SiNx layer 103 to form a plurality of grooves 104, as shown in FIG. 2.
Step four, selective epitaxial formation of SiO 2 Layer 105, covering the SiNx layer 103 and filling the trench, as shown in fig. 3.
Fifthly, corroding excessive SiO on the top (bulge) by adopting a grinding and polishing (Grading) or Dry etching (Dry etch) and TMAH (mechanical etch) mode 2 Layer and finally the substrate surface roughness is reduced by Chemical Mechanical Polishing (CMP) resulting in an acceptor substrate as shown in figure 4.
Sixth, a silicon layer 106 (5-100 nm) of a target thickness is formed directly on the acceptor substrate, and the surface roughness is reduced by CMP, as shown in fig. 5.
Example 2
Manufacturing process of SOI substrate in bonding mode
An acceptor substrate was obtained in the same manner as in the first to fifth steps of example 1.
Meanwhile, another Si substrate 201 is provided as a starting material, and Al is formed on the Si substrate 201 by ALD method 2 O 3 Layer 202, which serves as a donor substrate, is shown in fig. 6.
Melting and bonding the acceptor substrate shown in fig. 5 and the donor substrate, and then etching most of the top Si substrate by using a polishing (Grading) or Dry etching (Dry etch) manner and a TMAH manner as shown in fig. 7; finally, a silicon layer (5-100 nm) with the target thickness is realized by adopting a CMP mode;
the two embodiments only exemplify the substrate structure with the top layer being silicon, but this does not limit the application of the present invention, and the top layer silicon may be replaced by Ge, siGe, geSn, gaAs, inGaAs, inAs, etc. The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A method for preparing a substrate structure on silicon nitride is characterized by comprising the following steps:
providing a first substrate;
forming a first dielectric layer on the first substrate;
forming a SiNx layer on the first dielectric layer;
etching the SiNx layer to form a plurality of grooves;
forming a second dielectric layer covering the SiNx layer and filling the groove;
carrying out flattening treatment on the surface of the second dielectric layer to obtain an insulated substrate;
and (c) subjecting the insulated substrate to any one of the following processes:
depositing a semiconductor material on the second dielectric layer in a first mode;
bonding the insulated substrate with a second substrate with a third dielectric layer formed on the upper surface, wherein the bonding surface is the third dielectric layer and the second dielectric layer; the second substrate is then optionally thinned.
2. The method according to claim 1, wherein the first substrate is a silicon substrate, and the first dielectric layer is preferably silicon oxide and is formed by a thermal oxidation method.
3. The method of claim 1, wherein the bonding means is fusion bonding.
4. The method according to claim 1, wherein the planarization treatment is performed on the surface of the second dielectric layer by using the following method:
firstly grinding and polishing or dry etching, TMAH corrosion and then chemical mechanical polishing treatment.
5. A substrate structure on silicon nitride obtained by the production method as claimed in claim 1 or 2 or 3.
6. The substrate structure on silicon nitride according to claim 5, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer each independently employ at least one of silicon oxide and aluminum oxide.
7. The substrate structure on silicon nitride of claim 6, wherein the first dielectric layer is silicon oxide, the second dielectric layer is silicon oxide, and the third dielectric layer is aluminum oxide.
8. The substrate structure on silicon nitride according to claim 6, wherein the thickness of said SiNx layer is up to 100-500 nm;
and/or the presence of a gas in the gas,
the thickness of the first dielectric layer reaches 10-500 nm;
and/or the presence of a gas in the gas,
the thickness of the thinned semiconductor material or the second substrate reaches 5-100 nm.
9. The substrate structure on silicon nitride according to claim 6, wherein the first substrate is a silicon substrate.
10. The substrate structure on silicon nitride according to any of claims 6-9, wherein the second substrate and the semiconductor material are one of Si, ge, siGe, geSn, gaAs, inGaAs, inAs.
CN202210821047.9A 2022-07-13 2022-07-13 Substrate structure on silicon nitride and preparation method thereof Pending CN115172257A (en)

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