CN115171578A - Array substrate, display panel and driving chip - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a driving chip, wherein the array substrate comprises a chip binding area, the chip binding area is used for being connected with the driving chip of the display panel, the chip binding area is provided with signal terminals, a plurality of supporting pads and a test signal line, and the signal terminals are used for being connected with the signal terminals of the driving chip so as to carry out signal transmission; the supporting pads are used for supporting the driving chip; the test signal line is electrically connected with at least one supporting pad, and the supporting pad is electrically connected with a circuit to be tested so as to transmit the test signal to the circuit to be tested through the supporting pad. Through the mode, the utilization rate of the wiring space of the array substrate/the driving chip can be improved.

Description

Array substrate, display panel and driving chip

Technical Field

The invention relates to the technical field of photoelectric display, in particular to an array substrate, a display panel and a driving chip.

Background

COP (Chip On Panel) is a brand-new screen body packaging process, and by integrating a driving Chip of a screen body On a flexible printed circuit board made of a flexible material and then bending the driving Chip to the lower part of a screen, a frame can be further reduced, the screen occupation ratio can be improved, and the requirements of being lighter and thinner and narrower in frame can be met. In the technology, when the driving chip is packaged, the chip binding area generally needs to be provided with a plurality of convex blocks to support the driving chip, so that the driving chip is prevented from being damaged due to uneven stress when the driving chip is bound with the substrate, the reasonable layout of the internal circuit of the driving chip/substrate is restrained by the arrangement mode of the existing convex blocks, and the upgrading and the improvement of the subsequent structure of the driving chip/substrate are not facilitated.

Disclosure of Invention

The invention mainly solves the technical problem of providing an array substrate, a display panel and a driving chip, which can improve the utilization rate of the wiring space of the array substrate/the driving chip.

In order to solve the technical problems, the invention adopts a technical scheme that: the array substrate comprises a chip binding area, wherein the chip binding area is used for being connected with a driving chip of a display panel and provided with signal terminals, a plurality of supporting pads and test signal lines, and the signal terminals are used for being electrically connected with the signal terminals of the driving chip so as to carry out signal transmission; the supporting pad is used for supporting the driving chip; the test signal line is electrically connected with at least one supporting pad, and the supporting pad is electrically connected with the circuit to be tested so as to transmit the test signal to the circuit to be tested through the supporting pad.

In one embodiment, the chip bonding area comprises a middle area and edge areas positioned at two ends of the middle area, and the signal terminals are arranged in the middle area; at least a portion of the support pad is disposed at the edge region.

In one embodiment, the chip bonding region is a rectangular region, the middle region is a rectangular region, and the edge region is located at a short side of the middle region.

In one embodiment, the middle region includes a central region and a peripheral region, the signal terminals are disposed in the peripheral region, a portion of the support pad is disposed in the central region, and the remaining portion is disposed in the peripheral region.

In one embodiment, the middle region is a rectangular region, and the peripheral region is located on a long side of the middle region.

In one embodiment, the test signal line is electrically connected to at least one support pad located at the edge region.

In an embodiment, the support pads are symmetrically distributed in the edge/central area.

In one embodiment, the upper surfaces of the signal terminals and the upper surface of the supporting pad are located on the same horizontal plane.

In one embodiment, the signal terminals include input terminals for connecting with the flexible circuit board to input signals to the driving chip, and output terminals for connecting with signal lines of the array substrate to transmit signals output by the driving chip to the array substrate.

In one embodiment, the array substrate comprises a substrate, and a first metal layer, a second metal layer and a third metal layer which are stacked on the substrate; the array substrate further comprises a test connecting terminal, the test connecting terminal is arranged on the third metal layer, and the test connecting terminal is electrically connected with the supporting pad and a circuit to be tested respectively.

In one embodiment, the circuit to be tested includes a driving circuit, a power supply circuit, a scanning circuit or a touch circuit of the array substrate.

In order to solve the technical problem, the invention adopts another technical scheme that: the utility model provides a display panel, display panel includes array substrate and driver chip, driver chip and array substrate bind to be connected, array substrate includes that the chip binds the district, the chip is bound the district and is provided with signal terminal, a plurality of supporting pads and test signal line, signal terminal is used for being connected with driver chip's signal terminal electricity, in order to carry out signal transmission, the supporting pad is used for supporting driver chip, the test signal line is connected with at least one supporting pad electricity, the supporting pad is connected with the circuit electricity that awaits measuring, in order to transmit test signal to the circuit that awaits measuring through the supporting pad.

In order to solve the technical problem, the invention adopts another technical scheme that: the driving chip comprises signal terminals, a plurality of supporting pads and a test signal line, wherein the signal terminals are used for being electrically connected with the signal terminals of the display panel so as to carry out signal transmission; the supporting pad is used for supporting the driving chip body; the test signal line is electrically connected with at least one supporting pad, and the supporting pad is used for being electrically connected with a circuit to be tested of the display panel so as to transmit the test signal to the circuit to be tested through the supporting pad.

The invention has the beneficial effects that: different from the situation of the prior art, the test signal wire is electrically connected with the supporting pad, so that the supporting pad can be reused as a connecting terminal of the test signal wire to test the display panel on the basis of supporting the driving chip, the use value of elements is fully developed, the space for arranging the test connecting terminal can be saved, the wiring space of the array substrate is further saved, the wiring space of the array substrate is fully utilized, and the display panel with narrower frame and better performance is favorably developed.

Drawings

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic circuit diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic plan view illustrating a bonding area of an array substrate chip according to an embodiment of the present disclosure;

fig. 5 is a schematic plan view illustrating a bonding region of an array substrate chip according to an embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure.

Detailed Description

In order to make the purpose, technical solution and effect of the present application clearer and clearer, the present application is further described in detail below with reference to the accompanying drawings and examples.

The application provides a display panel, display panel includes array substrate, sets up the luminescent device on array substrate to and bind the driver chip who is connected with array substrate. The display panel comprises a display area and a non-display area, the light-emitting device is arranged in the display area, and the driving chip is bound in the non-display area.

Referring to fig. 1 to 3, fig. 1 is a schematic top view of an array substrate according to an embodiment of the present disclosure, fig. 2 is a schematic circuit structure of the array substrate according to the embodiment of the present disclosure, and fig. 3 is a schematic cross-sectional structure of the array substrate according to the embodiment of the present disclosure. The drawings are only exemplary and show panel structures, and are not actual sizes, wherein the related structures are clearly shown, and the area of a display area in an actual panel is far larger than that of a non-display area. In this embodiment, the array substrate 100 includes a first region 101 and a second region 102, the first region 101 is a projection region of a light emitting device of the display panel on the array substrate 100, and the second region 102 is a peripheral region surrounding the first region 101. Or the orthographic projection of the first area 101 on the reference plane is coincident with the orthographic projection of the display area of the display panel on the reference plane, the orthographic projection of the second area 102 on the reference plane is coincident with the orthographic projection of the non-display area of the display panel on the reference plane, and the reference plane is a plane parallel to the array substrate. A plurality of pixel circuits are disposed in the first region 101 of the array substrate 100, and other electronic components such as signal lines, peripheral circuits, a bonded driving chip, and a flexible circuit board are disposed in the second region 102 of the array substrate 100.

Specifically, the array substrate includes a chip bonding region 103, the chip bonding region 103 is located in the second region 102 and is used for being bonded and connected with a driving chip 200 of the display panel, and the chip bonding region 103 is provided with a signal terminal 10, a supporting pad 20 and a test signal line 30.

The signal terminals 10 are used for being connected with signal terminals of the driving chip 200 to realize signal transmission between the display panel and the driving chip 200; the plurality of supporting pads 20 are used for supporting the driving chips 200 to prevent the driving chips 200 from being damaged due to uneven stress when being bonded with the array substrate 100; the test signal wire 30 is electrically connected to at least one support pad 20, and the support pad 20 is electrically connected to a circuit to be tested to deliver a test signal to the circuit to be tested through the support pad 20. Further, the test signal line 30 may receive a test signal from an external test device, and transmit the test signal to a circuit to be tested through the support pad 20, so as to test the circuit to be tested.

In the embodiment, the test signal line is electrically connected with the supporting pad, so that the supporting pad can be reused as a connecting terminal of the test signal line to test the display panel on the basis of supporting the driving chip, the use value of elements is fully developed, the space for arranging the test connecting terminal can be saved, and the wiring space of the array substrate is saved. In other words, through the arrangement, the wiring space of the array substrate is fully utilized, and the development of the display panel with a narrower frame and better performance is facilitated. In the circuit layout of the existing array substrate, the supporting pad is not electrically connected with other devices, only plays a supporting role, and seriously wastes the wiring space of the chip binding area.

Referring to fig. 4 and 5 in combination, fig. 4 is a schematic plane structure diagram of a chip bonding region of an array substrate in an embodiment of the present disclosure, and fig. 5 is a schematic plane structure diagram of the chip bonding region of the array substrate in the embodiment of the present disclosure. In this embodiment, the die-bonding region 103 includes a middle region 1031 and edge regions 1032 located at both ends of the middle region 1031, the signal terminals 10 are disposed at the middle region 1031, and the supporting pads 20 are disposed at the edge regions 1032. As shown in fig. 4 and 5, the chip bonding region 103 may be a rectangular region, and may be a middle region 1031 and an edge region 1032 obtained by dividing the chip bonding region 103 along the long side direction of the rectangle, where the middle region 1031 may also be a rectangular region, and the edge region 1032 is a region located at two short sides of the middle region 1031. At least a portion of support pad 20 is disposed in the edge region 1032. In some embodiments, the support pads 20 are disposed entirely at the edge regions 1032, or the support pads 20 are disposed at the edge regions 1032 and the center region 10311, respectively.

Further, the middle region 1031 includes a central region 10311 and a peripheral region 10312, the signal terminals 10 are disposed on the peripheral region 10312, and the support pad 20 includes a portion thereof disposed on the central region 10311 and the remaining portion thereof disposed on the edge region 1032. As shown in fig. 4 and 5, the intermediate region 1031 may be a rectangular region, the intermediate region 1031 may be divided into regions in the short side direction of the rectangle, and the peripheral region 10312 is a region located on both long sides of the central region 10311. In other words, the signal terminals 10 are disposed at both sides of the middle region 1031, the center region 10311 thereof is vacant, and the supporting pads 20 may be disposed at the vacant center region 10311 to further support the driving chip 200. In other words, the supporting pad 20 may be selectively disposed at a region without the signal terminal, and is intended to support the driving chip, so that the stress of the driving chip is equalized.

The support cushion 20 may be provided in both the edge region 1032 and the central region 10311, or may be provided only in the edge region 1032/central region 10311. Preferably, the support pads 20 are symmetrically distributed in the edge regions 1032/central regions 10311. Alternatively, if the support pads 20 are disposed on the edge regions 1032, the support pads 20 should be disposed on both sides of the edge regions 1032 at the same time, and the support pads 20 on both side edge regions 1032 are symmetrically distributed to ensure that the support forces on both sides are balanced. If set up supporting pad 20 in central zone 10311, supporting pad 20 evenly arranges in central zone 10311 to guarantee that the holding power is balanced mutually.

Further, the upper surfaces of the signal terminals 10 and the upper surfaces of the supporting pads 20 are located on the same horizontal plane. Or the height of the signal terminal 10 is the same as that of the supporting pad 20, so that the connection surface between the array substrate 100 and the driving chip 200 is flat, the driving chip 200 can be stressed in a balanced manner and is not easily crushed, and meanwhile, the connection terminals between the array substrate 100 and the driving chip 200 can be ensured not to shift and can be stably electrically connected.

Referring to fig. 5, the signal terminal 10 includes an input terminal 11 and an output terminal 12, the input terminal 11 is used for connecting with the flexible circuit board to input a signal to the driving chip 200, and the output terminal 12 is used for connecting with a signal line of the array substrate to transmit a signal output by the driving chip 200 to the array substrate. Specifically, some signals of the flexible circuit board may be input to the driving chip through the input terminal 11, the driving chip processes the signals, and the signals processed by the driving chip 200 may be input to the screen body through the output terminal 12.

In one embodiment, the test signal line may be used for Acceptance Testing (AT) of the array substrate. Specifically, a plurality of signal wires are intensively arranged on the array substrate, and the signal wires are thin and densely arranged, so that disconnection and disconnection are easy to occur, and the problems of short circuit, electrostatic interference and the like between adjacent circuits can be caused, and the problems can cause adverse effects on the display effect of the display panel, thereby causing yield loss of the display panel. Therefore, before the array substrate is used, it is necessary to perform an AT test, such as a lighting test, on the array substrate, and to detect a defective product in time, thereby preventing the defective product from flowing into the next process and causing a larger loss.

Referring to fig. 2, the array substrate includes a plurality of pixel circuits, a plurality of signal lines and a peripheral circuit. The pixel circuit is connected with the light emitting device of the display panel and used for driving the light emitting device to emit light. Each pixel circuit is connected to a corresponding one or more signal lines. The signal lines include a plurality of Scan lines (Scan) and a plurality of Data lines (Data), the plurality of Scan lines can extend in the same direction and are arranged at intervals; the plurality of data lines may extend in the same direction and be spaced apart from each other, and the extending direction of the scan line may cross the extending direction of the data lines. Each pixel circuit is connected to at least one scan line and one data line, the scan line may provide a switching signal to the pixel circuit, and the data line may provide a gray scale signal to the data circuit. The signal line may further include a power supply line including a VDD signal line and a VSS signal line for supplying a power supply signal to the pixel circuit. The peripheral circuit includes a timing controller, a data driving circuit, a scan driving circuit, and the like. The data driving circuit may supply data signals to the pixel circuits through a plurality of data lines DL. The scan driving circuit may supply scan signals to the pixel circuits through a plurality of scan lines G1. The array substrate may further include a touch signal line, a touch driving circuit, and the like, so that the display panel has a touch function. The signal circuits are all likely to have short circuit and open circuit problems and need to be tested, namely, the signal circuits can be circuits to be tested.

In one embodiment, the test signal line 30 may test a Gate Driver on Array (GOA) circuit, a Power supply (Power) circuit, a touch circuit, a scan circuit, etc. of the Array substrate, that is, the drive circuit, the Power supply circuit, the scan circuit, or the touch circuit of the Array substrate may be a circuit to be tested. Specifically, when testing, external test equipment is connected to the one end of test signal line 30 for receive the test signal from external test equipment, and the other end of test signal line 30 is connected to the circuit that awaits measuring through supporting pad 20, can use two supporting pads usually, forms the connecting loop, passes through the supporting pad with the test signal and transmits for the circuit that awaits measuring to whether there is the abnormity such as short circuit, open circuit in the test signal circuit. After the test, disconnection and test equipment's connection, the supporting pad is not connected with other structures electricity, can not form the connecting channel, and the back is accomplished in the test promptly, can not demolish the relation of connection of supporting pad and test signal line, can not influence yet and produce the property ability. Wherein, can be that supporting pad 20 is direct to be connected with the circuit that awaits measuring, also can be that supporting pad 20 passes through test connection terminal and be connected with the circuit that awaits measuring.

Referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure. The array substrate comprises a substrate and a plurality of metal layers which are stacked on the substrate, and each signal wiring, each pixel circuit and each driving circuit are respectively arranged on different metal layers. Specifically, the array substrate includes a substrate, a semiconductor layer, a first metal layer (M1), a second metal layer (M2), a third metal layer (M3), and an insulating layer between the metal layers, which are stacked on the substrate. The semiconductor layer includes active layers of a plurality of transistors; the first metal layer at least comprises gate electrodes of a plurality of transistors, a first capacitor plate of a storage capacitor, a scanning line, a control signal line and a light-emitting control line; the second metal layer at least comprises a second capacitor plate of the storage capacitor; the third metal layer at least includes source-drain electrodes of the transistors, power lines (e.g., VDD signal lines, VSS signal lines), data lines, reference voltage lines, and initialization voltage lines.

The manufacturing of the supporting pad 20 may reuse the process of the array substrate circuit area, that is, the supporting pad 20 may be formed by multiple metal layers. Specifically, when the first metal layer is formed, the supporting pad pattern is formed in the chip bonding region, and when the second metal layer and the third metal layer are formed, the supporting pad pattern is formed in the chip bonding region, so that the insulating layer and the metal layer are manufactured layer by layer, and the circuit region of the array substrate and the supporting pad 20 are formed.

In one embodiment, the circuit of each metal layer can be tested separately. That is, the circuit to be tested on each metal layer may be connected to the support pad, as shown in fig. 6, the circuit to be tested in the first metal layer may be connected to the support pad through a test signal line, and the test signal line may be formed when the circuit of the metal layer is manufactured.

In another embodiment, the circuits to be tested on each metal layer may be concentrated on a certain metal layer, for example, the circuits to be tested on each metal layer are only connected to the support pad at the third metal layer, all the circuits and circuits to be tested on each metal layer are led out to the third metal layer, for example, cross-line connection may be implemented in a via hole manner, and then the circuits are connected to the support pad at the third metal layer through the test connection terminal, thereby implementing the test on the circuits.

In an embodiment, the test signal line may be directly connected to the signal line/pad of the circuit to be tested, or the test connection terminal may be disposed on the metal layer, and the circuit or circuit to be tested is led out to the test connection terminal, and is connected to the support pad through the test connection terminal, and is further electrically connected to the test signal line to receive the test signal.

The number of the supporting pads 20 is plural, and correspondingly, there may be plural testing signal lines 30, which are respectively connected to different circuits to be tested, so as to test different circuits.

In the above embodiment, the test signal line is electrically connected with the supporting pad, so that the supporting pad can be reused as a connecting terminal of the test signal line to test the display panel on the basis of supporting the driving chip, the use value of elements is fully developed, the space for arranging the test connecting terminal can be saved, and the wiring space of the array substrate is saved. In other words, through the arrangement, the wiring space of the array substrate is fully utilized, and the development of the display panel with a narrower frame and better performance is facilitated.

Based on this, the present application also provides a driving chip, which includes signal terminals, a supporting pad and a test signal line, wherein the signal terminals are used for being connected with the signal terminals of the display panel to perform signal transmission; the plurality of supporting pads are used for supporting the driving chip body; the test signal line is electrically connected with at least one supporting pad, and the supporting pad is used for being electrically connected with a circuit to be tested of the display panel so as to transmit the test signal to the circuit to be tested through the supporting pad.

In this embodiment, the supporting pad of the driving chip can be reused as the test connection terminal to test the display panel besides the supporting function.

In this embodiment, the driver chip and the array substrate are bonded and packaged in a COP manner, and when the driver chip and the array substrate are connected, the interfaces are opposite; or supporting pad structure can set up on drive chip, also can set up on array substrate, also can be drive chip and array substrate on all set up the supporting pad, can be selective with partial supporting pad and test signal line connection in order to test display panel.

In one embodiment, the array substrate and the driving chip provided in the present application can be used as an array substrate and a driving chip of a display device such as a Light Emitting Diode (LED), an Organic Light Emitting Diode (OLED), a Micro-LED, a liquid crystal, etc., that is, the display panel disclosed in the present application can be used in various display modes, such as an OLED display, a quantum dot display, a Micro-LED display, a liquid crystal display, etc., but is not limited to the display modes.

The above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes performed by the content of the present specification and the attached drawings, or applied to other related technical fields directly or indirectly, are included in the scope of the present invention.

Claims (10)

1. The array substrate is characterized by comprising a chip binding area, wherein the chip binding area is used for being connected with a driving chip of a display panel, and the chip binding area is provided with:

the signal terminal is electrically connected with the signal terminal of the driving chip to carry out signal transmission;

a plurality of supporting pads for supporting the driving chip;

the test signal line is electrically connected with at least one support pad, and the support pad is electrically connected with a circuit to be tested so as to transmit a test signal to the circuit to be tested through the support pad.

2. The array substrate of claim 1,

the chip binding region comprises a middle region and edge regions positioned at two ends of the middle region, and the signal terminals are arranged in the middle region; at least a portion of the support pad is disposed in the edge region;

preferably, the chip bonding area is a rectangular area, the middle area is a rectangular area, and the edge area is located on the short side of the middle area.

3. The array substrate of claim 2,

the middle area comprises a central area and a peripheral area, the signal terminals are arranged in the peripheral area, one part of the supporting pad is arranged in the central area, and the rest part of the supporting pad is arranged in the peripheral area;

preferably, the middle area is a rectangular area, and the peripheral area is located on the long side of the middle area.

4. The array substrate of claim 2 or 3,

the test signal line is electrically connected to at least one of the support pads located at the edge region.

5. The array substrate of claim 2 or 3,

the support pads are symmetrically distributed in the edge area/the central area;

preferably, the upper surfaces of the signal terminals and the upper surface of the supporting pad are located on the same horizontal plane.

6. The array substrate of claim 1,

the signal terminals comprise input terminals and output terminals, the input terminals are used for being connected with the flexible circuit board so as to input signals to the driving chip, and the output terminals are used for being connected with signal lines of the array substrate so as to transmit the signals output by the driving chip to the array substrate.

7. The array substrate of any one of claims 1-3 and 6,

the array substrate comprises a substrate, a first metal layer, a second metal layer and a third metal layer, wherein the first metal layer, the second metal layer and the third metal layer are stacked on the substrate;

the array substrate further comprises a test connecting terminal, the test connecting terminal is arranged on the third metal layer, and the test connecting terminal is respectively electrically connected with the supporting pad and the circuit to be tested.

8. The array substrate of claim 7,

the circuit to be tested comprises a driving circuit, a power supply circuit, a scanning circuit or a touch circuit of the array substrate.

9. A display panel, comprising:

the array substrate comprises a chip binding area, wherein the chip binding area is provided with signal terminals, a plurality of supporting pads and test signal lines, the signal terminals are used for being electrically connected with the signal terminals of the driving chip so as to carry out signal transmission, the supporting pads are used for supporting the driving chip, the test signal lines are electrically connected with at least one supporting pad, and the supporting pads are electrically connected with a circuit to be tested so as to transmit test signals to the circuit to be tested through the supporting pads;

and the driving chip is bound and connected with the array substrate.

10. A driver chip, comprising:

signal terminals for electrically connecting with the signal terminals of the display panel to perform signal transmission;

a plurality of supporting pads for supporting the driving chip body;

the test signal line is electrically connected with at least one support pad, and the support pad is used for being electrically connected with a circuit to be tested of the display panel so as to transmit a test signal to the circuit to be tested through the support pad.

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