CN115168084A

CN115168084A - Apparatus, system, and method for processor authentication

Info

Publication number: CN115168084A
Application number: CN202210715844.9A
Authority: CN
Inventors: 张沁涛
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2022-10-11

Abstract

The embodiment of the application provides a device, a system and a method for processor verification, and relates to the technical field of computers. The device includes: the debugging information management logic circuit is used for receiving debugging information transmitted by a design to be verified, preprocessing the received debugging information and then transmitting the preprocessed debugging information, wherein the design to be verified is a processor core, and the debugging information comprises running state information of the processor core; the debugging information cache unit is used for receiving and storing debugging information sent by the debugging information management logic circuit; and the debugging information transmission circuit comprises a high-speed interface connected with the host, and is used for reading the debugging information from the debugging information cache unit and transmitting the read debugging information to the host through the high-speed interface. Because the debugging information comprises the state information of the processor in the running process, the state of the CPU in the running process can be recorded, and clues and basis are provided for analyzing the running state and positioning problems.

Description

Apparatus, system, and method for processor authentication

Technical Field

The present application relates to the field of computer technology, and more particularly, to an apparatus, system, and method for processor verification.

Background

An integrated circuit (ASIC) chip refers to an integrated circuit chip designed and manufactured according to the requirements of a specific user and the requirements of a specific electronic system. In the ASIC design flow, the time spent verifying and debugging accounts for about 70% of the total time. Verification is a very important link in chip design. In order to increase the speed of verification and the test coverage during functional verification, prototype verification is often used.

The verification work of a processor (CPU) can be divided into three parts, i.e., work on a Personal Computer (PC), work of a verification platform, and debugging work. The PC is responsible for generating and downloading configuration files, receiving and transmitting test excitation data and analyzing test results. The verification platform provides the environment and resources for the chip to work normally and sends the result back to the PC. The debugging work adopts a logic analyzer to observe key signals in the CPU, and the results can be uploaded to a PC through a serial port. However, since the CPU is complicated in operation, it is difficult to determine the cause of an error by these simple means. Therefore, a method is needed to record the operating status of the CPU and provide clues and bases for analyzing the operating status and locating problems.

Disclosure of Invention

The embodiment of the application provides a device, a system and a method for processor verification, and aims to solve at least one technical problem in the prior art.

According to a first aspect of embodiments herein, there is provided an apparatus for processor authentication, the apparatus comprising:

the debugging information management logic circuit is used for receiving debugging information transmitted by a design to be verified, preprocessing the received debugging information and then transmitting the preprocessed debugging information, wherein the design to be verified is a processor core, and the debugging information comprises running state information of the processor core;

the debugging information cache unit is used for receiving and storing the debugging information sent by the debugging information management logic circuit; and

and the debugging information transmission circuit comprises a high-speed interface connected with a host, and is used for reading the debugging information from the debugging information cache unit and transmitting the read debugging information to the host through the high-speed interface.

In one possible implementation, the debug information management logic is specifically configured to: and combining the received debugging information, the corresponding timestamp and the effective length of the debugging information into a preset format and then sending the preset format to the debugging information cache unit.

In another possible implementation manner, the debug information caching unit is further configured to send a first preset level to the debug information transmission circuit when the number of the stored debug information reaches a preset number;

the debugging information transmission circuit is specifically configured to, after receiving the first preset level, read the debugging information stored in the debugging information cache unit, encapsulate the read debugging information into a data frame, and transmit the data frame to the host through the high-speed interface.

In another possible implementation manner, the debug information caching unit is specifically configured to: storing the received debugging information into one of two storage units, wherein the rest storage space of the storage unit is enough to store the received debugging information, and if the rest storage spaces of the two storage units are not enough to store the received debugging information, generating a counter-pressure signal and transmitting the counter-pressure signal to the debugging information management logic circuit;

and the debugging information management logic circuit is further used for sending a pause signal to the processor core to pause the work of the processor core if the back pressure signal transmitted by the debugging information cache unit is received.

According to a second aspect of embodiments herein, there is provided a system for processor verification, the system comprising: a debug information management logic circuit, a debug information cache unit, a debug information transmission circuit and a host, wherein,

the debugging information management logic circuit is used for receiving debugging information transmitted by a design to be verified, preprocessing the received debugging information and then sending the preprocessed debugging information to the debugging information caching unit, wherein the design to be verified is a processor core, and the debugging information comprises running state information of a processor;

the debugging information cache unit is used for receiving and storing debugging information sent by the debugging information management logic circuit;

the debugging information transmission circuit comprises a high-speed interface connected with the host, and is used for reading debugging information from the debugging information cache unit and transmitting the read debugging information to the host through the high-speed interface;

and the host is used for receiving the debugging information sent by the debugging information transmission circuit and saving the received debugging information in a file form.

In another possible implementation, the host is specifically configured to: when the monitoring process receives the data frame, the occupancy of the memory space is checked, if the memory space is determined to be enough to store the received data frame, the received data frame is stored in the corresponding debugging information page in the memory, and the debugging information page is moved to the disk by the sub-process and stored in a file form.

In another possible implementation, the host is further configured to perform one or more of the following operations:

after the moving is finished, terminating the subprocess and clearing a corresponding debugging information page in the memory;

if the size of the file in the disk exceeds a preset warning value, deleting the file which is moved to the disk earliest;

if receiving the instruction of stopping receiving the data frame, moving the rest debugging information pages in the memory to the disk, and clearing the debugging information pages in the memory.

In another possible implementation, the host is further configured to: if the memory space is determined not to be enough to store the received data frame, sending a second preset level to the debugging information transmission circuit;

and the debugging information transmission circuit is also used for suspending the sending of the debugging information after receiving the second preset level.

According to a third aspect of embodiments of the present application, there is provided a method for verifying a processor, the method including:

the debugging information management logic circuit receives debugging information transmitted by the design to be verified, preprocesses the received debugging information and sends the preprocessed debugging information to the debugging information caching unit for storage, wherein the design to be verified is a processor core, and the debugging information comprises running state information of a processor;

the debugging information transmission circuit reads the debugging information from the debugging information cache unit and transmits the read debugging information to the host through the high-speed interface.

In one possible implementation, the method further includes:

and the host receives the debugging information sent by the debugging information transmission circuit and saves the received debugging information in a file form.

In another possible implementation manner, the sending, by the debug information management logic circuit, the received debug information to the debug information cache unit for storage after preprocessing, includes:

the debugging information management logic circuit combines the received debugging information, the corresponding timestamp and the effective length of the debugging information into a preset format and then sends the preset format to the debugging information cache unit for storage.

According to a fourth aspect of embodiments herein, there is provided a computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the authentication method of the processor shown in the third aspect.

The technical scheme provided by the embodiment of the application has the following beneficial effects:

the debugging information from the processor core is preprocessed through the debugging information management logic circuit and then sent to the debugging information cache unit in the system for storage, and the debugging information transmission circuit reads the debugging information from the debugging information cache unit and transmits the read debugging information to the host through the high-speed interface. Because the debugging information comprises the state information in the running process of the processor, the state in the running process of the CPU can be recorded, and clues and bases are provided for analyzing the running state and positioning problems.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.

Fig. 1 is a schematic structural diagram of an apparatus for processor verification according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a system for processor verification according to an embodiment of the present application;

FIG. 3 is a block diagram of a system for processor verification according to another embodiment of the present application;

fig. 4 is a flowchart illustrating a verification method for a processor according to an embodiment of the present application;

FIG. 5 is a flowchart illustrating a method for verifying a processor according to another embodiment of the present disclosure;

fig. 6 is a flowchart illustrating a method implemented by a host in an authentication method of a processor according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the embodiments set forth below in connection with the drawings are exemplary descriptions for explaining technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application are explained below by describing several exemplary embodiments. It should be noted that the following embodiments may be referred to, referred to or combined with each other, and the description of the same terms, similar features, similar implementation steps, etc. in different embodiments is not repeated.

The process of "verification," as referred to herein, includes applying test cases to a design-under-test (DUT) and comparing the results to expected results to determine whether the DUT is operating correctly.

The embodiment of the application provides an apparatus for processor verification, which comprises: the device comprises a debugging information management logic circuit, a debugging information cache unit and a debugging information transmission circuit, wherein the debugging information management logic circuit is used for receiving debugging information to be verified and designed for transmission, preprocessing the received debugging information and then transmitting the preprocessed debugging information to the debugging information cache unit. The to-be-verified processor is designed as a processor core, and the debugging information comprises running state information of the processor. And the debugging information cache unit is used for receiving and storing the debugging information sent by the debugging information management logic circuit. And the debugging information transmission circuit comprises a high-speed interface connected with the host, and is used for reading the debugging information from the debugging information cache unit and transmitting the read debugging information to the host through the high-speed interface.

In one possible implementation, the debug information management logic is specifically configured to: and combining the received debugging information, the corresponding timestamp and the effective length of the debugging information into a preset format and then sending the preset format to a debugging information cache unit.

In another possible implementation manner, the debug information cache unit is further configured to send a first preset level to the debug information transmission circuit when the number of the stored debug information reaches a preset number.

And the debugging information transmission circuit is specifically used for reading the debugging information stored in the debugging information cache unit after receiving the first preset level, packaging the read debugging information into a data frame and transmitting the data frame to the host through the high-speed interface.

In another possible implementation manner, the debug information caching unit is specifically configured to: and storing the received debugging information into one of the two storage units, wherein the residual storage space of the storage unit is enough to store the received debugging information, and if the residual storage spaces of the two storage units are not enough to store the received debugging information, generating a backpressure signal and transmitting the backpressure signal to the debugging information management logic circuit.

And the debugging information management logic circuit is also used for sending a pause signal to the processor core if the back pressure signal transmitted by the debugging information cache unit is received so as to pause the work of the processor core.

An embodiment of the present application further provides a system for processor verification, including: the debugging device comprises a debugging information management logic circuit, a debugging information cache unit, a debugging information transmission circuit and a host, wherein the debugging information management logic circuit is used for receiving debugging information to be verified and designed to be transmitted, preprocessing the received debugging information and then transmitting the preprocessed debugging information to the debugging information cache unit. The to-be-verified processor is designed as a processor core, and the debugging information comprises running state information of the processor.

And the debugging information cache unit is used for receiving and storing the debugging information sent by the debugging information management logic circuit.

And the debugging information transmission circuit comprises a high-speed interface connected with the host, and is used for reading the debugging information from the debugging information cache unit and transmitting the read debugging information to the host through the high-speed interface.

In another possible implementation manner, the debug information caching unit is further configured to send a first preset level to the debug information transmission circuit when the number of the stored debug information reaches a preset number.

and after the moving is finished, terminating the subprocess and clearing the corresponding debugging information page in the memory.

And if the size of the file in the disk exceeds the preset warning value, deleting the file which is moved to the disk at the earliest time.

If an instruction of stopping receiving the data frame is received, the rest debugging information pages in the memory are moved to a disk, and the debugging information pages in the memory are cleared.

In another possible implementation, the host is further configured to: and if the memory space is determined not to be enough to store the received data frame, sending a second preset level to the debugging information transmission circuit.

In another possible implementation manner, the debug information caching unit is specifically configured to: and storing the received debugging information into one of the two storage units, wherein the residual storage space of the storage unit is enough to store the received debugging information, and if the residual storage spaces of the two storage units are not enough to store the received debugging information, generating a counter-pressure signal and transmitting the counter-pressure signal to the debugging information management logic circuit.

And the debugging information management logic circuit is also used for sending a pause signal to the processor core to pause the work of the processor core if receiving the back pressure signal transmitted by the debugging information cache unit.

In the above embodiments of the present application, the debugging information includes, but is not limited to: one or more items of retired instruction address, instruction operation code, exception type, interrupt type, exception reason, interrupt reason, privilege mode and CPU status register in the running process of the processor.

Fig. 1 is a schematic structural diagram of an apparatus for processor verification according to an embodiment of the present disclosure. The apparatus 10 shown in fig. 1 comprises: debug information management logic 101, debug information cache unit 102, and debug information transfer circuitry 103. Wherein the DUT100 is designed to be verified as a processor CPU core.

And the debugging information management logic circuit 101 is configured to receive debugging information transmitted by the design to be verified 100, preprocess the received debugging information, and send the preprocessed debugging information to the debugging information cache unit 102, where the debugging information includes running state information of the processor.

And a debug information cache unit 102 for receiving and storing debug information sent by the debug information management logic circuit 101.

And a debug information transmission circuit 103 including a high-speed interface connected to the host, for reading the debug information from the debug information cache unit 102 and transmitting the read debug information to the host through the high-speed interface.

In this embodiment, the debug information from the processor core is preprocessed by the debug information management logic circuit and then sent to the debug information cache unit in the system for storage, and the debug information transmission circuit reads the debug information from the debug information cache unit and transmits the read debug information to the host through the high-speed interface. Because the debugging information comprises the state information of the processor in the running process, the device can record the state of the CPU in the running process, and clues and basis are provided for analyzing the running state and positioning problems.

In this embodiment, in order to ensure the correctness of transmission and facilitate the analysis and detection of transmission errors by software, the debug information management logic circuit 101 is specifically configured to: the received debug information, the corresponding timestamp, and the effective length of the debug information are combined into a preset format and then sent to the debug information cache unit 102.

That is, the debug information management logic 101 combines the debug information, the timestamp, and the effective length of the debug information into a fixed format for transmission. Specifically, the fixed format may be set in advance, for example: frame header + timestamp + debug information + effective length of debug information + frame check information.

It should be noted that, in this embodiment, the fixed format may be determined according to the type of the high-speed interface, and the effective length of the debug information may be determined according to the transmission efficiency of the system.

In some optional embodiments, the debug information cache unit 102 is further configured to send a first preset level to the debug information transmission circuit 103 when the amount of the stored debug information reaches a preset amount.

The debug information transmission circuit 103 is specifically configured to, after receiving the first preset level, read the debug information stored in the debug information cache unit, encapsulate the read debug information into a data frame, and transmit the data frame to the host through the high-speed interface.

That is, when the debug information cache unit 102 stores a certain amount of debug information (the amount may be set in advance according to the size of the storage space), the debug information transmission circuit 103 is notified to read. For example: the debug information cache unit 102 may transmit a high level to the debug information transmission circuit 103 to notify the debug information transmission circuit 103 to read the debug information stored in the debug information cache unit 102. After the debug information data is read from the storage unit of the debug information cache unit 102, the debug information transmission circuit 103 encapsulates the data into data frames and transmits the data frames to the high-speed interface.

In other optional embodiments, the debug information cache unit 102 is specifically configured to: and storing the received debugging information into one of the two storage units, wherein the remaining storage space of the storage unit is enough to store the received debugging information, and if the remaining storage space of the two storage units is not enough to store the received debugging information, generating a counter-pressure signal and transmitting the counter-pressure signal to the debugging information management logic circuit 101.

The debug information management logic 101 is further configured to send a halt signal to the processor core 100 if the back-pressure signal transmitted by the debug information cache unit is received, so as to halt the operation of the processor core 100.

That is, in order to ensure that data is not lost and efficiency is taken into consideration, the inside of the debug information cache unit 102 may be divided into 2 storage units, and after the debug information cache unit 102 receives the debug information, if there is enough storage space in one storage unit to store the debug information, the debug information is directly stored; otherwise, storing the data in another storage unit; if there is insufficient space in none of the 2 memory cells, a backpressure signal is generated and may be sent to debug information management logic 101. After receiving the backpressure signal, the debug information management logic circuit 101 sends a hash signal to the CPU core 100, and suspends the operation of the CPU core.

A system for processor verification provided by the present application is described in detail below with reference to fig. 2 and 3.

Fig. 2 is a schematic structural diagram of a system for processor verification according to an embodiment of the present disclosure. The system 20 shown in fig. 2 includes: a debug information management logic circuit 201, a debug information cache unit 202, a debug information transmission circuit 203, and a host 204. The DUT200 to be verified is designed to be a processor CPU core.

And the debugging information management logic circuit 201 is configured to receive debugging information transmitted by the design to be verified 200, preprocess the received debugging information, and send the preprocessed debugging information to the debugging information cache unit 202, where the debugging information includes running state information of the processor.

And a debug information cache unit 202, configured to receive and store the debug information sent by the debug information management logic 201.

The debug information transmission circuit 203 includes a high-speed interface connected to the host 204, and is configured to read the debug information from the debug information cache unit 202 and transmit the read debug information to the host 204 through the high-speed interface.

And a host 204 for receiving the debugging information transmitted by the debugging information transmission circuit 203 and saving the received debugging information in a file form.

In the embodiment, debugging information from a processor core is preprocessed by a debugging information management logic circuit in the system and then sent to a debugging information cache unit in the system for storage, a debugging information transmission circuit in the system reads the debugging information from the debugging information cache unit and transmits the read debugging information to a host through a high-speed interface, and the host receives the debugging information and then stores the debugging information in a file form. Because the debugging information comprises the state information of the processor in the running process, the system can record the state of the CPU in the running process, and clues and basis are provided for analyzing the running state and positioning problems.

Fig. 3 is a schematic structural diagram of a verification system for processor verification according to another embodiment of the present application. The system shown in fig. 3 comprises a hardware part (HW part in the figure) and a software part (SW part in the figure). The hardware part is realized on a Field Programmable Gate Array (FPGA) verification platform, and includes: the CPU core 200, the Debug information management logic circuit 21, the Debug information cache unit 22, the Debug information transmission circuit 23, and the timestamp generation circuit 24.

The CPU core 200 is designed to be verified, and in order to facilitate monitoring of the test process or tracing and locating problems occurring in the test process, debugging (Debug) information including CPU running state information needs to be sent from the CPU core 200 to the Debug information management logic circuit 21. The debug information includes, but is not limited to, retired instruction address, instruction opcode, exception type, interrupt type, exception/interrupt reason and privilege mode, CPI status register, etc. during the running of the CPU.

Meanwhile, for convenience of practical application, the CPU may determine whether to enable the debug information uploading function or to Start the output of debug information once by using a control signal such as an enable signal enable. The Debug information management logic 21 may temporarily stop the operation of the CPU core 200 by the suspend signal halt until the suspend signal is deasserted.

The CPU core 200 transmits Debug information to the Debug information management logic circuit 21, and the Debug information management logic circuit 21 associates the received Debug information with the time stamp one by one. And calculating the effective length of the debug information received this time. The three kinds of information (debug information, timestamp and effective length of debug information) are combined into a fixed format and sent to the debug information cache unit 22.

In the embodiment, in order to ensure the correctness of transmission and facilitate the analysis and detection of transmission errors by software, the debug information, the timestamp and the effective length of the debug information are combined into a fixed format for transmission. Specifically, the fixed format may be set in advance, for example: frame header + timestamp + debug information + effective length of debug information + frame check information.

In some embodiments, the Debug information management logic 21 may further receive a backpressure signal sent by the Debug information buffering unit 22 (for example, when the backpressure signal is marked as high), and after receiving the backpressure signal, send a hash signal to the CPU core 200 to suspend its operation. It should be noted that the function of the Debug information management logic circuit 21 is configurable, and whether to enable the function may be selected according to actual situations.

The time stamp generating circuit 24 is configured to generate a time stamp and send the time stamp to the Debug information management logic circuit 21, so that the Debug information management logic circuit 21 associates the time stamp with the Debug information when receiving the Debug information.

The Debug information cache unit 22 is internally divided into 2 storage units (e.g. storage space 0 and storage space 1 in the figure) for storing Debug information. The Debug information cache unit 22 may adopt a block random access memory (block RAM) inside the FPGA, or may use an external memory unit, such as a Double Data Rate (DDR). After receiving the Debug information, the Debug information cache unit 22 directly stores the Debug information if there is enough storage space in the storage unit 0 to store the Debug information; otherwise, storing the data in the storage unit 1; if there is insufficient space in none of the 2 memory cells, a back voltage signal is generated. The backpressure signal may be sent to the Debug information management logic 21.

In this embodiment, the inside of the Debug information cache unit 22 is divided into 2 storage units, which is convenient for hardware implementation, such as a ping-pong algorithm, and can ensure that data is not lost and efficiency is also considered.

The Debug information cache unit 22 needs to update the occupied amount of the storage space every time of the read/write operation. The Debug information cache unit 22 also has a read/write operation control function of the storage unit. When a certain number of Debug information is stored (the number may be set in advance according to the size of the storage space), the Debug information transmission circuit 23 is notified to read. For example: the Debug information cache unit 22 may transmit a high level to the Debug information transmitting circuit 23 to notify the Debug information transmitting circuit 23 to read the Debug information stored in the Debug information cache unit 22.

After the Debug information data is read from the storage unit of the Debug information cache unit 22, the Debug information transmission circuit 23 encapsulates the data into data frames and transmits the data frames to a high-speed interface unit, such as a high-speed serial computer expansion bus (PCIe) or a Universal Serial Bus (USB).

In this embodiment, the amount of data read at a time depends on the efficiency of the transmission interface. Each debug information data is data in a fixed format, and the debug information data comprises debug information, a timestamp and the effective length of the debug information. Further, since the high-speed interface has a requirement in terms of timing, physical, electrical, and the like for receiving data, it is necessary to perform the data frame transfer to the high-speed interface in accordance with a standard requirement in terms of timing, physical, electrical, and the like.

The software part (SW) can be realized on a PC machine, and the specific realization process is as follows:

after initialization is completed, a monitoring process is established for receiving a data frame containing debug information; waiting for the hardware to upload the debug data frame to the host through a cable or an interface; checking the occupation condition of a hard memory, and if enough space exists, storing the received data frame into a debugging information page (debug info page) corresponding to the CPU memory; otherwise the hardware part HW is informed to suspend the sending of data frames.

It should be noted that, in this embodiment, the Debug information transmission circuit 23 may be notified to suspend the transmission of the data frame by transmitting a high level to the Debug information transmission circuit 23.

If the data frame is received completely, starting another 1 subprocess, and moving the debugging information page data in the memory to a disk; meanwhile, the monitoring process continues to receive debugging information data from the high-speed interface, and if new data comes and the hard memory has enough space, the debugging information data is saved in the memory again, and a new sub-process is started for moving the data in the memory to a disk and saving the data in a file form. After the disk is written, the sub-process is terminated and the corresponding debug information page in the memory is cleared. The host process also checks whether the size of the file stored in the disk exceeds a preset warning value, and if so, the earliest file is deleted. If receiving the instruction of stopping receiving the data frame, the residual debugging information page in the memory is moved to the disk, and the debugging information page in the memory is cleared.

In this embodiment, in order to avoid memory overflow, each time a data frame is monitored, the occupation condition of the hard memory needs to be checked first, and the received data frame is stored in the debug information page in the memory under the condition that the memory space is sufficient. Usually, every N data frames are stored in a debug information page, and in special cases, the last remaining one or M data frames are stored in a debug information page, where M is less than or equal to N. N is a positive integer greater than 1 and may be determined based on the transmission efficiency of the high-speed interface.

It should be noted that, in order to ensure that data is not lost, the size of the file stored in the disk cannot exceed the entire disk storage space. The guard value is set so that a file written earliest to the disk can be deleted if the guard value is exceeded. The alert value may set 50%, 60%, 65%, 70%, 75%, etc. of the maximum storage space of the disk.

That is to say, the embodiment of the present application provides a system that can be used to track the operating state of a CPU at a certain time and locate the cause of an error in the CPU prototype verification. The hardware part is responsible for collecting debugging information, packing the debugging information into a fixed format, caching the debugging information, packaging the debugging information into a data frame and transmitting the data frame. The software part is responsible for receiving data frames, caching and writing the data frames into a disk in a file form.

Fig. 4 is a flowchart illustrating a verification method for a processor according to an embodiment of the present disclosure. The method shown in fig. 4 may be applied to the apparatus or system for processor authentication shown in the above embodiments, and the method includes:

s301, the debugging information management logic circuit receives debugging information transmitted by the design to be verified, preprocesses the received debugging information and then sends the received debugging information to the debugging information cache unit for storage.

The to-be-verified processor is designed as a processor core, and the debugging information comprises running state information of the processor.

S302, the debugging information transmission circuit reads the debugging information from the debugging information cache unit and transmits the read debugging information to the host through the high-speed interface.

In the above embodiment, the debug information management logic circuit preprocesses the debug information from the processor core and sends the debug information to the debug information cache unit for storage, and the debug information transmission circuit reads the debug information from the debug information cache unit and transmits the read debug information to the host through the high-speed interface. Because the debugging information comprises the state information of the processor in the running process, the method can record the state of the CPU in the running process, and provides clues and basis for analyzing the running state and positioning problems.

Fig. 5 is a flowchart illustrating a verification method for a processor according to another embodiment of the present application. The method shown in fig. 5 may further include, on the basis of the method shown in fig. 4:

s303, the host receives the debugging information sent by the debugging information transmission circuit and saves the received debugging information in a file form.

In the above embodiment, the debug information management logic circuit preprocesses the debug information from the processor core and sends the debug information to the debug information cache unit for storage, the debug information transmission circuit reads the debug information from the debug information cache unit and transmits the read debug information to the host through the high-speed interface, and the host receives the debug information and stores the debug information in a file form. Because the debugging information comprises the state information of the processor in the running process, the method can record the state of the CPU in the running process, and provides clues and basis for analyzing the running state and positioning problems.

In some embodiments, the step of sending the received debug information to the debug information cache unit for storage after the debug information management logic circuit in S301 preprocesses the received debug information may specifically include:

Specifically, in this embodiment, in order to ensure the correctness of transmission and facilitate the analysis and detection of transmission errors by software, the debug information, the timestamp, and the effective length of the debug information are combined into a fixed format and then transmitted. Specifically, the fixed format may be set in advance, for example: frame header + timestamp + debug information + effective length of debug information + frame check information.

In other embodiments, the method may further include:

s304 (not shown), when the amount of the stored debug information reaches the preset amount, the debug information caching unit sends a first preset level to the debug information transmission circuit.

S302 may specifically include: and the debugging information transmission circuit reads the debugging information stored in the debugging information cache unit after receiving the first preset level, encapsulates the read debugging information into a data frame and transmits the data frame to the host through the high-speed interface.

Specifically, in this embodiment, if the number of pieces of debug information stored in the debug information cache unit reaches the preset number, a high level may be transmitted to the debug information transmission circuit, and the debug information transmission circuit reads the debug information stored in the debug information cache unit after receiving the high level, and encapsulates the read debug information into a data frame and transmits the data frame to the host through the high-speed interface. Since the high-speed interface has requirements on timing, physical, electrical and the like for receiving data, the debug information transmission circuit needs to perform the data frame transmission to the high-speed interface according to the standard requirements on timing, physical, electrical and the like.

In other embodiments, S303 may specifically include: when the host receives the data frame through the monitoring process, the occupancy of the memory space is checked, if the memory space is determined to be enough to store the received data frame, the received data frame is stored in the corresponding debugging information page in the memory, and the debugging information page is moved to the disk by the sub-process and stored in a file form.

In another alternative, the method can further comprise the following steps:

if the host determines that the memory space is not enough to store the received data frame, sending a second preset level to the debugging information transmission circuit; and after receiving the second preset level, the debugging information transmission circuit suspends the sending of the debugging information.

Specifically, in this embodiment, if the host determines that the memory space is not sufficient to store the received data frame, a high level may be sent to the debug information transmission circuit, and the debug information transmission circuit may suspend sending the debug information after receiving the high level.

That is to say, in the above embodiment, in order to avoid memory overflow, each time a data frame is monitored, the occupation condition of the hard memory needs to be checked first, and when the memory space is sufficient, the received data frame is stored to the debug information page in the memory, and when the memory space is insufficient, the hardware is notified to suspend sending.

In other embodiments, the method further comprises:

s305 (not shown in the figure), the debug information caching unit stores the received debug information into one of the two storage units included in the debug information caching unit, where the remaining storage space of the storage unit is enough to store the received debug information, and if the remaining storage space of the two storage units is not enough to store the received debug information, a backpressure signal is generated and transmitted to the debug information management logic circuit;

s306 (not shown), the debug information management logic circuit sends a halt signal to the processor core to halt the operation of the processor core if receiving the back-pressure signal transmitted by the debug information cache unit.

Specifically, in this embodiment, the inside of the Debug information cache unit is divided into 2 storage units, which is convenient for hardware implementation, such as a ping-pong algorithm, so that it can be ensured that data is not lost and efficiency is also considered.

In other embodiments, the method further comprises:

s307 (not shown), the host performs one or more of the following operations:

after the moving is finished, stopping the subprocess and clearing the corresponding debugging information page in the memory;

if the size of the file in the disk exceeds a preset warning value, deleting the file which is moved to the disk at the earliest time;

In the above embodiments, the debug information is not limited to: one or more items of retired instruction addresses, instruction operation codes, exception types, interrupt types, exception reasons, interrupt reasons, privilege modes and CPU state registers in the running process of the processor.

Fig. 6 is a flowchart illustrating a method for verifying a processor, which is implemented by a host according to an embodiment of the present application. The method shown in fig. 6 includes:

s40, after the initialization is completed, a monitoring process is established for receiving the data frame containing debug information.

S41, receiving a data frame which is uploaded by hardware through a cable or an interface and contains debug information.

S42, checking the occupation condition of the hard memory, and if the space is enough, storing the received data frame into a debug information page (debug info page) corresponding to the CPU memory; otherwise the HW is notified to suspend the sending of data frames.

S43, determining whether the frame data is received completely, if so, executing S44, otherwise, executing S41.

S44, starting 1 subprocess, and moving the debug information page in the memory to a disk.

S45, the monitoring process continues to receive the data frame containing debug information from the high-speed interface, if a new data frame is received and the hard memory has enough space, the new data frame is stored in the memory again, and a new sub-process is started to move the data in the memory to the disk.

S46, after the magnetic disk writing of one sub-process is finished, the sub-process is terminated and the corresponding debug information page in the memory is cleared.

S47, the main process checks whether the size of the file stored in the disk exceeds a preset warning value, and if so, the earliest file is deleted.

And S48, judging whether to stop receiving the data frame, if so, executing S49, and otherwise, executing S41.

S49, if an instruction of stopping receiving the data frame is received, moving the residual debug information page in the memory to a disk, and clearing the debug information page in the memory.

In this embodiment, in order to avoid memory overflow, each time a data frame is monitored, the occupation condition of the hard memory needs to be checked first, and the received data frame is stored in the debug information page in the memory under the condition that the memory space is sufficient.

To sum up, in the verification method of the processor provided in the embodiment of the present application, the debug information from the processor core is preprocessed by the debug information management logic circuit and then sent to the debug information cache unit for storage, the debug information transmission circuit reads the debug information from the debug information cache unit and transmits the read debug information to the host through the high-speed interface, and the host receives the debug information and then stores the debug information in a file form. Because the debugging information comprises the state information of the processor in the running process, the method can record the state of the CPU in the running process, and clues and basis are provided for analyzing the running state and positioning problems.

It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functioning unit and sold or used as a stand-alone product, may be stored in a processor readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and other various media capable of storing program codes.

The embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, can implement the steps of the foregoing method embodiments and corresponding content. Compared with the prior art, the method can realize that: the debugging information from the processor core is preprocessed through the debugging information management logic circuit and then sent to the debugging information cache unit in the system for storage, the debugging information transmission circuit reads the debugging information from the debugging information cache unit and transmits the read debugging information to the host through the high-speed interface, and the host receives the debugging information and then stores the debugging information in a file form. Because the debugging information comprises the state information in the running process of the processor, the state in the running process of the CPU can be recorded, and clues and bases are provided for analyzing the running state and positioning problems.

The processor-readable storage medium can be any available medium or data storage device that can be accessed by a processor, including but not limited to magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid State Disks (SSDs)), among others.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk memory, optical memory, and the like) having computer-usable program code embodied therein.

It should be understood that, although each operation step is indicated by an arrow in the flowchart of the embodiment of the present application, the implementation order of the steps is not limited to the order indicated by the arrow. In some implementation scenarios of the embodiments of the present application, the implementation steps in the flowcharts may be performed in other sequences as needed, unless explicitly stated otherwise herein. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on an actual implementation scenario. Some or all of these sub-steps or stages may be performed at the same time, or each of these sub-steps or stages may be performed at different times, respectively. Under the scenario that the execution time is different, the execution sequence of the sub-steps or phases may be flexibly configured according to the requirement, which is not limited in the embodiment of the present application.

The foregoing is only an optional implementation manner of a part of implementation scenarios in this application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of this application are also within the protection scope of the embodiments of this application without departing from the technical idea of this application.

Claims

1. An apparatus for processor authentication, the apparatus comprising:

2. The apparatus of claim 1, wherein the debug information management logic circuitry is to: and combining the received debugging information, the corresponding timestamp and the effective length of the debugging information into a preset format and then sending the preset format to the debugging information cache unit.

3. The apparatus of claim 1, wherein the debug information cache unit is further configured to send a first preset level to the debug information transfer circuit when the amount of stored debug information reaches a preset amount;

4. The apparatus according to any of claims 1-3, wherein the debug information cache unit is specifically configured to: storing the received debugging information into one of two storage units, wherein the rest storage space of the storage unit is enough to store the received debugging information, and if the rest storage spaces of the two storage units are not enough to store the received debugging information, generating a counter-pressure signal and transmitting the counter-pressure signal to the debugging information management logic circuit;

5. A system for processor validation, the system comprising: a debug information management logic circuit, a debug information cache unit, a debug information transmission circuit and a host, wherein,

and the host is used for receiving the debugging information sent by the debugging information transmission circuit and storing the received debugging information in a file form.

6. The system of claim 5, wherein the debug information cache unit is further configured to send a first predetermined level to the debug information transfer circuitry when the amount of stored debug information reaches a predetermined amount;

7. The system of claim 6, wherein the host is specifically configured to: when the monitoring process receives the data frame, the occupancy of the memory space is checked, if the memory space is determined to be enough to store the received data frame, the received data frame is stored in the corresponding debugging information page in the memory, and the debugging information page is moved to the disk by the sub-process and stored in a file form.

8. The system of claim 7, wherein the host is further configured to perform one or more of the following operations:

9. The system of claim 7, wherein the host is further configured to: if the memory space is determined not to be enough to store the received data frame, sending a second preset level to the debugging information transmission circuit;

10. The system according to any of claims 5 to 9, wherein the debug information caching unit is specifically configured to: storing the received debugging information into one of two storage units, wherein the remaining storage space of the storage unit is enough to store the received debugging information, and if the remaining storage spaces of the two storage units are not enough to store the received debugging information, generating a counter-pressure signal and transmitting the counter-pressure signal to the debugging information management logic circuit;

11. A method of authenticating a processor, the method comprising:

the debugging information management logic circuit receives debugging information transmitted by a design to be verified, preprocesses the received debugging information and sends the received debugging information to a debugging information cache unit for storage, wherein the design to be verified is a processor core, and the debugging information comprises running state information of a processor;

12. The method of claim 11, further comprising:

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the authentication method of the processor of claim 11 or 12.