CN112579334B

CN112579334B - Signal recording method and device for processor based on Ethernet

Info

Publication number: CN112579334B
Application number: CN202011461903.1A
Authority: CN
Inventors: 李小波; 刘志超
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-08
Filing date: 2020-12-08
Publication date: 2023-04-25
Anticipated expiration: 2040-12-08
Also published as: CN112579334A

Abstract

The present disclosure provides a method, apparatus, device and storage medium for recording signals for a processor based on ethernet. Wherein the method comprises the following steps: acquiring a record enabling signal, wherein the record enabling signal indicates recording of a signal to be observed in the processor; and responding to the record enabling signal, recording data of a plurality of signals to be observed in the processor, and transmitting data of at least one signal in the plurality of signals to be observed through the Ethernet interface.

Description

Signal recording method and device for processor based on Ethernet

Technical Field

The present disclosure relates to processor debugging techniques, and more particularly, to an ethernet-based processor-oriented signal recording method, apparatus, device, and storage medium.

Background

In recent years, the rapid development of information processing applications such as artificial intelligence and big data processing makes the design of a processor more and more complex and the scale of the processor is continuously increasing, and how to debug a complex processor has become a difficult problem in processor verification. While debugging processes of complex processors often require acquisition of execution sequences (e.g., program count pointer values) of multiple programs or threads, processor internal signals, registers, bus transactions, and states, etc. to locate software and hardware problems of the processor, for general system level debugging, the process often requires tens of hours, and more often requires days or even longer, so how to record the execution sequences of the processor and the processor internal bus signals in real time to improve the debugging efficiency has become a difficulty in the processor debugging technology. The current debugging technology of the processor cannot record the track of the execution program of the processor in real time and for a long time, and is difficult to meet the debugging requirement of a complex processor.

Therefore, there is a need for a method that can record signals during processor debugging in real time, over time, and efficiently.

Disclosure of Invention

In order to solve the above problems, the present disclosure realizes real-time, large-capacity, long-time and efficient recording of debug signal information inside a processor by transmitting recorded data of a signal to be observed back to a host in real time via an ethernet interface and completing offline parsing by the host.

The embodiment of the disclosure provides a signal recording method facing a processor based on Ethernet, which comprises the following steps: acquiring a record enabling signal, wherein the record enabling signal indicates recording of a signal to be observed in the processor; and responding to the record enabling signal, recording data of a plurality of signals to be observed in the processor, and transmitting data of at least one signal in the plurality of signals to be observed through an Ethernet interface.

According to an embodiment of the present disclosure, the signal recording method further includes: in response to the recording enable signal, a transmission data source of the Ethernet interface is set as recorded data of a plurality of signals to be observed inside the processor.

According to an embodiment of the present disclosure, the signal recording method further includes: and responding to the record enabling signal, resetting the Ethernet interface before setting the transmission data source of the Ethernet interface, and resetting each module of the processor after finishing the setting of the transmission data source of the Ethernet interface.

According to an embodiment of the present disclosure, the recording data of the plurality of signals to be observed inside the processor and transmitting data of at least one signal of the plurality of signals to be observed through an ethernet interface includes: determining a plurality of signals to be observed inside the processor; sampling the plurality of signals to be observed, and selecting data of at least one signal from the sampled data of the plurality of signals to be observed; and transmitting data of the selected at least one signal through the ethernet interface.

According to an embodiment of the present disclosure, the transmitting the data of the selected at least one signal through the ethernet interface further includes: adding an Ethernet packet header and an integrity check code to the data of the selected at least one signal to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and transmitting the Ethernet data packet through an Ethernet interface.

According to an embodiment of the disclosure, the determining the plurality of signals to be observed inside the processor further includes: acquiring an observation indication signal, wherein the observation indication signal indicates a plurality of signals to be observed in the processor; and determining the plurality of signals to be observed inside the processor based on the observation indication signal.

According to an embodiment of the present disclosure, the signal recording method further includes: acquiring a record disabling signal, wherein the record disabling signal indicates that recording of a signal to be observed in the processor is stopped; and responding to the record disabling signal, stopping recording the signal to be observed in the processor, and setting the transmitting data source of the Ethernet interface as normal operation data.

According to an embodiment of the present disclosure, the signal to be observed includes at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence.

Embodiments of the present disclosure provide an ethernet-based processor-oriented signal recording apparatus, comprising: a signal receiving module configured to receive a recording enable signal indicating recording of a signal to be observed inside the processor; a signal recording module configured to perform data recording on a plurality of signals to be observed inside the processor in response to the recording enable signal; and an ethernet interface module configured to transmit data of at least one of the plurality of signals to be observed through an ethernet interface in response to the recording enable signal.

According to an embodiment of the present disclosure, the signal recording apparatus further includes: a signal selection module configured to: setting a transmission data source of the Ethernet interface module as recorded data of a plurality of signals to be observed inside the processor in response to the recording enable signal; and selecting data of at least one signal from the recorded data of the plurality of signals to be observed inside the processor.

According to an embodiment of the present disclosure, the signal recording apparatus further includes: and the reset control module is configured to respond to the record enabling signal, reset the Ethernet interface module before setting the transmission data source of the Ethernet interface module, and reset each module of the processor after the signal selection module completes the setting of the transmission data source of the Ethernet interface module.

According to an embodiment of the present disclosure, the signal recording module includes a first number of signal samplers and a first number of recording data registers, wherein each signal sampler is configured to sample one of the plurality of signals to be observed and store the obtained sampled data in the corresponding recording data register.

According to an embodiment of the present disclosure, wherein the record data register is an asynchronous first-in first-out register.

According to an embodiment of the disclosure, the ethernet interface module includes: a signal wrapper for adding an ethernet packet header and an integrity check code to data of at least one signal of the plurality of signals to be observed to generate an ethernet data packet, wherein the ethernet packet header includes a destination address, a source address, and a packet type; and the Ethernet interface is used for sending the Ethernet data packet through the Ethernet interface.

According to an embodiment of the disclosure, the signal receiving module is further configured to receive an observation indication signal indicating a plurality of signals to be observed inside the processor; wherein the signal recording module is further configured to determine the plurality of signals to be observed inside the processor based on the observation indication signal.

According to an embodiment of the disclosure, the signal receiving module is further configured to receive a recording disable signal, the recording disable signal indicating that recording of a signal to be observed inside the processor is stopped; wherein the signal recording module is further configured to stop recording a signal to be observed inside the processor in response to the recording disable signal; and the signal selection module is further configured to set a transmission data source of the ethernet interface module to normal operation data in response to the recording disable signal.

According to an embodiment of the present disclosure, wherein the operation mode of the signal recording apparatus includes a signal recording mode and a normal operation mode based on the operation state of the processor including a debug state and a normal state, wherein the recording enable signal is transmitted to the signal recording apparatus in response to the processor entering the debug state from the normal state, so that the signal recording apparatus enters the signal recording mode; and in response to the processor returning from the debug state to the normal state, sending the record disable signal to the signal recording device so that the signal recording device enters the normal operation mode.

Embodiments of the present disclosure provide an ethernet-based processor-oriented signal recording apparatus, comprising: a processor; and a memory having stored thereon computer executable instructions for implementing the method as described above when executed by the processor.

Embodiments of the present disclosure provide a computer readable storage medium having stored thereon computer executable instructions which, when executed by a processor, are for implementing a method as described above.

Embodiments of the present disclosure provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device performs the ethernet-based processor-oriented signal recording method according to the embodiments of the present disclosure.

The embodiment of the disclosure provides a signal recording method, device, equipment and storage medium based on Ethernet and facing a processor. The method provided by the embodiment of the disclosure records and packages the signals to be observed, the register and the like in the processor, then sends the data packet of the recorded signals to the host in real time through the Ethernet interface, and completes offline analysis on the host, thereby realizing real-time and long-time and large-capacity recording of the debugging signal information in the processor, greatly improving the efficiency and depth of the verification and debugging of the processor, and simultaneously, the method can be reused for realizing the real-time transmission and analysis of the related recorded signals of other functions when the processor is in a non-debugging state, and has wider applicability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are required to be used in the description of the embodiments will be briefly described below. It should be apparent that the drawings in the following description are only some exemplary embodiments of the present disclosure, and that other drawings may be obtained from these drawings by those having ordinary skill in the art without undue effort.

Fig. 1 illustrates a flowchart of a method 100 for ethernet-based processor-oriented signal recording in accordance with an embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of an ethernet packet according to an embodiment of the present disclosure.

Fig. 3 illustrates a flowchart of a method 300 of ethernet-based processor-oriented signal recording in accordance with an embodiment of the present disclosure.

Fig. 4a shows a schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.

Fig. 4b shows a specific internal schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.

Fig. 5 shows a flowchart of the operation of an ethernet-based processor-oriented signal recording apparatus according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of an ethernet-based processor-oriented signal recording device 600 in accordance with an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

In the present specification and drawings, substantially the same or similar steps and elements are denoted by the same or similar reference numerals, and repeated descriptions of the steps and elements will be omitted. Meanwhile, in the description of the present disclosure, the terms "first," "second," and the like are used merely to distinguish the descriptions, and are not to be construed as indicating or implying relative importance or order.

In the present specification and drawings, elements are described in the singular or plural form according to an embodiment. However, the singular and plural forms are properly selected for the proposed case only for convenience of explanation and are not intended to limit the present disclosure thereto. Accordingly, the singular may include the plural and the plural may include the singular unless the context clearly indicates otherwise.

Verification debugging of a complex processor often requires recording of program execution sequences of the processor, observation of internal signals of the processor, register values, bus transactions, status, and the like, and thus recording of program execution sequences or bus transactions, and the like in real time and in large capacity is very important for improving the efficiency of verification debugging.

A processor debugging technology can be based on an external logic analyzer, by connecting signals to be observed, registers and the like in a processor to a debugging bus and outputting the signals to pins, and then sampling and acquiring signal data, register values and the like in the processor for debugging and observation through the external logic analyzer. Because the limited memory capacity of the external logic analyzer leads to limited data volume which can be tracked during each operation, and because of the limitation of sampling width and depth, the external logic analyzer can only sample dozens to hundreds of signals, and the sampling depth is only thousands to millions of clock cycles, and the width and depth of data which can be observed simultaneously are limited, therefore, the method cannot record the track of the execution program of the processor in real time and for a long time, is difficult to meet the debugging requirements of various complex applications and software and hardware on the processor, and in addition, the method also needs to occupy debugging pins, and the bus width which can be observed simultaneously is also limited.

Therefore, the present disclosure provides a signal recording method and device for a processor based on ethernet, which can obtain internal key information of the processor in real time, for a long time and efficiently.

Embodiments of the present disclosure will be further described below with reference to the accompanying drawings.

As shown in fig. 1, first, at step 101, a recording enable signal may be acquired, which indicates recording of a signal to be observed inside a processor.

The obtained record enabling signal may indicate that the processor needs to be debugged currently, and in the process of debugging, a signal to be observed in the processor needs to be recorded. Wherein, according to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence. The signal to be observed may also be any other signal inside the processor that needs to be recorded, according to embodiments of the present disclosure.

Then, at step 102, in response to the recording enable signal, a plurality of signals to be observed inside the processor may be data recorded, and data of at least one of the plurality of signals to be observed may be transmitted through the ethernet interface.

According to an embodiment of the present disclosure, performing data recording on a plurality of signals to be observed inside a processor and transmitting data of at least one of the plurality of signals to be observed through an ethernet interface may include determining the plurality of signals to be observed inside the processor; sampling a plurality of signals to be observed, and selecting data of at least one signal from sampling data of the plurality of signals to be observed; and transmitting data of the selected at least one signal through the ethernet interface.

Wherein, according to an embodiment of the present disclosure, determining the plurality of signals to be observed inside the processor may further include acquiring an observation indication signal indicating the plurality of signals to be observed inside the processor, and determining the plurality of signals to be observed inside the processor based on the observation indication signal. By this observation instruction signal, it is possible to determine recording of a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed inside the processor. After a plurality of signals to be observed to be recorded are determined, the signals may be sampled respectively to obtain sampled data of the respective signals. Considering that the sample data may be transmitted in packets, the data of at least one signal to be currently transmitted may be selected among the sample data of the signals. For example, the plurality of signals to be observed may include debug signals A, B, C and D, which are all sampled and sampled data of each signal is obtained, respectively, and the sampled data of these signals may be transmitted in packets, wherein the data of a single transmission may include 64-bit data of debug signal a, 32-bit data of debug signal B, and 32-bit data of debug signal C.

According to an embodiment of the present disclosure, transmitting the data of the selected at least one signal through the ethernet interface may further include adding an ethernet packet header and an integrity check code to the data of the selected at least one signal to generate an ethernet data packet, wherein the ethernet packet header may include a destination address, a source address, a packet type; and sending the Ethernet data packet through the Ethernet interface. By adding various control information to the data of the selected at least one signal, a data packet conforming to the ethernet standard can be generated, which can be transmitted in real time via the ethernet interface to a host for parsing the data packet.

Specifically, fig. 2 shows a schematic diagram of an ethernet packet according to an embodiment of the present disclosure.

As shown in fig. 2, the ethernet packet may include a destination address field, a source address field, a type/length field, a data field, and a redundancy check field. The destination address field may indicate a transmission destination address of the data packet, the source address field may indicate a source address of the data packet, the type/length field may indicate an upper protocol after the data packet is transmitted to the destination address, the data field may include data to be transmitted, padding data, the upper protocol, and the like, and the redundancy check field may include an integrity check code for checking whether corruption occurs in the data transmission process. When the host receives the Ethernet data packet, firstly checking whether the target address of the data packet is matched with the address of the host, if so, continuing to check the redundancy check code field to determine whether the data packet is complete, removing auxiliary information such as address, redundancy check and the like in the data packet and extracting record signal data after confirming the completion, and sending the data to an upper protocol indicated by the type/length field for subsequent processing.

According to embodiments of the present disclosure, a host for offline parsing may receive such ethernet packets via its ethernet interface, capture and store relevant packets in a host file for subsequent parsing by a common packet capture tool (e.g., ethernet packet capture tool Wireshark), etc., so the signal recording method 100 may theoretically implement processor internal signal recording of approximately infinite duration and infinite depth.

In addition to the steps as described with reference to fig. 1, the ethernet-based processor-oriented signal recording method proposed by the present disclosure may also include other steps. Specifically, as a non-limiting example, fig. 3 shows a flowchart of a processor-oriented signal recording method 300 based on ethernet in accordance with an embodiment of the present disclosure. As shown in fig. 3, the signal recording method 300 may further include the following steps in addition to steps 101 and 102, based on the signal recording method 100.

In accordance with an embodiment of the present disclosure, at step 303, the ethernet interface may be reset in response to the record enable signal.

In response to the record enable signal, the ethernet interface may be started first to enter a state capable of transmitting data, so as to avoid a situation that data that needs to be transmitted by the module after other modules are started first cannot be transmitted after the data is transmitted to the ethernet interface.

In response to the record enable signal, the transmit data source of the ethernet interface may be set to the recorded data of the plurality of signals to be observed inside the processor at step 304, according to an embodiment of the present disclosure.

After the start-up of the ethernet interface is completed, a transmission data source thereof may be set, and the recorded data of the plurality of signals to be observed inside the processor is communicated to the ethernet interface.

In accordance with an embodiment of the present disclosure, at step 305, the modules of the processor may be reset after the setting of the transmit data source of the ethernet interface is completed in response to the record enable signal.

After completing the operations of steps 303 and 304, the preparation work for sending the record data required for debugging the processor is completed, at this time, each module in the processor may be reset, so that the processor starts to perform the debugging operation, and the data of the signal to be observed may normally flow into the ethernet interface.

In accordance with an embodiment of the present disclosure, at step 306, a record disable signal may be acquired that indicates that recording of a signal to be observed inside the processor is to be stopped.

The acquisition of the logging disable signal may indicate that the current processor has exited debugging and may therefore indicate that logging of signals to be observed within the processor is stopped.

According to an embodiment of the present disclosure, in response to the recording disable signal, the recording of the signal to be observed inside the processor is stopped and the transmission data source of the ethernet interface is set to normal operation data at step 307.

After the processor exits from the debug, the steps of the signal recording method 300 may be multiplexed with the real-time transfer of relevant signal recordings that implement other functions of the processor by setting the transmit data source of the ethernet interface to normal operating data.

As shown in fig. 4a, the ethernet-based processor-oriented signal recording apparatus 400 may include a signal receiving module 401, a signal recording module 402, and an ethernet interface module 403.

Wherein the signal receiving module 401 may be configured to receive a recording enable signal, which may indicate that a signal to be observed inside the processor is recorded. The receiving of the record enable signal may indicate that the processor needs to be debugged currently, and the record enable signal may indicate recording of a signal to be observed in the process of debugging the processor. According to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence. The signal to be observed may also be any other signal inside the processor that needs to be recorded, according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive an observation indication signal, which may indicate a plurality of signals to be observed inside the processor. According to an embodiment of the present disclosure, the observation instruction signal may instruct recording of a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed.

According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive a recording disable signal, which may indicate that recording of the signal to be observed inside the processor is stopped; wherein the signal recording module 402 may be configured to stop recording the signal to be observed inside the processor in response to the recording disable signal. Receipt of the record disable signal may indicate that the current processor has exited debug, and thus the record disable signal may indicate that the signal recording module 402 is no longer recording signals to be observed within the processor.

The signal recording module 402 may be configured to perform data recording of a plurality of signals to be observed inside the processor in response to the recording enable signal. According to an embodiment of the present disclosure, the signal recording module 402 may be further configured to determine a plurality of signals to be observed inside the processor based on the observation indication signal.

According to an embodiment of the present disclosure, the signal recording module 402 may determine to record a plurality of signals, such as a processor program count pointer, a processor internal bus, etc., among various signals to be observed based on the observation instruction signal, and then sample each of the determined plurality of signals to be observed, respectively, and store corresponding sampled data thereof.

The signal recording apparatus 400 may further include a signal selection module 404 and a reset control module 405 according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the signal selection module 404 may be configured to set a transmission data source of the ethernet interface module 403 to be the recorded data of the plurality of signals to be observed inside the processor in response to the recording enable signal, and select the data of at least one signal from the recorded data of the plurality of signals to be observed inside the processor. The signal selection module 404 may select a transmission data source required to implement a current function (e.g., a debug function) among a plurality of transmission data sources corresponding to signal records for implementing different functions of the processor, and select data of at least one signal to be currently recorded from the transmission data source to transmit to the ethernet interface module 403.

The ethernet interface module 403 may be configured to transmit data of at least one of the plurality of signals to be observed through the ethernet interface in response to the recording enable signal. The ethernet interface module 403 may generate a data packet according to the ethernet standard by adding various control information to the data of at least one signal of the plurality of signals to be observed, and transmit the data packet to a host for parsing the data packet in real time via the ethernet interface.

In accordance with an embodiment of the present disclosure, the signal selection module 404 may be further configured to set the transmission data source of the ethernet interface module 403 to normal operation data in response to the record disable signal. When the processor exits from the debug, the signal recording apparatus 400 can be multiplexed to realize real-time transmission of relevant signal records of other functions of the processor by setting the transmission data source of the ethernet interface module 403 to normal operation data.

According to an embodiment of the present disclosure, the reset control module 405 may be configured to, in response to the record enable signal, preferentially reset the ethernet interface module 403 before setting the transmission data source of the ethernet interface module 403, and reset the modules of the processor after the signal selection module 404 completes the setting of the transmission data source of the ethernet interface module 403.

In response to the record enable signal, the reset control module 405 may instruct the entire signal recording apparatus 400 to turn on the real-time debug record function, at which time the reset control module 405 may apply a modified reset control flow to temporarily inhibit resetting of the processor and other modules in the signal recording apparatus 400 and to preferably reset the ethernet interface module 403. After the reset of the ethernet interface module 403 and the setting of the transmission data source are completed, the transmission interface of the signal recording apparatus 400 is turned on, and at this time, each module of the processor may be reset, so that the data of the signal to be observed may normally flow into the ethernet interface module 403.

Specifically, as a non-limiting example, fig. 4b shows a specific internal schematic diagram of a processor-oriented signal recording device 400 based on ethernet according to an embodiment of the present disclosure.

As shown in fig. 4b, the ethernet-based processor-oriented signal recording apparatus 400 may include a signal receiving module 401, a signal recording module 402, and an ethernet interface module 403.

Wherein the signal receiving module 401 may be configured to receive a recording enable signal, which may indicate that a signal to be observed inside the processor is recorded. The receiving of the record enable signal may indicate that the processor needs to be debugged currently, and the record enable signal may indicate recording of a signal to be observed in the process of debugging the processor. According to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence.

According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive an observation indication signal, which may indicate a plurality of signals to be observed inside the processor; wherein the signal recording module 402 may be configured to determine a plurality of signals to be observed inside the processor based on the observation indication signal. According to an embodiment of the present disclosure, the signal recording apparatus 400 may determine to record a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed based on the observation instruction signal.

According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive a recording disable signal, which may indicate that recording of the signal to be observed inside the processor is stopped; wherein the signal recording module 402 may be further configured to stop recording the signal to be observed inside the processor in response to the recording disable signal. Receipt of the record disable signal may indicate that the current processor has exited debug, and thus the record disable signal may indicate that the signal recording module 402 is no longer recording signals to be observed within the processor.

The signal recording module 402 may be configured to perform data recording of a plurality of signals to be observed inside the processor in response to the recording enable signal.

According to an embodiment of the present disclosure, the signal recording module 402 may include a first number of signal samplers 412 and a first number of recording data registers 422, wherein each signal sampler 412 may be configured to sample one of a plurality of signals to be observed and store the obtained sampled data in a corresponding recording data register 422.

According to an embodiment of the present disclosure, the signal sampler 412 may locally sample the signal to be observed based on the clock domain in which the signal is located, and store its data in the corresponding log data register 422. According to an embodiment of the present disclosure, the log data register 422 may be an asynchronous first-in first-out register. The read and write operations of the log data register 422 may be performed separately according to the clock domains in which the read and write ends thereof are respectively located, and the log data register 422 may enable the signal sampler 412 based on the empty/full state thereof. According to an embodiment of the present disclosure, the data size storable by the record data register 422 may be 1536 bytes. According to the ethernet protocol, the length of the normal ethernet packet is not greater than 0x0600 (1536) bytes, so the record data register 422 can store the data of the signal to be observed with the size of the data size of the complete ethernet packet.

The ethernet interface module 403 may be configured to transmit data of at least one of the plurality of signals to be observed through the ethernet interface in response to the recording enable signal.

According to an embodiment of the present disclosure, the ethernet interface module 403 may include: a signal wrapper 413, configured to add an ethernet packet header and an integrity check code to data of at least one signal of the plurality of signals to be observed, so as to generate an ethernet data packet, where the ethernet packet header may include a destination address, a source address, and a packet type; and an ethernet interface 423 that may be used to transmit ethernet packets through the ethernet interface 423.

According to an embodiment of the present disclosure, in the ethernet packet transmitted by the signal recording apparatus 400 in response to the recording enable signal, the target address may be an address of a host for offline parsing, the source address may be an address of the signal recording apparatus 400, the data field may include data of at least one signal of the plurality of signals to be observed, and the redundancy check field may be an integrity check code such as a cyclic redundancy check code. When the host receives the Ethernet data packet, firstly checking whether the target address of the data packet is matched with the address of the host, if so, continuously checking the redundancy check field to determine whether the data packet is complete, removing auxiliary information such as address, redundancy check and the like in the data packet and extracting record signal data after confirming the completion, and sending the data to an upper protocol indicated by the type/length field for subsequent processing.

According to embodiments of the present disclosure, the ethernet packet may include a plurality of sampled data of the signal to be observed. For each of the plurality of data sources that the signal recording apparatus 400 may send, the data of each signal may be stored in a data packet according to a corresponding predetermined data source format, for example, the ethernet data packet corresponding to the current data source may include 128 bits of data, where the data of the debug signal a is located at [0:63 bit, data of debug signal B is located at [64:95 bits, the data of debug signal C is located at [96:127 bits. After being sent to the host, the host can analyze the data belonging to different signals in the data packet according to the predetermined data source format.

In accordance with an embodiment of the present disclosure, when a transmission data source of the ethernet interface module 403 is changed, the signal wrapper 413 may insert a gap packet between two data packets before and after the change to indicate the change of the transmission data source. The interval packet may be a packet of a special format (e.g., 0 xdelaef character filling), and in the subsequent parsing of the host, if it is determined that the content of the received packet is the same as the interval packet, it is determined that the transmission data source of the next packet will be changed, and a new predetermined data source format is applied thereto for parsing.

According to embodiments of the present disclosure, the ethernet interface 423 may include a media access control (Media Access Control, MAC) interface and a Physical Layer (PHY) interface. Wherein, after receiving the data packet from the signal wrapper 413, the MAC interface may split and repackage the data packet so that the data packet includes the destination MAC address and its own source MAC address, and then send it to the PHY interface. The PHY interface is primarily responsible for encoding and serializing data from the MAC interface and then converting the digital signal to an analog signal for transmission. According to an embodiment of the present disclosure, a host for offline parsing may receive ethernet packets from the signal recording apparatus 400 via its ethernet interface, capture related packets by a common packet capture tool (e.g., ethernet packet capture tool Wireshark) or the like and store them in a host file for subsequent parsing, so the signal recording apparatus 400 may theoretically implement processor internal signal recording of approximately infinite duration and infinite depth.

According to an embodiment of the present disclosure, the ethernet-based processor-oriented signal recording apparatus 400 may further include a signal selection module 404 and a reset control module 405.

According to an embodiment of the present disclosure, the signal selection module 404 may be configured to set a transmission data source of the ethernet interface module 403 to be the recorded data of the plurality of signals to be observed inside the processor in response to the recording enable signal, and select the data of at least one signal from the recorded data of the plurality of signals to be observed inside the processor.

According to an embodiment of the present disclosure, the signal selection module 404 may include a signal selector 414, and the signal selector 414 may select at least one signal to be observed from among a plurality of signals to be observed, gate its corresponding record data register 422 and fetch the sampled data of the signal therefrom, and write it into the signal wrapper 413 in the ethernet interface module 403.

In accordance with an embodiment of the present disclosure, the signal selection module 404 may utilize the signal selector 414 to select a transmission data source required to implement a current function (e.g., a debug function) among a plurality of transmission data sources corresponding to signal records for implementing different functions of a processor. Wherein for each data source that the signal recording apparatus 400 can transmit, the transmitting data source may comprise data of a plurality of signals to be recorded, and reading data from the data source may be in accordance with its corresponding predetermined data source format. For example, in a case where a debug function of the processor is to be implemented in response to the recording enable signal, the signal selector 414 may set the transmission data source of the ethernet interface module 403 as a debug signal data source (i.e., data of a plurality of signals to be observed), and sequentially read data of a part of signals from the data of the plurality of signals to be observed according to a predetermined data source format corresponding to the transmission data source, for example, sequentially strobe and fetch 64-bit data of the debug signal a, 32-bit data of the debug signal B, and 32-bit data of the debug signal C.

As described above, the signal recording apparatus 400 may select any signal to be recorded, such as a processor program count pointer, a processor internal bus, etc., record the sampled data in the corresponding record data register 422, and perform gating by the signal selector 414 to package the sampled data to generate a data packet conforming to the ethernet standard format, and transmit the data packet to the host in real time via the ethernet interface 423 to complete signal recording.

In accordance with an embodiment of the present disclosure, the signal selection module 404 may be further configured to set the transmission data source of the ethernet interface module 403 to normal operation data in response to the record disable signal. When the processor exits from the debug, the signal recording apparatus 400 may be multiplexed to implement real-time transfer of relevant signal records for other functions of the processor by setting the transmission data source of the ethernet interface module 403 to normal operation data.

According to an embodiment of the present disclosure, the operation mode of the signal recording apparatus 400 may include a signal recording mode and a normal operation mode based on the operation state of the processor, wherein in response to the processor entering the debug state from the normal state, a recording enable signal is transmitted to the signal recording apparatus 400 such that the signal recording apparatus 400 enters the signal recording mode; in response to the processor returning from the debug state to the normal state, a record disable signal is sent to signal recording device 400 causing signal recording device 400 to enter a normal operational mode. The operation mode of the signal recording apparatus 400 may be switched according to a change in the operation state of the current processor.

Fig. 5 shows a flowchart of the operation of an ethernet-based processor-oriented signal recording apparatus according to an embodiment of the present disclosure. In particular, considering that the operation mode of the signal recording apparatus can be switched between the signal recording mode and the normal operation mode accordingly as the operation state of the processor is changed between the debug state and the normal state, fig. 5 shows a process in which the operation mode of the signal recording apparatus is switched as the operation state of the processor is changed after the signal recording apparatus is started.

As shown in fig. 5, after the signal recording apparatus is started, it may be determined by the signal receiving module whether a recording enable signal is received (501).

If the processor is always running in a normal state, the signal receiving module does not receive the record enable signal, at this time, all the modules of the processor may be reset normally by the reset control module (502), so that all the modules of the processor are started (503) and the program is run normally (504). In this case, the signal recording device operates in a normal operation mode, and may be used to send ethernet packets of related signals that need to be recorded when the processor performs operations other than debugging tasks, where the sending data source of the ethernet interface module in the signal recording device is a normal data register.

According to embodiments of the present disclosure, a record enable signal may be sent to a signal receiving module in response to a processor entering a debug state from a normal state. After the signal receiving module determines that the recording enable signal is received, the signal recording apparatus may be instructed to enter a signal recording mode. First, a reset control flow setting is performed by the reset control module for each module in the signal recording apparatus and the processor (510), and then the ethernet interface module is reset preferentially according to the reset control flow (511). After the ethernet interface module is reset, the signal selection module may switch the transmitting data source of the ethernet interface module from the normal data register to the record data register in the signal record module (512). After the foregoing steps are completed, the preparation of the signal recording device for sending the debug record data is completed, at which time other modules of the device and each module in the processor may be reset (513), so that the processor starts to perform the debug operation (514), and the debug record data packet acquired by the device is sent to the host for parsing via the ethernet interface.

During debugging of the processor, it may be determined in real time by the signal receiving module whether a record disable signal is received (515).

According to embodiments of the present disclosure, a record disable signal may be sent to the signal receiving module in response to the processor returning from the debug state to the normal state. If the signal recording device is started, after the signal receiving module determines that the recording disabling signal is received, the signal recording device is instructed to switch from the signal recording mode to the normal operation mode, at this time, the transmitting data source of the ethernet interface module can be switched from the recording data register in the signal recording module to other common data registers (516), in the normal operation mode, the signal recording device can be multiplexed to the real-time transmission of the related signal records for realizing other functions of the processor, and after the switching of the transmitting data source is completed, the processor can resume the normal program operation (504).

As shown in fig. 6, an ethernet-based processor-oriented signal recording device 600 according to an embodiment of the present disclosure may include a processor 601 and a memory 602, which may be interconnected by a bus 603.

The processor 601 may perform various actions and processes in accordance with programs or code stored in the memory 602. In particular, the processor 601 may be an integrated circuit chip having signal processing capabilities. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. Various methods, steps, procedures, and logic blocks disclosed in embodiments of the present disclosure may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, and may be an X86 architecture or an ARM architecture or the like.

The memory 602 stores executable instructions that when executed by the processor 601 are for implementing an ethernet-based processor-oriented signal recording method in accordance with an embodiment of the present disclosure. The memory 602 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (ddr SDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memory of the methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, may implement an ethernet-based processor-oriented signal recording method according to embodiments of the present disclosure. Similarly, the computer readable storage medium in embodiments of the present disclosure may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. It should be noted that the memory of the methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Embodiments of the present disclosure also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device performs the ethernet-based processor-oriented signal recording method according to the embodiments of the present disclosure.

It is noted that the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises at least one executable instruction for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In general, the various example embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, firmware, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The exemplary embodiments of the present disclosure described in detail above are illustrative only and are not limiting. Those skilled in the art will understand that various modifications and combinations of these embodiments or features thereof may be made without departing from the principles and spirit of the disclosure, and such modifications should fall within the scope of the disclosure.

Claims

1. An ethernet-based processor-oriented signal recording method, comprising:

acquiring a record enabling signal, wherein the record enabling signal indicates recording of a signal to be observed in the processor; and

responding to the record enabling signal, recording data of a plurality of signals to be observed in the processor, and sending data of at least one signal in the plurality of signals to be observed in real time through an Ethernet interface, wherein the data of the at least one signal is used for debugging the processor;

setting a transmission data source of the Ethernet interface as recorded data of a plurality of signals to be observed inside the processor in response to the recording enable signal;

and responding to the record enabling signal, resetting the Ethernet interface before setting the transmission data source of the Ethernet interface, and resetting each module of the processor after finishing the setting of the transmission data source of the Ethernet interface.

2. The signal recording method of claim 1, wherein the data recording of the plurality of signals to be observed inside the processor and transmitting data of at least one of the plurality of signals to be observed through an ethernet interface comprises:

determining a plurality of signals to be observed inside the processor;

sampling the plurality of signals to be observed, and selecting data of at least one signal from the sampled data of the plurality of signals to be observed; and

the data of the selected at least one signal is transmitted through the ethernet interface.

3. The signal recording method of claim 2, wherein the transmitting data of the selected at least one signal through the ethernet interface further comprises:

adding an Ethernet packet header and an integrity check code to the data of the selected at least one signal to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and

and sending the Ethernet data packet through an Ethernet interface.

4. The signal recording method of claim 2, wherein the determining the plurality of signals to be observed inside the processor further comprises:

Acquiring an observation indication signal, wherein the observation indication signal indicates a plurality of signals to be observed in the processor; and

based on the observation indication signal, the plurality of signals to be observed inside the processor are determined.

5. The signal recording method of claim 1, further comprising:

acquiring a record disabling signal, wherein the record disabling signal indicates that recording of a signal to be observed in the processor is stopped; and

and responding to the record disabling signal, stopping recording the signal to be observed in the processor, and setting the transmitting data source of the Ethernet interface as normal operation data.

6. The signal recording method of claim 1, wherein the signal to be observed comprises at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence.

7. An ethernet-based processor-oriented signal recording apparatus, comprising:

a signal receiving module configured to receive a recording enable signal indicating recording of a signal to be observed inside the processor;

a signal recording module configured to record data of a plurality of signals to be observed inside the processor in response to the recording enable signal, wherein the data of at least one signal is used for debugging the processor;

An ethernet interface module configured to transmit data of at least one of the plurality of signals to be observed in real time through an ethernet interface in response to the recording enable signal; and

a signal selection module configured to set a transmission data source of the ethernet interface as recorded data of a plurality of signals to be observed inside the processor in response to the recording enable signal;

and the reset control module is configured to respond to the record enabling signal, reset the Ethernet interface module before setting the transmission data source of the Ethernet interface module, and reset each module of the processor after the signal selection module completes the setting of the transmission data source of the Ethernet interface module.

8. The signal recording device of claim 7, the signal selection module further configured to:

data of at least one signal is selected from the recorded data of a plurality of signals to be observed inside the processor.

9. The signal recording apparatus of claim 7, wherein the signal recording module comprises a first number of signal samplers and a first number of recording data registers, wherein each signal sampler is configured to sample one of the plurality of signals to be observed and store the obtained sampled data in the corresponding recording data register.

10. The signal recording apparatus of claim 9 wherein the record data register is an asynchronous first-in first-out register.

11. The signal recording apparatus of claim 7, wherein the ethernet interface module comprises:

a signal wrapper for adding an ethernet packet header and an integrity check code to data of at least one signal of the plurality of signals to be observed to generate an ethernet data packet, wherein the ethernet packet header includes a destination address, a source address, and a packet type; and

and the Ethernet interface is used for sending the Ethernet data packet through the Ethernet interface.

12. The signal recording apparatus of claim 7, wherein the signal receiving module is further configured to receive an observation indication signal indicating a plurality of signals to be observed inside the processor;

wherein the signal recording module is further configured to determine the plurality of signals to be observed inside the processor based on the observation indication signal.

13. The signal recording apparatus of claim 8, wherein the signal receiving module is further configured to receive a record disable signal indicating that recording of a signal to be observed inside the processor is stopped;

Wherein the signal recording module is further configured to stop recording a signal to be observed inside the processor in response to the recording disable signal; and

the signal selection module is further configured to set a transmission data source of the ethernet interface module to normal operation data in response to the record disable signal.

14. The signal recording apparatus according to claim 8 or 13, wherein the operation mode of the signal recording apparatus includes a signal recording mode and a normal operation mode based on the operation state of the processor including a debug state and a normal state, wherein,

transmitting the recording enable signal to the signal recording device in response to the processor entering the debug state from the normal state, such that the signal recording device enters the signal recording mode;

and in response to the processor returning from the debug state to the normal state, sending the record disable signal to the signal recording device so that the signal recording device enters the normal operation mode.

15. The signal recording apparatus of claim 7, wherein the signal to be observed comprises at least one of: processor program count pointer, processor internal bus, processor internal register, processor internal program execution sequence.

16. An ethernet-based processor-oriented signal recording device, comprising:

a processor; and

a memory having stored thereon computer executable instructions for implementing the method of any of claims 1-6 when executed by a processor.

17. A computer readable storage medium having stored thereon computer executable instructions for implementing the method of any of claims 1-6 when executed by a processor.