CN115148602A - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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CN115148602A
CN115148602A CN202210826777.8A CN202210826777A CN115148602A CN 115148602 A CN115148602 A CN 115148602A CN 202210826777 A CN202210826777 A CN 202210826777A CN 115148602 A CN115148602 A CN 115148602A
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side wall
dielectric layer
layer
substrate
ldmos device
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陈正龙
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Shanghai Bright Power Semiconductor Co Ltd
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Shanghai Bright Power Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention provides an LDMOS device and a manufacturing method thereof.A side wall with a step side wall is formed on the side wall of a field oxide layer, a field plate with a step part is formed on the basis of the side wall with the step side wall, the surface electric field of a drift region near the field oxide layer can be further optimized by utilizing the step part of the field plate, and the side wall with the step side wall can prevent polycrystalline silicon from being positioned at the bottom of the drift region to be broken down, so that a more effective RESURF result is provided, and higher breakdown voltage and lower on-resistance can be further realized. In addition, the side wall with the step side wall is manufactured by performing corresponding anisotropic etching process on the multilayer laminated dielectric layers, the process is simple, the side wall is self-aligned, and the size is not required to be etched.

Description

LDMOS device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to an LDMOS device and a manufacturing method thereof.
Background
Lateral double-Diffused Metal Oxide Semiconductor (LDMOS) devices have the advantages of high withstand voltage, large gain, low distortion, and the like, and are more compatible with a Complementary Metal Oxide Semiconductor (CMOS) process, so that the LDMOS devices are widely applied to integrated circuits.
For the LDMOS device, it is required to achieve a higher Breakdown Voltage (BV) and a lower on-resistance (Rsp), and the main method is to increase the Breakdown voltage by using a RESURF (Reduced Surface Field) technique. Specifically, referring to fig. 1, after a well 101 is formed in a substrate 100, a drain drift region 102 is added to the substrate 100, a mask (mask layer) is added, material deposition, photolithography and etching are performed, a ROX (field Oxide) structure 103 is formed on the surface of the drain drift region 102, a Gate Oxide (GOX, not shown) and polysilicon (poly) are then deposited, the ROX structure 103 can make polysilicon laterally extend from a channel onto the drain drift region 102, and after the polysilicon and the Gate Oxide are further etched, a field plate 104 is formed, which changes electric field distribution of the drain drift region and does not break down at the bottom of the polysilicon, so that a higher breakdown voltage can be achieved.
Disclosure of Invention
The invention aims to provide an LDMOS device and a manufacturing method thereof, which can achieve a better RESURF effect, further improve the breakdown voltage of the device and reduce the on-resistance.
To achieve the above object, the present invention provides a method for manufacturing an LDMOS device, which includes:
providing a substrate and forming a field oxide layer on a part of the substrate;
depositing a plurality of dielectric layers on the field oxide layer and the exposed substrate in a conformal manner;
sequentially carrying out anisotropic etching on the multiple dielectric layers to form a side wall formed by stacking the multiple dielectric layers on the side wall of the field oxide layer;
removing the upper dielectric layer in the side wall to enable the side wall to form a step side wall;
depositing a polysilicon layer on the field oxide layer, the side wall and the substrate at the periphery of the side wall in a conformal manner;
and etching to remove the redundant polysilicon layer to form a field plate with a step part, wherein the step part of the field plate covers the step side wall and continuously extends to the partial top of the field oxide layer.
Optionally, the method for manufacturing an LDMOS device further includes, before forming a field oxide layer on a portion of the substrate, or after forming the field plate:
performing ion implantation on a partial region of the substrate to form a well region of a first conductivity type;
and carrying out ion implantation on partial area of the substrate outside the well region to form a drift region of the second conduction type.
Optionally, the multiple dielectric layers include a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence from bottom to top, the second dielectric layer is made of a material different from that of the first dielectric layer and that of the third dielectric layer, and the third dielectric layer is the upper dielectric layer.
Optionally, the step of sequentially performing anisotropic etching on the multiple dielectric layers to form the side wall includes:
performing anisotropic etching on the third dielectric layer by taking the second dielectric layer as an etching stop layer, and forming a first side wall on the side wall of the top of the second dielectric layer;
and carrying out anisotropic etching on the second dielectric layer by taking the first dielectric layer as an etching stop layer to form a second side wall with the side wall aligned with the first side wall.
Optionally, in the process of performing anisotropic etching on the second dielectric layer to form the second sidewall, the first sidewall is subjected to anisotropic etching to thin the first sidewall, so that the top of the first sidewall and the top of the second sidewall are flush with each other and not higher than the top of the first dielectric layer on the top of the field oxide layer.
Optionally, the step of removing the upper dielectric layer in the sidewall spacer to form a stepped sidewall on the sidewall spacer includes: removing the first dielectric layer exposed by the first side wall and the second side wall;
the manufacturing method of the LDMOS device further comprises the following steps: and forming a gate dielectric layer after the step side wall is formed and before the polysilicon layer is deposited in a conformal manner, wherein the gate dielectric layer is connected with the side wall and covers part of the substrate at the periphery of the side wall.
Optionally, the step of removing the upper dielectric layer in the sidewall so that the sidewall forms a step sidewall comprises: removing the first side wall and reserving the first dielectric layer;
the manufacturing method of the LDMOS device further comprises the following steps: and after removing the redundant polysilicon layer by etching to form a field plate with a step part, etching to remove the redundant first dielectric layer by taking the field plate and the second side wall as masks, wherein the first dielectric layer between the field plate and the substrate is used as a gate dielectric layer.
Based on the same inventive concept, the present invention also provides an LDMOS device, which includes:
a substrate;
the field oxide layer is formed on part of the substrate;
the side wall is provided with a step side wall and is formed on the side wall of the field oxide layer;
a field plate having a step portion covering the step sidewall and continuously extending onto a portion of the top of the field oxide layer.
Optionally, the sidewall spacer includes a first dielectric layer and a second dielectric layer stacked in sequence from bottom to top, and the material of the second dielectric layer is different from that of the first dielectric layer.
Optionally, the first dielectric layer further extends from the bottom of the stepped sidewall to a position between the field plate and the substrate at the periphery of the sidewall, so as to serve as a gate dielectric layer;
or the outer side wall of the first dielectric layer is aligned with the outer side wall of the second dielectric layer, the LDMOS device further comprises a gate dielectric layer, and the gate dielectric layer is connected with the side wall and is positioned between the field plate and part of the substrate on the periphery of the side wall.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. the side wall with the step side wall is formed on the side wall of the field oxide layer, and the electric field intensity of a junction area of a thicker field oxide layer on the drift region and a thinner gate dielectric layer on the periphery of the side wall can be reduced by utilizing the thickness gradual change function of the side wall with the step side wall, so that the breakdown voltage of the device can be improved.
2. The polysilicon field plate is covered on the step side wall along with the shape to form a step part, so that the surface electric field of the drift region near the field oxide layer is further optimized by using the step part of the field plate, the side wall with the step side wall can prevent the polysilicon from being punctured at the bottom of the drift region, a more effective RESURF result is provided, and then higher breakdown voltage and lower on-resistance can be realized.
3. The side wall with the step side wall is manufactured by utilizing the multilayer laminated dielectric layers to carry out corresponding etching processes in all directions, the process is simple, the side wall is self-aligned, the size is not required to be aligned, and compared with the scheme that the field oxide layer side wall is directly etched to trim the field oxide layer side wall into the step side wall, the bird's beak structure of the field oxide layer and the polycrystalline silicon layer is avoided, the problem of tip effect is avoided, and the method is suitable for manufacturing 6V-300V LDMOS devices.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional LDMOS device.
Fig. 2 is a schematic flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present invention.
Fig. 3 to 12 are schematic cross-sectional views illustrating a method for manufacturing an LDMOS device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when a layer is referred to as being formed on another layer, it can be formed directly on the other layer or intervening layers may also be present. Where the terms "upper", "lower", "top", "bottom", "inner", "middle", "longitudinal", "lateral", and the like indicate orientations or positional relationships based on those shown in the drawings, it is merely for convenience in describing the present invention and simplifying the description, and it is not intended to indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention, where "longitudinal" may be understood as a direction perpendicular to the surface of a substrate, and "lateral" may be understood as a direction parallel to the surface of a substrate. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising" are used in an inclusive sense to specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items. The terms "identical" and "consistent" include identical and identical meanings, and may also include meanings that are approximately identical or nearly identical subject to allowable process tolerances. The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2 to fig. 12, an embodiment of the invention provides a method for manufacturing an LDMOS device, which includes:
s1, providing a substrate, and forming a field oxide layer on part of the substrate;
s2, depositing a plurality of dielectric layers on the field oxide layer and the exposed substrate in a conformal manner;
s3, sequentially carrying out anisotropic etching on the multiple dielectric layers to form a side wall formed by stacking the multiple dielectric layers on the side wall of the field oxide layer;
s4, removing the upper dielectric layer in the side wall to enable the side wall to form a step side wall;
s5, depositing a polysilicon layer on the field oxide layer, the side wall and the substrate on the periphery of the side wall in a conformal manner;
and S6, etching and removing the redundant polycrystalline silicon layer to form a field plate with a step part, wherein the step part of the field plate covers the step side wall and continuously extends to the partial top of the field oxide layer.
Referring to fig. 3, the substrate 200 provided in step S1 may be any suitable substrate material, such as silicon, silicon-on-insulator, germanium, silicon carbide, silicon germanium, etc., or a substrate material on which a semiconductor epitaxial layer, such as silicon carbide, is epitaxially grown. The conductivity type of the substrate is, for example, the second conductivity type.
In step S1, a drift region 204 is further formed in the substrate 200, and a field oxide layer 205 is formed on a portion of the drift region 204, which includes the following steps:
s1.1, referring to fig. 3, a Photo Resistance (PR) layer 201 is coated on a substrate 200, the PR layer 201 is subjected to photolithography (including exposure and development) to expose a surface of a partial region (i.e., a region where a well region 202 is to be formed) of the substrate 200, and then the exposed region of the substrate 200 is subjected to ion implantation using the photoresist layer 201 after photolithography as a mask to form the well region 202 of a first conductive type.
S1.2, referring to fig. 4, the photoresist layer 201 is removed, photoresist material is coated on the substrate 200 again to form a photoresist layer 203, the photoresist layer 203 is subjected to photolithography (including exposure and development) to mask the well region 202 and expose a portion of the substrate 200 (i.e., a region where the drift region 204 is to be formed) outside the well region 202, and then the photoresist layer 203 after photolithography is used as a mask to perform ion implantation on the exposed region of the substrate 200 to form the drift region 204 of the second conductivity type as a voltage-withstanding region of the LDMOS device.
S1.3, referring to fig. 5, the photoresist layer 203 is removed, an oxide layer (such as silicon oxide, etc.) is deposited on the surface of the substrate 200 by a suitable deposition process such as chemical vapor deposition, the deposited oxide layer covers the surfaces of the well region 202 and the drift region 204, a photoresist (not shown) is coated, and the photoresist is subjected to photolithography by using a mask layer (mask), the photoresist layer after photolithography is used as a mask, the oxide layer is etched until the surfaces of the well region 202 and the drift region 204 are exposed, and a field oxide layer (ROX) 205 located on a portion of the surface of the drift region 204 is formed.
In steps S1.1 and S1.2, annealing treatment may be performed during ion implantation, or annealing treatment may be performed after the ion implantation in step S1.2, so that ions implanted in the well region 202 and the drift region 204 are diffused to a desired extent in the lateral and longitudinal directions. Wherein, in the longitudinal direction, the depth of the drift region 204 may be equal to, greater than, or less than the depth of the well region 202; the drift region 204 may be laterally contiguous with the well region 202 or may be spaced apart from the well region 202.
As an example, the substrate 200 and the well region 202 are both of a first conductivity type, and the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments of the present invention, the first conductive type may be an N-type, and the second conductive type may be a P-type.
In addition, the ion doping concentration of the drift region 204 and the well region 202 and the film thickness of the field oxide layer 205 need to be designed reasonably according to the voltage withstanding requirement and the on-resistance requirement of the LDMOS device, for example, the film thickness of the field oxide layer 205 (i.e., the deposition thickness of the oxide layer) is
Figure RE-GDA0003829822770000061
Referring to fig. 6, in step S2, a first dielectric layer 206, a second dielectric layer 207, and a third dielectric layer 208 are sequentially deposited on the substrate 200 by a suitable process such as chemical vapor deposition, and the first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 are conformal to cover the surfaces of the well region 202, the field oxide layer 205, and the drift region 204, so that the first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 form steps (or steps) when they respectively extend from above the top of the well region 202 to above the top of the field oxide layer 205.
In this embodiment, the materials of the first dielectric layer 206 and the third dielectric layer 208 are the same, and the material of the second dielectric layer 207 is different from the materials of the first dielectric layer 206 and the third dielectric layer 208. The film thickness of the first dielectric layer 206 is smaller than the film thickness of the second dielectric layer 207 and the film thickness of the third dielectric layer 208, and the first dielectric layer 206 is used as a protective layer for protecting the surfaces of the well region 202 and the drift region 204 and a stop layer when the second dielectric layer 207 is etched, and meanwhile, the process time is shortened when the second dielectric layer 207 is removed by subsequent etching. As an example, the first dielectric layer 206 and the third dielectric layer 208 are both made of silicon dioxide, the second dielectric layer 207 is made of silicon nitride, and the first dielectric layer 206, the second dielectric layer 207, and the third dielectric layer 208 have thicknesses respectively equal to
Figure RE-GDA0003829822770000071
In step S3, referring to fig. 7, first, the second dielectric layer 207 is used as an etching stop layer to perform anisotropic etching (i.e., sidewall etching) on the third dielectric layer 208, so as to remove the third dielectric layer 208 on the top of the field oxide layer 205 and most of the third dielectric layer 208 on the periphery of the sidewall of the field oxide layer 205 (including the third dielectric layer 208 on the well region 202 and on the drift region 204), and the remaining third dielectric layer 208 is retained on the sidewall of the top of the second dielectric layer 207, thereby forming a first sidewall 208a. Next, referring to fig. 7 and 8, with the first sidewall 208a as a mask and the first dielectric layer 206 as an etching stop layer, the second dielectric layer 207 is anisotropically etched (i.e., sidewall etching) to remove the second dielectric layer 207 on the top of the field oxide layer 205 and most of the second dielectric layer 207 (including the second dielectric layer 207 on the well 202 and on the drift region 204) on the periphery of the sidewall of the field oxide layer 205, so as to form a second sidewall 207a aligned with the first sidewall 208b, so that the first sidewall 208b and the second sidewall 207a form a sidewall of the field oxide layer 205, and the first dielectric layer 206 protects the surface of the substrate 200 including the well 202 and the drift region 204 in this process.
In this embodiment, in the process of etching the second dielectric layer 207 to form the second sidewall 207a, through reasonable selection of the etchant, the first sidewall 208a can be thinned by the etching process, the height and the transverse width of the top of the first sidewall 208a are reduced, the remaining first sidewall 208a is finally thinned to be the first sidewall 208b, and the remaining second dielectric layer 207 has sidewalls aligned with the first sidewall 208b and a top aligned with the first sidewall 208b, so that the height of the top of the sidewall is prevented from being higher than the surface of the first dielectric layer 206 on the top of the field oxide layer 205, and meanwhile, since the thickness of the remaining first sidewall 208b is relatively close to the thickness of the first dielectric layer 206, the first dielectric layer 206 exposed by the first sidewall 208b and the second sidewall 207a can be removed in the subsequent step S4, thereby simplifying the process.
In step S4, referring to fig. 8 and 9, the first sidewall 208b and the first dielectric layer 206 exposed by the second sidewall 207a may be removed together by using a suitable etching process, such as dry etching (anisotropic etching) or wet etching (isotropic etching), so as to form a sidewall composed of the second sidewall 207a and the remaining first dielectric layer 206a therebelow, and the sidewall has a step sidewall, where the step sidewall is composed of a surface of the second sidewall 207a exposed after the first sidewall 208b is removed and a sidewall originally exposed by the first sidewall 208 b. That is, the second side wall 207a is formed in a substantially "L" shape at this time, and the vertical portion 207b next to the side wall of the field oxide layer 205 has a film thickness d2 in the longitudinal direction larger than the film thickness d1 in the longitudinal direction of the horizontal portion 207c extending laterally outward from the bottom of the portion.
It should be noted that the etching processes in step S3 and step S4 are all self-aligned, and are implemented without an additional mask, and do not require an overlay dimension, and the process is simple, and compared with a scheme of directly etching the field oxide sidewall to trim the sidewall of the field oxide into a step sidewall, the method does not cause the field oxide to generate a bird' S beak structure, and avoids the problem of generating a tip effect.
In step S5, referring to fig. 9 and 10, a gate dielectric layer (GOX) 209 is first grown on the well region 202 and the drift region 204 by a thermal oxidation process, and then a polysilicon layer 210 is deposited on the gate dielectric layer 209 and the exposed sidewalls thereof and the surface of the field oxide layer 205 by a chemical vapor deposition process, and the deposited polysilicon layer 210 forms a step portion 210a by conformally covering the step sidewalls of the sidewalls.
The thickness of the gate dielectric layer 209 is smaller than the thickness of the horizontal portion 207c of the second sidewall 207a and the thickness of the first dielectric layer 206, so as to ensure that the polysilicon layer 210 can form a step shape (i.e., a step forming the step 210 a) when extending from the surface of the gate dielectric layer 209 to the top surface of the horizontal portion 207c of the second sidewall 207 a.
In step S6, with continued reference to fig. 9 and 10, the excess polysilicon layer 210 and the gate dielectric layer 209 thereunder are etched away, and a portion of the remaining polysilicon layer 210, which is located above the well 202 and laterally extends to the bottom of the sidewall, and the gate dielectric layer 209 is sandwiched between the well 202 and the corresponding drift region 204, forms a gate (not labeled) of the LDMOS device, and another portion, which is connected to the gate and extends along the stepped sidewall of the sidewall and laterally extends to the top of the field oxide layer 205, forms a field plate (not labeled) with a stepped portion 210a.
Referring to fig. 11, after the field plate is formed, the method for manufacturing the LDMOS device of the present embodiment may further continue the subsequent conventional process to complete the manufacturing of the LDMOS device. Examples include: firstly, performing source-drain ion implantation on the well region 202 on one side of the polysilicon layer 210 and the drift region 204 on the other side of the polysilicon layer to form a source region 212 located in the well region 202 and a drain region 213 located in the drift region 204, wherein the source region 212 and the drain region 213 are both of a second conductivity type; then, performing body region ion implantation on the well region 202 outside the source region 212 to form a body region 211 of the first conductivity type; then, high-temperature annealing treatment between 800 ℃ and 1000 ℃ is carried out, so that ions (namely impurities) in the substrate 200 are fully activated; depositing an interlayer dielectric layer, and photoetching and etching a contact hole to form a gate contact hole, a source contact hole and a drain contact hole; further depositing metal to fill the contact holes and form metal wiring, and the like.
According to the manufacturing method of the LDMOS device, the side wall which is self-aligned to the side wall of the field oxide layer is formed on the side wall of the field oxide layer through deposition and etching of the multiple dielectric layers, the side wall is expected to be provided with the step side wall, the field plate with the step part is formed through the side wall with the step side wall, then, the electric field distribution of the drift region is optimized through the field plate, the breakdown voltage of the device is improved, the on-resistance of the device can be reduced under the condition that the breakdown voltage of the existing LDMOS device is the same, and the manufacturing method is simple in process and easy to implement.
It should be understood that the technical solutions of the present invention are not limited to the methods for manufacturing the LDMOS device in the above embodiments, and those skilled in the art can make any reasonable modifications based on the above embodiments to obtain other embodiments of the present invention.
For example, in another embodiment of the present invention, in step S1, before depositing the oxide material for forming the field oxide layer 205, the drift region 204 is formed, and then the well region 202 is formed.
For another example, in another embodiment of the present invention, the well region 202 and the drift region 204 are not formed before the oxide material for forming the field oxide layer 205 is deposited in step S1, but the well region 202 and the drift region 204 are formed in the substrate 200 after the field plate is formed in step S6.
For example, in another embodiment of the present invention, in step S6, a gate dielectric layer 209 is formed by a deposition process, and the gate dielectric layer is further etched after the polysilicon layer 210 is etched to form a field plate, so as to remove the excess gate dielectric layer 209, where the remaining gate dielectric layer is covered by the remaining polysilicon layer 210, that is, a part of the remaining gate dielectric layer covers the surface of the sidewall and extends to the top of the field oxide layer 205.
For another example, in still another embodiment of the present invention, referring to fig. 12, the material of the first dielectric layer 206 and the third dielectric layer 207 deposited in step S2 is different, and the deposited first dielectric layer 206 may be used as a subsequent gate dielectric layer, so that the first dielectric layer 206 is remained when the first sidewall 208b is removed in step S4, and after the polysilicon layer 210 is etched in step S6, the first dielectric layer 206 is etched by using the remaining polysilicon layer 210 as a mask, and the remaining first dielectric layer 206 is covered by the remaining polysilicon layer 210 and the second sidewall 207a, that is, a portion of the remaining first dielectric layer 206 directly sandwiched between the polysilicon layer 210 and the substrate 200 is used as the gate dielectric layer 206b between the gate and the substrate 200, and another portion is directly covered by the second sidewall 207a and is used as a portion 206a of the sidewall.
Based on the same inventive concept, an embodiment of the present invention further provides an LDMOS device that can be formed by using the method for manufacturing an LDMOS device as described in any of the above embodiments, referring to fig. 11, the LDMOS device includes a substrate 200, a field oxide layer 205, a sidewall having a step sidewall, and a field plate having a step portion. The materials of the substrate 200, the field oxide layer 205, the sidewall having the step sidewall, and the field plate having the step portion may refer to the above description, and are not described herein again.
A well region 202 of the first conductivity type and a drift region 204 of the second conductivity type are formed in the substrate 200, and a body region 211 of the first conductivity type and a source region 212 of the second conductivity type are formed in the well region 202, and a drain region 213 of the second conductivity type is formed in the drift region 204.
A field oxide layer 205 is formed on a portion of the drift region 204 and exposes the drain region 213.
The sidewall spacer with step sidewall includes a first dielectric layer 206a (i.e., bottom sidewall spacer) and a second dielectric layer (i.e., second sidewall 207a above) sequentially stacked on the sidewall of the field oxide layer 205.
The step of the field plate covers the step sidewall of the sidewall and extends continuously to the top of the portion of the field oxide layer 205.
The LDMOS device of this embodiment further has a gate, the gate and the field plate are formed by using the same polysilicon layer, the gate laterally extends from one side of the field plate opposite to the drain region 213 to a portion of the top of the well region 202, and a gate dielectric layer 209 is sandwiched between the gate and the well region 202 and the drift region 204.
As an example, the gate dielectric layer 209 and the first dielectric layer 206a are formed by using the same dielectric layer, or the first dielectric layer further extends from the bottom of the sidewall of the step to a position between the field plate and the substrate at the periphery of the sidewall to serve as the gate dielectric layer.
As another example, the gate dielectric layer 209 and the first dielectric layer 206a are formed by different films, in which case, the outer sidewall of the first dielectric layer 206a is aligned with the outer sidewall of the second dielectric layer, and the gate dielectric layer 209 is connected to the sidewall and is located between the field plate and a portion of the substrate at the periphery of the sidewall.
In summary, in the LDMOS device and the manufacturing method thereof of the present invention, the sidewall having the step sidewall is formed on the sidewall of the field oxide layer, and the electric field strength of the boundary region between the thicker field oxide layer on the drift region and the thinner gate dielectric layer at the periphery of the sidewall can be reduced by using the thickness gradual change function of the sidewall having the step sidewall, so as to improve the breakdown voltage of the device. Meanwhile, the polysilicon field plate covers the stepped side wall to form a stepped part, so that the surface electric field of the drift region near the field oxide layer is further optimized by using the stepped part of the field plate, and the side wall with the stepped side wall can prevent the polysilicon from being punctured at the bottom of the drift region, thereby providing a more effective RESURF result and further realizing higher breakdown voltage and lower on-resistance. In addition, the side wall with the step side wall is manufactured by utilizing the multilayer laminated dielectric layers to carry out corresponding etching processes in all directions, the process is simple, the side wall is self-aligned, the size is not required to be etched, and compared with the scheme that the field oxide layer side wall is directly etched to trim the side wall of the field oxide layer into the step side wall, the bird's beak structure of the field oxide layer is avoided, the problem of tip effect is avoided, and the method is suitable for manufacturing 6V-300V LDMOS devices.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims (10)

1. A method for manufacturing an LDMOS device, comprising:
providing a substrate and forming a field oxide layer on a part of the substrate;
depositing a plurality of dielectric layers on the field oxide layer and the exposed substrate thereof in a conformal manner;
sequentially carrying out anisotropic etching on the multiple dielectric layers to form a side wall formed by stacking the multiple dielectric layers on the side wall of the field oxide layer;
removing the upper dielectric layer in the side wall to enable the side wall to form a step side wall;
depositing a polysilicon layer on the field oxide layer, the side wall and the substrate at the periphery of the side wall in a conformal manner;
and etching to remove the redundant polysilicon layer to form a field plate with a step part, wherein the step part of the field plate covers the step side wall and continuously extends to the partial top of the field oxide layer.
2. The method of fabricating the LDMOS device set forth in claim 1 further comprising, before forming a field oxide layer on a portion of said substrate or after forming said field plate:
performing ion implantation on a partial region of the substrate to form a well region of a first conductivity type;
and carrying out ion implantation on partial region of the substrate outside the well region to form a drift region of the second conduction type.
3. The method for manufacturing the LDMOS device of claim 1, wherein the plurality of dielectric layers includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence from bottom to top, the second dielectric layer is made of a different material from the first dielectric layer and the third dielectric layer, and the third dielectric layer is the upper dielectric layer.
4. The method for manufacturing the LDMOS device of claim 3, wherein the step of sequentially performing anisotropic etching on the plurality of dielectric layers to form the side wall comprises:
performing anisotropic etching on the third dielectric layer by taking the second dielectric layer as an etching stop layer, and forming a first side wall on the side wall of the top of the second dielectric layer;
and carrying out anisotropic etching on the second dielectric layer by taking the first dielectric layer as an etching stop layer to form a second side wall with the side wall aligned with the first side wall.
5. The manufacturing method of the LDMOS device of claim 4, wherein in the process of performing anisotropic etching on the second dielectric layer to form the second side wall, the first side wall is simultaneously subjected to anisotropic etching to thin the first side wall, so that the top of the first side wall and the top of the second side wall are flush with each other and are not higher than the top of the first dielectric layer on the top of the field oxide layer.
6. The method for manufacturing the LDMOS device of claim 4, wherein the step of removing the upper dielectric layer in the sidewall spacer to form a stepped sidewall spacer on the sidewall spacer comprises: removing the first dielectric layer exposed by the first side wall and the second side wall;
the manufacturing method of the LDMOS device further comprises the following steps: and forming a gate dielectric layer after the step side wall is formed and before the polysilicon layer is deposited in a conformal manner, wherein the gate dielectric layer is connected with the side wall and covers part of the substrate at the periphery of the side wall.
7. The method for manufacturing the LDMOS device of claim 4, wherein the step of removing the upper dielectric layer in the sidewall spacer to form a stepped sidewall spacer on the sidewall spacer comprises: removing the first side wall and reserving the first dielectric layer;
the manufacturing method of the LDMOS device further comprises the following steps: and after removing the redundant polysilicon layer by etching to form a field plate with a step part, etching to remove the redundant first dielectric layer by taking the field plate and the second side wall as masks, wherein the first dielectric layer between the field plate and the substrate is used as a gate dielectric layer.
8. An LDMOS device, comprising:
a substrate;
the field oxide layer is formed on part of the substrate;
the side wall is provided with a step side wall and is formed on the side wall of the field oxide layer;
a field plate having a step portion covering the step sidewall and continuously extending onto a portion of the top of the field oxide layer.
9. The LDMOS device of claim 8, wherein the sidewall spacer includes a first dielectric layer and a second dielectric layer stacked in sequence from bottom to top, the second dielectric layer being of a different material than the first dielectric layer.
10. The LDMOS device set forth in claim 8 wherein said first dielectric layer further extends laterally from the bottom of said step sidewall to between said field plate and said substrate at the periphery of said sidewall spacer to serve as a gate dielectric layer;
or the outer side wall of the first dielectric layer is aligned with the outer side wall of the second dielectric layer, the LDMOS device further comprises a gate dielectric layer, and the gate dielectric layer is connected with the side wall and is positioned between the field plate and part of the substrate on the periphery of the side wall.
CN202210826777.8A 2022-07-13 2022-07-13 LDMOS device and manufacturing method thereof Pending CN115148602A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116525660A (en) * 2023-07-03 2023-08-01 北京智芯微电子科技有限公司 LDMOSFET device with longitudinal gate oxide structure and manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116525660A (en) * 2023-07-03 2023-08-01 北京智芯微电子科技有限公司 LDMOSFET device with longitudinal gate oxide structure and manufacturing method
CN116525660B (en) * 2023-07-03 2023-09-12 北京智芯微电子科技有限公司 LDMOSFET device with longitudinal gate oxide structure and manufacturing method

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