CN115148268A

CN115148268A - Storage device, verification method and storage system

Info

Publication number: CN115148268A
Application number: CN202210727804.6A
Authority: CN
Inventors: 张静; 王砚; 郭晓江
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2022-10-04

Abstract

The embodiment of the application provides a storage device, a verification method and a storage system, wherein the storage device comprises: a memory cell array including a plurality of memory cells; sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node; control logic coupled to the memory cell array and the sensing circuit, the control logic configured to: the method includes the steps of pre-charging the sensing node to a predetermined initial voltage through the sensing circuit, discharging the sensing node through the sensing circuit, and acquiring at least three different verification information in a discharging process of the sensing node, wherein the sensing potential corresponding to each verification information is different.

Description

Storage device, verification method and storage system

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a storage device, a verification method and a storage system.

Background

Currently, for NAND flash memory, an Incremental Step-Pulse Programming (ISPP) method is generally used for Programming, that is, a memory cell is programmed by sequentially using a plurality of Pulse Programming voltages which are increased Step by Step, and each Programming process may include a Programming operation and a subsequent verifying operation. During the programming process, the memory cells are verified using a verify voltage after each program operation performed on the memory cells.

Disclosure of Invention

The embodiment of the application provides a storage device, a verification method and a storage system.

In a first aspect, an embodiment of the present application provides a storage device, where the storage device includes:

a memory cell array including a plurality of memory cells;

sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node;

control logic coupled to the memory cell array and the sensing circuit, the control logic configured to:

precharging the sense node to a predetermined initial voltage through the sensing circuit,

discharging the sense node through the sense circuit, an

At least three different verification messages are acquired in the discharging process of the sensing node, and the sensing potential corresponding to each verification message is different.

In a second aspect, an embodiment of the present application provides a verification method, where the method includes:

precharging a sensing node to a predetermined initial voltage;

and discharging the sensing node, and acquiring at least three different verification information in the discharging process of the sensing node, wherein the sensing potential corresponding to each verification information is different.

In a third aspect, an embodiment of the present application provides a memory system, including a controller and the memory device in the foregoing technical solution; the controller is coupled to the storage device and is used for controlling the storage device.

An embodiment of the application provides a storage device, a verification method and a storage system, wherein the storage device comprises: a memory cell array including a plurality of memory cells; sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node; control logic coupled to the memory cell array and the sensing circuit, the control logic configured to: the method includes the steps of pre-charging the sensing node to a predetermined initial voltage through the sensing circuit, discharging the sensing node through the sensing circuit, and acquiring at least three different verification information in a discharging process of the sensing node, wherein the sensing potential corresponding to each verification information is different. According to the embodiment of the application, the sensing node is discharged after being precharged to the preset initial voltage, and the verification information is obtained according to the sensing potential sensing in the discharging process of the sensing node, so that the times of pausing discharging of the sensing node in the sensing process are reduced, and the verification time is saved.

Drawings

FIG. 1 is a block diagram of a memory system shown in the present application according to an exemplary embodiment;

FIG. 2A is a schematic diagram of a memory card shown for the present application in accordance with an exemplary embodiment;

FIG. 2B is a schematic diagram of a Solid State Drive (SSD) shown in accordance with an exemplary embodiment of the present application;

fig. 3 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a sensing circuit according to an embodiment of the present disclosure;

FIG. 5 is a first timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 6 is a second timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 7 is a third timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 8 is a distribution diagram of threshold voltages of memory cells according to an embodiment of the present application;

fig. 9 is a schematic flowchart of a verification method according to an embodiment of the present application;

the figure includes: 100. a system; 102. a memory system; 104. a storage device; 106. a controller; 108. a host; 202. a memory card; 204. a memory card connector; 206. a Solid State Drive (SSD); 208. an SSD connector; 310. an array of memory cells; 320. a sensing circuit; 321. a first sensing circuit; 322. a second sensing circuit; 323. a third sensing circuit; 3211. a first latch; 3221. a second latch; 3231. a third latch; 324. a pre-charge circuit; 330. a row decoder; 340. and a control logic.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on … …," "adjacent … …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent … …," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relationship terms such as "under … …", "under … …", "under … …", "over … …", "over", and the like, may be used herein for ease of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Referring to FIG. 1, FIG. 1 is a block diagram of a memory system shown in accordance with an exemplary embodiment of the present application. The system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more storage devices 104 and a controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 108 may be configured to send data to storage device 104 or receive data from storage device 104.

The storage device 104 may be any storage device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) may have reduced leakage current from the drive transistors (e.g., string drivers) coupled to unselected word lines during an erase operation, which allows for further scaling of the drive transistors.

According to some embodiments, the controller 106 is coupled to the storage device 104 and the host 108, and is configured to control the storage device 104. Controller 106 may manage data stored in storage 104 and communicate with host 108. In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. The controller 106 may be configured to control the operations of the memory device 104, such as read, erase, and program operations. The controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, controller 106 is also configured to process Error Correction Codes (ECC) with respect to data read from memory device 104 or written to memory device 104. The controller 106 may also perform any other suitable functions, such as formatting the storage device 104. The controller 106 may communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the controller 106 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The controller 106 and the one or more storage devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronics. In one example as shown in fig. 2A, the controller 106 and the single storage device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 108 in FIG. 1). In another example as shown in fig. 2B, controller 106 and plurality of storage devices 104 may be integrated into SSD 206. SSD 206 can also include an SSD connector 208 that couples SSD 206 with a host (e.g., host 108 in fig. 1). In some embodiments, the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.

In an embodiment of the present application, the memory device includes a memory Cell array, and the memory Cell array includes a plurality of memory cells, where a memory Cell may be a Single-Level Cell (SLC) type, a Multi-Level Cell (MLC) type, a triple-Level Cell (TLC) type, a Quad-Level Cell (QLC) type, a Penta-Level Cell (Penta-Level Cell, PLC) type, or a higher Level type. Each SLC cell may store 1 bit of data, each MLC cell may store 2 bits of data, each TLC cell may store 3 bits of data, each QLC cell may store 4 bits of data, and each PLC cell may store 5 bits of data. Each memory cell may maintain one of Q possible data states, where Q is a positive integer equal to or greater than 2, e.g., Q =2 for SLC, Q =4 for MLC, Q =8 for TLC, Q =16 for QLC, and Q =32 for PLC. The Q possible data states may include an erased state S (0) and programmed states S (1) through S (Q-1), where programmed state S (1) is the lowest programmed state and programmed state S (Q-1) is the highest programmed state. In one example, TLC can be programmed to one of 8 possible data states, where program state S (1) is the lowest program state and program state S (7) is the highest program state.

Threshold voltage distributions corresponding to different program states are different, and therefore, a plurality of verification processes need to be performed, generally, during verification, a memory cell needs to be charged to a higher potential and then a plurality of discharging operations are performed, SO that voltages at Sensing nodes (SO) corresponding to different stages of the memory cell are detected by a Sensing circuit, a Sensing result can be used to complete verification of the memory cell, and a verification result can be stored in a latch of a page buffer for determining a program result of the memory cell.

After the memory cell performs the programming operation, a corresponding verification operation needs to be performed, a key process in the verification operation is a sense node SO discharging process, and charges accumulated at the sense node SO can be discharged through the bit line BL and the channel. If the total amount of discharge during the predetermined discharge period is sufficient for a significant voltage drop to occur at the sense node SO, the threshold voltage of the corresponding memory cell can be considered to be lower than the verify voltage, which indicates that the memory cell is not verified and needs to be programmed and verified again. On the other hand, if the total amount of discharge during the predetermined discharge period is small, i.e., the amount of charge or voltage remaining after discharge is higher than the predetermined voltage, it indicates that the memory cell passes verification and is restricted from programming in the next programming cycle. However, in the current verification operation, the memory cells belonging to different programming states need to be verified by using different verification voltages, and in the process of discharging the sensing node SO of the memory cell, multiple charging operations need to be performed, SO that the verification process is complicated, the verification time is too long, and the programming efficiency is affected.

Based on this, an embodiment of the present application provides a memory device, and referring to fig. 3, fig. 3 is a schematic structural diagram of the memory device provided in the embodiment of the present application, as shown in fig. 3, the memory device includes:

a memory cell array 310, the memory cell array 310 including a plurality of memory cells;

a sensing circuit 320 coupled to the memory cell array 310, the sensing circuit 320 including a first sensing circuit 321, a second sensing circuit 322, and a third sensing circuit 323 coupled to a sensing node;

control logic 340 coupled to the memory cell array 310 and the sensing circuit 320, the control logic 340 configured to:

the sensing node is precharged to a predetermined initial voltage by the sensing circuit 320,

the sense node is discharged by sense circuit 320, an

Here, the control logic 340 may be connected with the memory cell array 310 through the sensing circuit 320 and the row decoder 330. The sensing circuit 320, row decoder 330, and control logic 340 may be implemented in peripheral circuits of the memory device.

Here, the memory cell array 310 may be connected to the row decoder 330 via word lines WL0 to WLn-1, a cell string selection line SSL, and a ground selection line GSL. The memory cell array 310 may also be connected to the sensing circuit 320 via bit lines BL0 to BLm-1. The memory cell array 310 may include a plurality of memory cell strings. Each memory cell string may be connected to a bit line via a string selection transistor SST. The memory cell array 310 may be formed of a memory plane (plane) including a plurality of memory blocks (blocks), each of which may include a plurality of memory pages (pages), each of which may include a plurality of memory cells (cells). In addition, although the memory device is illustrated as a flash memory device as an example, it is understood that the present application is not limited to the flash memory device and may be applied to any type of non-volatile memory, for example, a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read Only Memory (EPROM), an erasable programmable read only memory (EEPROM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Resistive Random Access Memory (RRAM), a Ferroelectric Random Access Memory (FRAM), and the like.

Here, the sensing circuit 320 may function as a write driver or as a sense amplifier depending on the operation mode. During a program operation, the sensing circuit 320 may transmit a bit line voltage corresponding to a memory cell to be programmed to a bit line of the memory cell array 310. During a read operation, the sensing circuit 320 may sense data stored in a selected memory cell through the sensing node. The sensing circuit 320 may latch the verification data and output the verification data to the outside.

In the embodiment of the present application, the sensing node is precharged to a predetermined initial voltage, the sensing node is discharged, at least three different verification information are obtained in the discharging process of the sensing node, and the sensing potential corresponding to each verification information is different. Here, the three different pieces of verification information may include first verification information, second verification information, and third verification information, the first verification information, the second verification information, and the third verification information corresponding to the first sensing potential, the second sensing potential, and the third sensing potential, respectively.

In some embodiments, the first sensing circuit may include a first latch to store the first verification information; the second sensing circuit may include a second latch to store the second verification information; the third sensing circuit may include a third latch to store the third verification information.

Here, the row decoder 330 may select any one of the memory blocks of the memory cell array 310 in response to the address ADDR. The row decoder 330 may select any one of word lines of a selected memory block. The row decoder 330 may transmit a word line voltage to a word line of a selected memory block.

Here, the control logic 340 may receive a program command CMD and may output various control signals for controlling the sensing circuit 320 and the row decoder 330 to perform a program operation in response to the program command CMD. In addition, the control logic 340 is further configured to discharge the sensing node SO after precharging the sensing node SO to a predetermined initial voltage, and obtain at least first verification information, second verification information and third verification information during the discharge process of the sensing node SO, where the first verification information, the second verification information and the third verification information correspond to the first sensing potential, the second sensing potential and the third sensing potential, respectively. The first verification information, the second verification information and the third verification information are different, and the first sensing potential, the second sensing potential and the third sensing potential are also different.

Referring to fig. 4, fig. 4 is a circuit diagram of a sensing circuit provided in an embodiment of the present application. As shown in fig. 4, the sensing circuit includes a first sensing circuit including a first latch 3211 for storing first verification information, a second sensing circuit including a second latch 3221 for storing second verification information, and a third sensing circuit including a third latch 3231 for storing third verification information.

In a specific example, the first latch 3211 and the second latch 3221 may store information about a bit line forcing operation (forcing operation) corresponding to different bit line voltages required to be applied to the respective bit lines during programming controlled by the program command CMD, and in the present embodiment, four different bit line voltages may be latched by the first latch 3211, the second latch 3221 and the third latch 3231 during programming. A detailed description thereof will be described later with reference to fig. 8 and the like.

Still referring to FIG. 4, in the embodiment of the present application, the sensing circuit further includes a pre-charge circuit 324, and the pre-charge circuit 324 is connected to the bit line through the sensing node SO.

Here, the precharge circuit 324 may be configured to apply a first bit line voltage, which is greater than a ground voltage and less than a program-inhibited bit line voltage, to a first bit line connected to the first forced cell. The precharge circuit 324 may be further configured to apply a second bit line voltage greater than the first bit line voltage and less than the program-inhibited bit line voltage to a second bit line connected to the second forced cell. It should be noted that the precharge circuit 324 may also be configured to apply the program-inhibited bit line voltage to a third bit line connected to a third memory cell. Here, the third memory cell is a program-inhibited memory cell.

It should be noted that the bit lines in the memory cell array are connected to the sensing node and the precharge circuit through transistors, and the bit lines can be conducted to the sensing node and the precharge circuit by applying bias signals to the transistors, such as VPASS-HV or VBLBIAS, so as to program and verify the corresponding memory cells.

Still referring to fig. 4, in embodiments of the present application, the peripheral circuitry may further include a cache latch. Here, the first sensing circuit, the second sensing circuit, and the third sensing circuit may share a cache latch, which in turn performs a cache function for different bit lines. For example, the stored data of a first force cell connected to a first bit line may be transferred by a first latch to a cache latch for subsequent output; the stored data of the second forced cell connected to the second bit line may be transferred by the second latch to the cache latch for subsequent output; the stored data of the third memory cell connected to the third bit line may be transferred from the third latch to the cache latch for subsequent output. The first forcing unit, the second forcing unit, and the third storing unit will be described in detail later with reference to fig. 8.

Referring to fig. 5, fig. 5 is a first voltage timing diagram of the sensing node according to a specific example of the present application. As shown in fig. 5, the control logic is configured to precharge the sensing node to a predetermined initial voltage by applying a precharge signal PRECH-SEL, discharge and stop discharging the sensing node SO by a control signal VSOBLK, the sensing node SO being discharged when the control signal VSOBLK is at a high level; when the control signal VSOBLK is low, the sensing node SO stops discharging. At time t1, the sensing node SO is charged by applying the precharge signal PRECH-SEL SO that the sensing node SO reaches a predetermined initial voltage. At time t2, the sensing node SO starts to be discharged, and at time t3, the sensing node SO stops being discharged, and the first latch can be enabled to obtain the first verification information according to the first pause potential at the sensing node SO through the signal RST _ 2=1. At time t4, the sensing node SO is charged again by applying the precharge signal PRECH-SEL to make the sensing node SO reach the predetermined initial voltage again. At time t5, the sensing node SO starts to be discharged, and at time t6, the sensing node SO stops being discharged, and the signal RST _3=1 enables the second latch to obtain the second verification information according to the second pause potential sensing at the sensing node SO. At time t7, the sensing node SO is discharged again, and at time t8, the discharging of the sensing node SO is suspended, and by the signal SET _ s =1, the third latch can be caused to sense the third verification information according to the third suspension potential at the sensing node SO. Here, the first pause potential is larger than the second pause potential, which is larger than the third pause potential.

It should be noted that, at the time t8, after the third latch obtains the third verification information according to the third pause potential sensing of the sensing node SO, the third latch needs to continue discharging the sensing node SO until the potential at the sensing node SO recovers to the potential before the precharge, that is, the potential at the sensing node SO recovers to the potential at the sensing node SO before the time t 1. Fig. 5 only shows that at the time t8, the third latch senses the third verification information according to the third pause potential at the sensing node SO, and fig. 5 does not show the subsequent process of discharging the sensing node SO until the potential at the sensing node SO is restored to the potential before the precharge. The subsequent process of discharging the sensing node SO is not shown in fig. 6 and 7, and will not be described in detail hereinafter.

Here, from time t3 to time t4, i.e., during the time period (1), the control signal VSOBLK is at a low level, the discharging of the sensing node SO is suspended, and the first latch senses the first verification information according to the first suspension potential at the sensing node SO. At the time point from t6 to t7, i.e. the time period (2), the control signal VSOBLK is at a low level, the discharging to the sensing node SO is suspended, and the second latch senses according to the second suspension potential at the sensing node SO to obtain the second verification information.

In the embodiment of the present application, during the discharging of the sensing node, the discharging of the sensing node is suspended, SO that the latch senses the verification information according to the suspended potential at the sensing node SO.

In view of the above, embodiments of the present disclosure provide a memory device, which discharges a sensing node after the sensing node is precharged to a predetermined initial voltage, and obtains verification information according to sensing potential during the discharging process of the sensing node.

In some embodiments, referring to fig. 6, fig. 6 is a second voltage timing diagram of the sensing node provided in a specific example of the present application. As shown in fig. 6, the control logic is specifically configured to: in the discharging process of the sensing node, the discharging of the sensing node is suspended, and the first sensing circuit senses and obtains first verification information according to the suspended potential of the sensing node.

In some embodiments, after obtaining the first authentication information, the control logic is further configured to: the sensing node is charged to the preset initial voltage again, the sensing node is discharged, and under the condition that the sensing node is kept discharged, the second sensing circuit senses at least one potential of the sensing node to obtain second verification information; and the third sensing circuit senses and obtains third verification information according to the pause potential of the sensing node.

In some embodiments, the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential; wherein the first sensing potential is greater than the second sensing potential, which is greater than the third sensing potential.

The verifying operation for the specific memory cell may be implemented by using the sensing node, for example, precharging the sensing node corresponding to the specific memory cell to a predetermined initial voltage, and comparing a sensing potential (including the first sensing potential, the second sensing potential, and the third sensing potential) obtained after discharging the sensing node with a preset voltage (including the first preset voltage, the second preset voltage, and the third preset voltage) to determine whether the verifying operation for the specific memory cell passes. If the sensing potential on the sensing node is greater than or equal to a preset voltage, determining that the memory cell passes verification; if the sensing potential on the sensing node is less than the preset voltage, the memory cell is determined to be not verified.

In some embodiments, the control logic is further configured to: comparing the first sensing potential with a first preset voltage to obtain first verification information; if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used for indicating the first memory cell passing the verification of the first verification voltage.

Here, if the first sensing potential is greater than or equal to a first preset voltage, it indicates that the current threshold voltage of the first memory cell is greater than or equal to a first verification voltage, and the first memory cell passes verification; if the first sensing potential is smaller than a first preset voltage, it indicates that the current threshold voltage of the first memory cell is smaller than a first verification voltage, and the first memory cell fails to be verified.

In some embodiments, the control logic is further configured to: comparing the second sensing potential with a second preset voltage to obtain second verification information; and if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used for indicating a second storage unit passing the verification of the second verification voltage.

Here, if the second sensing potential is greater than or equal to a second preset voltage, it indicates that the current threshold voltage of the second memory cell is greater than or equal to a second verification voltage, and the second memory cell passes verification; if the second sensing potential is smaller than a second preset voltage, it indicates that the current threshold voltage of the second memory cell is smaller than a second verification voltage, and the second memory cell fails to be verified.

In some embodiments, the control logic is further configured to: comparing the third sensing potential with a third preset voltage to obtain third verification information; wherein if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used for indicating a third memory cell that passes verification of the third verification voltage.

Here, if the third sensing potential is greater than or equal to a third preset voltage, it indicates that the current threshold voltage of the third memory cell is greater than or equal to a third verification voltage, and the third memory cell passes verification; if the third sensing potential is less than a third preset voltage, it indicates that the current threshold voltage of the third memory cell is less than a third verification voltage, and the third memory cell fails verification.

In some embodiments, the first verify voltage is less than the second verify voltage, which is less than the third verify voltage.

Still referring to fig. 6, the sensing node is precharged to a predetermined initial voltage by applying a precharge signal PRECH-SEL, and the sensing node SO is discharged and stopped from being discharged by the control signal VSOBLK. At time t1, the sensing node SO is charged by applying the precharge signal PRECH-SEL to reach a predetermined initial voltage. At time t2, the sensing node SO starts to be discharged, and at time t3, the sensing node SO stops being discharged, and the first latch can obtain the first verification information according to the sensing of the suspension potential at the sensing node SO through the signal RST _ 2=1. At time t4, the sensing node SO is charged again by applying the precharge signal PRECH-SEL to make the sensing node SO reach the predetermined initial voltage again. At time t5, the sensing node SO is discharged, and when the sensing node is kept discharged, the second latch senses the second verification information according to a potential of the sensing node SO through the signal RST _ 3=1. At time t7, the sensing node SO is continuously discharged, and at time t8, the discharging of the sensing node SO is suspended, and the third latch senses the third verification information according to the suspended potential at the sensing node SO through the signal SET _ s = 1.

Here, the verification information is obtained according to the sensing potential sensing in the process of discharging the sensing node, so that the times of pausing the discharging of the sensing node in the sensing process are reduced, and the verification time is effectively saved. Specifically, in the verification process shown in fig. 6, the time saving is (t 7-t 6), i.e., the time period (2), compared to the verification process shown in fig. 5.

In an embodiment of the present application, the control logic is specifically configured to: in the discharging process of the sensing node, the discharging of the sensing node is suspended, and the second sensing circuit senses and obtains second verification information according to the suspended potential of the sensing node; recharging the sensing node to the preset initial voltage, discharging the sensing node, and sensing by the first sensing circuit according to at least one potential of the sensing node to obtain first verification information under the condition that the sensing node is kept discharged; and the third sensing circuit senses and obtains third verification information according to the pause potential of the sensing node.

In some embodiments, referring to fig. 7, fig. 7 is a third timing diagram of the voltage of the sensing node provided in a specific example of the present application. As shown in fig. 7, the control logic is specifically configured to: discharging the sensing node, and under the condition that the sensing node is kept discharged, sensing by the first sensing circuit and the second sensing circuit according to at least two different potentials of the sensing node to obtain first verification information and second verification information respectively; and the third sensing circuit senses and obtains third verification information according to the pause potential of the sensing node.

Still referring to fig. 7, the sensing node is precharged to a predetermined initial voltage by applying a precharge signal PRECH-SEL, and the sensing node SO is discharged and stopped from being discharged by the control signal VSOBLK. At time t1, the sensing node SO is charged by applying the precharge signal PRECH-SEL SO that the sensing node SO reaches a predetermined initial voltage. At time t2, the sensing node SO starts to be discharged, and when the sensing node is kept discharged, the signals RST _2=1 and RST _3=1 sequentially pass through, and the first latch and the second latch respectively sense two different potentials of the sensing node SO to obtain first verification information and second verification information. At time t7, the sensing node SO is continuously discharged, at time t8, the discharging of the sensing node SO is suspended, and the third latch senses the third verification information according to the suspension potential at the sensing node SO through the signal SET _ s = 1.

Here, the verification information is obtained according to the sensing potential sensing in the process of discharging the sensing node, so that the times of pausing the discharging of the sensing node in the sensing process are further reduced, and the verification time is effectively saved. Specifically, in the verification process shown in fig. 7, the time saving is [ (t 4-t 3) + (t 7-t 6) ], i.e., the time period ((1) + (2)) is saved, compared to the verification process shown in fig. 5.

In this embodiment, taking the ISPP programming scheme of the 3D NAND flash memory device as an example, in different programming stages of one ISPP programming process, in order to optimize threshold voltage distribution and relatively more intensively distribute the threshold values of the memory cells in the threshold voltage regions of the corresponding data states, bit line forcing operations (forcing operations) are implemented by biasing the bit lines of the memory cells of different bit lines with different bit line voltages, so that even if the programming voltages Vpgm of the gates (applied by word lines) of the memory cells of different bit lines are the same, the programming effects will be different, and the threshold voltage difference of the memory cells with the current larger threshold voltage difference is reduced after being programmed and relatively approaches to the ideal threshold voltage region of the corresponding data state.

Referring to fig. 8, fig. 8 is a distribution diagram of threshold voltages of memory cells according to an embodiment of the present application. Here, vfc1 is a first verify voltage, vfc2 is a second verify voltage, vvfy is a third verify voltage, the first verify voltage Vfc1 is less than the second verify voltage Vfc2, and the second verify voltage Vfc2 is less than the third verify voltage Vvfy. Still referring to fig. 8, the first latch may include first verification information DL corresponding to the first verification voltage Vfc1 as force information for the first force operation. The second latch may include second verification information DM corresponding to the second verification voltage Vfc2 as force information for the second force operation. The third latch may store third verify information DS corresponding to the third verify voltage Vvfy.

In example embodiments of the present application, a memory cell having a voltage greater than the first verify voltage Vfc1 is a first memory cell that passes the verification of the first verify voltage, a memory cell having a voltage greater than the second verify voltage Vfc2 is a second memory cell that passes the verification of the second verify voltage, and a memory cell having a voltage greater than the third verify voltage Vvfy is a third memory cell that passes the verification of the third verify voltage. The memory cells having the threshold voltages greater than the first verify voltage Vfc1 and less than the third verify voltage Vvfy may be memory cells to be forced, where the memory cells to be forced include a first Forcing Cell (Forcing Cell) and a second Forcing Cell, while the memory cells having the threshold voltages greater than the first verify voltage Vfc1 and less than the second verify voltage Vfc2 may be first Forcing cells to be forced, and the memory cells having the threshold voltages greater than the second verify voltage Vfc2 and less than the third verify voltage Vvfy may be second Forcing cells to be forced. The storage unit of the first storage unit except the second storage unit and the third storage unit is a first forcing unit to be subjected to a first forcing operation. In other words, the first memory cell includes a first forced cell to be subjected to a first forced operation, a second forced cell to be subjected to a second forced operation, and a third memory cell to be inhibited from programming.

In example embodiments of the present application, a memory cell having a voltage smaller than the first verifying voltage Vfc1 is a normal program cell, and the normal program cell is a memory cell in which a forced operation is not performed among the program cells.

The first latch may store information about the first forced operation during a program operation. More specifically, the first latch may store information to distinguish a memory cell to be subjected to the first forced operation among memory cells, i.e., distinguishing information to distinguish a memory cell to be subjected to the first forced operation and a memory cell not to be subjected to the first forced operation from each other, based on the first verify voltage Vfc1.

The second latch may store information about the second forced operation during the program operation. More specifically, the second latch may store information to distinguish a memory cell to be subjected to the second forced operation, i.e., distinguishing information to distinguish a memory cell to be subjected to the second forced operation and a memory cell not to be subjected to the second forced operation from each other, among memory cells based on the second verify voltage Vfc 2.

The third latch may store information used to distinguish a memory cell to be subjected to a program inhibit operation among memory cells, i.e., distinguishing information that distinguishes the memory cell to be subjected to the program operation and the memory cell to be subjected to the program inhibit operation from each other, based on the third verify voltage Vvfy. Note that the third verify information stored in the third latch is information obtained based on the program verify voltage Vvfy.

The first latch may include first verification information DL corresponding to the first verification voltage Vfc1 as force information for the first force operation. When the threshold voltage is greater than the first verification voltage Vfc1, the first latch may store "1" as the first verification information DL. In addition, the memory cell having a threshold voltage smaller than the first verify voltage Vfc1 is a normal program cell rather than a forced cell, and the first latch may store '0' as the first verify information DL. Here, the first verification information DL may be first forced operation information indicating that the memory cell of the corresponding bit line will not perform the first forced operation in the case where the first forced operation information is "0".

The second latch may include second verification information DM corresponding to the second verification voltage Vfc2 as force information for the second force operation. The second verify voltage Vfc2 may be less than the third verify voltage Vvfy and greater than the first verify voltage Vfc1. In example embodiments of the present application, memory cells having threshold voltages greater than the second verify voltage Vfc2 and less than the third verify voltage Vvfy may be memory cells to be subjected to a second force operation, referred to herein as second force cells. In other words, the second memory cell includes a second forced cell to which the second forced operation is to be performed and a third memory cell to which the program is to be inhibited. When the threshold voltage is greater than the second verification voltage Vfc2, the second latch may store "1" as the second verification information DM. Further, if the memory cell having the threshold voltage smaller than the second verification voltage Vfc2 is a memory cell not performing the second forced operation but a normal program cell performing the normal program operation and a first forced cell performing the first forced operation, the second latch may store "0" as the second verification information DM. Here, the second verification information DM may be second forced operation information indicating that the memory cell of the corresponding bit line will not perform the second forced operation in a case where the second forced operation information is "0".

The third latch may store third verify information DS corresponding to the third verify voltage Vvfy. In example embodiments of the present application, the memory Cell having a threshold voltage greater than the third verify voltage Vvfy may be an Inhibiting Cell (Inhibiting Cell), referred to herein as a third memory Cell, and the third latch may store "1" as the third verify information DS. Also, the memory Cell having a threshold voltage level smaller than the third verify voltage Vvfy may be a program Cell (PGM Cell), where the program Cell includes a normal program proceeding Cell, a first forcing Cell, and a second forcing Cell, and then the third latch may store '0' as the third verify information. Note that the third verify voltage Vvfy may also be referred to as a program verify voltage Vvfy.

In this embodiment, based on the first verification information, the second verification information, and the third verification information, a programming method of forcibly operating two bit lines for different memory cells in one programming process can be implemented, and thus, the memory cells can be prevented from being over-programmed, thereby reducing the width of threshold voltage distribution of the plurality of memory cells and improving the accuracy of the programming operation.

In some embodiments, the control logic is further configured to: applying a first bit line voltage to a first bit line connected to a first forced cell, applying a second bit line voltage to a second bit line connected to a second forced cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first, second, and third verification information; the first bit line voltage is greater than a ground voltage and less than the program-inhibit bit line voltage, and the second bit line voltage is greater than the first bit line voltage and less than the program-inhibit bit line voltage.

In some embodiments, the control logic is further configured to: according to the first, second, and third verification information, a normal program bit line voltage Vprog (e.g., a ground voltage Vgnd) is applied to the memory cells performing a normal program operation. Here, the program-inhibited bit line voltage Vinh may be a power supply voltage Vdd, the first bit line voltage being greater than a ground voltage (normal program bit line voltage Vprog) and less than the program-inhibited bit line voltage Vinh, and the second bit line voltage being greater than the first bit line voltage and less than the program-inhibited bit line voltage Vinh.

In some embodiments, the first forcing unit is a storage unit of the first storage unit other than the second storage unit and the third storage unit; the second forcing unit is a storage unit in the second storage unit except the third storage unit.

In a program process such as ISPP, when a program operation is performed by applying a same program voltage Vpgm to memory cells of a selected row, the sensing circuit may apply a corresponding bit line voltage to the corresponding memory cells using first verification information DL, second verification information DM, and third verification information DS, so that the memory cells may be distinguished from a bit line forcing operation. In other words, in the present embodiment, the different memory cells are subjected to the classification program control, the memory cells may be classified into the normal program cell, the first forced cell to be subjected to the first bit line forcing operation, the second forced cell to be subjected to the second bit line forcing operation, and the third memory cell to be subjected to the program inhibit operation, and the four types of memory cells are subjected to the classification program control using different bit line voltages.

In some embodiments, the information stored in the corresponding latch may also be updated based on the verify results of the memory cell. Specifically, the information stored in the first latch is updated according to the first verification information of the storage unit; updating the information stored in the second latch according to the second verification information of the storage unit; the information stored in the third latch is updated based on the third verification information for the memory cell.

An embodiment of the present application further provides a verification method, referring to fig. 9, where fig. 9 is a schematic flowchart of the verification method provided in the embodiment of the present application, and as shown in fig. 9, the method includes:

step S901, precharging a sensing node to a predetermined initial voltage;

step S902, discharging the sensing node, and acquiring at least three different verification information during the discharging process of the sensing node, where the sensing potential corresponding to each verification information is different.

In some embodiments, the obtaining at least three different verification information during the discharging of the sense node comprises:

and in the discharging process of the sensing node, stopping discharging the sensing node, and sensing according to the stopped potential of the sensing node to obtain first verification information.

In some embodiments, the obtaining at least three different verification information during the discharging of the sense node further comprises:

after the first verification information is obtained, the sensing node is charged to the preset initial voltage again, the sensing node is discharged, and under the condition that the sensing node is kept discharged, second verification information is obtained according to at least one potential of the sensing node;

and stopping discharging the sensing node, and sensing according to the stopping potential of the sensing node to obtain third verification information.

discharging the sensing node, and respectively sensing according to at least two different potentials of the sensing node to obtain first verification information and second verification information under the condition of keeping the sensing node discharged;

and stopping discharging the sensing node, and sensing to obtain third verification information according to the stopping potential of the sensing node.

In some embodiments, the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential;

wherein the first sensing potential is greater than the second sensing potential, which is greater than the third sensing potential.

comparing the first sensing potential with a first preset voltage to obtain first verification information;

if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used for indicating the first memory cell passing the verification of the first verification voltage.

comparing the second sensing potential with a second preset voltage to obtain second verification information;

and if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used for indicating the second memory cell passing the verification of the second verification voltage.

comparing the third sensing potential with a third preset voltage to obtain third verification information;

wherein if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used for indicating a third memory cell that passes the verification of the third verification voltage.

In some embodiments, the method further comprises:

applying a first bit line voltage to a first bit line connected to a first forced cell, applying a second bit line voltage to a second bit line connected to a second forced cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first, second, and third verification information;

the first bit line voltage is greater than a ground voltage and less than the program-inhibit bit line voltage, and the second bit line voltage is greater than the first bit line voltage and less than the program-inhibit bit line voltage.

In some embodiments, the first forcing unit is a storage unit of the first storage unit other than the second storage unit and the third storage unit;

the second forcing unit is a storage unit in the second storage unit except the third storage unit.

In some embodiments, the method further comprises:

storing the first verification information to a first latch;

storing the second verification information to a second latch;

storing the third verification information to a third latch.

The embodiment of the application also provides a memory system, which comprises a controller and the memory device in the technical scheme; the controller is coupled to the storage device and is used for controlling the storage device.

An embodiment of the application provides a storage device, a verification method and a storage system, wherein the storage device comprises: a memory cell array including a plurality of memory cells; sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node; control logic coupled to the memory cell array and the sensing circuit, the control logic configured to: the method includes the steps of pre-charging the sensing node to a predetermined initial voltage through the sensing circuit, discharging the sensing node through the sensing circuit, and acquiring at least three different verification information in a discharging process of the sensing node, wherein a sensing potential corresponding to each verification information is different. According to the embodiment of the application, the sensing node is discharged after being precharged to the preset initial voltage, and the verification information is obtained according to the sensing potential sensing in the discharging process of the sensing node, so that the times of pausing discharging of the sensing node in the sensing process are reduced, and the verification time is saved.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that are included in the present application, which are made by the present specification and the accompanying drawings, or are directly/indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A storage device, comprising:

a memory cell array including a plurality of memory cells;

discharging the sense node through the sense circuit, an

2. The storage device of claim 1, wherein the control logic is specifically configured to: in the discharging process of the sensing node, the discharging of the sensing node is suspended, and the first sensing circuit senses and obtains first verification information according to the suspended potential of the sensing node.

3. The storage device of claim 2, wherein after obtaining the first authentication information, the control logic is further configured to: the sensing node is charged to the preset initial voltage again, the sensing node is discharged, and under the condition that the sensing node is kept discharged, the second sensing circuit senses at least one potential of the sensing node to obtain second verification information; and the third sensing circuit senses and obtains third verification information according to the pause potential of the sensing node.

4. The storage device of claim 1, wherein the control logic is specifically configured to: discharging the sensing node, and sensing by the first sensing circuit and the second sensing circuit according to at least two different potentials of the sensing node to obtain first verification information and second verification information under the condition that the sensing node is kept discharged; and the third sensing circuit senses and obtains third verification information according to the pause potential of the sensing node.

5. The memory device according to claim 3 or 4, wherein the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential;

6. The storage device of claim 5, wherein the control logic is further configured to: comparing the first sensing potential with a first preset voltage to obtain first verification information;

7. The storage device of claim 6, wherein the control logic is further configured to: comparing the second sensing potential with a second preset voltage to obtain second verification information;

and if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used for indicating a second storage unit passing the verification of the second verification voltage.

8. The storage device of claim 7, wherein the control logic is further configured to: comparing the third sensing potential with a third preset voltage to obtain third verification information;

wherein if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used for indicating a third memory cell that passes verification of the third verification voltage.

9. The memory device of claim 8, wherein the first verify voltage is less than the second verify voltage, and wherein the second verify voltage is less than the third verify voltage.

10. The storage device of claim 9, wherein the control logic is further configured to: applying a first bit line voltage to a first bit line connected to a first force cell, applying a second bit line voltage to a second bit line connected to a second force cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first verification information, the second verification information, and the third verification information;

11. The storage device of claim 10,

the first forcing unit is a storage unit except the second storage unit and the third storage unit in the first storage unit;

12. The storage device of claim 3 or 4,

the first sensing circuit comprises a first latch for storing the first verification information;

the second sensing circuit comprises a second latch for storing the second verification information;

the third sensing circuit includes a third latch for storing the third verification information.

13. A method of authentication, the method comprising:

precharging a sensing node to a predetermined initial voltage;

14. The method of claim 13, wherein obtaining at least three different verification information during the discharging of the sense node comprises:

15. The method of claim 14, wherein obtaining at least three different verification information during the discharging of the sense node further comprises:

16. The method of claim 13, wherein obtaining at least three different verification information during the discharging of the sense node comprises:

17. The verification method according to claim 15 or 16, wherein the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential;

18. The method of claim 17, wherein obtaining at least three different verification information during the discharging of the sense node comprises:

19. The method of claim 18, wherein obtaining at least three different verification information during the discharging of the sensing node further comprises:

20. The method of claim 19, wherein obtaining at least three different verification information during the discharging of the sense node further comprises:

21. The method of claim 20, wherein the first verify voltage is less than the second verify voltage, and wherein the second verify voltage is less than the third verify voltage.

22. The authentication method of claim 21, further comprising:

the first bit line voltage is greater than a ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage and less than the program-inhibited bit line voltage.

23. The authentication method according to claim 22,

24. The authentication method according to claim 15 or 16, wherein the method further comprises:

storing the first verification information to a first latch;

storing the second verification information to a second latch;

storing the third verification information to a third latch.

25. A memory system comprising a controller and the memory device of any one of claims 1 to 12; the controller is coupled to the storage device and is used for controlling the storage device.