CN114822662A

CN114822662A - Storage device, verification method and storage system

Info

Publication number: CN114822662A
Application number: CN202210472297.6A
Authority: CN
Inventors: 王砚; 杜智超; 宋大植; 郭晓江; 王瑜
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-07-29

Abstract

The application discloses a storage device, a verification method and a storage system, wherein the storage device comprises: the memory cell array, the memory cell in the said memory cell array is arranged according to the row and column; sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node; control logic coupled to the memory cell array and the sensing circuit, the control logic configured to precharge the sensing node to a predetermined initial voltage and to change a sensing time point to cause the sensing node to assume at least three different potentials; the first sensing circuit, the second sensing circuit and the third sensing circuit respectively sense at least three different potentials of the sensing node to obtain first verification information, second verification information and third verification information.

Description

Storage device, verification method and storage system

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a memory device, a verification method, and a memory system.

Background

Currently, for NAND flash memory, an Incremental Step Pulse Programming (ISPP) method is generally adopted for programming, that is, a plurality of pulse programming voltages which are increased step by step are used in sequence to program a memory cell, and each programming process may include a programming operation and a subsequent verifying operation. During the programming process, the memory cells are verified using a verify voltage after each program operation performed on the memory cells.

However, in the current verification operation, memory cells belonging to different programming levels or states need to use different verification voltages, and the verification process is complicated, so that the verification time is too long, and the programming efficiency is affected.

Disclosure of Invention

Embodiments of the present application are intended to provide a memory device, a verification method, and a memory system.

The technical scheme of the application is realized as follows:

a first aspect of an embodiment of the present application provides a storage device, where the storage device includes:

the memory cell array, the memory cell in the said memory cell array is arranged according to the row and column;

sensing circuitry coupled to the memory cell array, the sensing circuitry including first, second, and third sensing circuitry coupled to a sense node;

control logic coupled to the memory cell array and the sensing circuit, the control logic configured to precharge the sensing node to a predetermined initial voltage and to change a sensing time point to cause the sensing node to assume at least three different potentials; the first sensing circuit, the second sensing circuit and the third sensing circuit respectively sense at least three different potentials of the sensing node to obtain first verification information, second verification information and third verification information;

the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information;

after obtaining the first verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change a sensing time point to cause the sensing node to assume at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense at least two different potentials of the sensing node to obtain second verification information and third verification information.

after obtaining the second verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change a sensing time point to cause the sensing node to assume at least two different potentials; the first sensing circuit and the third sensing circuit respectively sense at least two different potentials of the sensing node to obtain first verification information and third verification information.

Optionally, the control logic is specifically configured to discharge the sensing node after precharging the sensing node to a predetermined initial voltage, and change a sensing time point during the discharge of the sensing node to make the sensing node assume at least three different potentials;

the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential.

Optionally, the control logic is further configured to: comparing the first sensing potential with a first preset voltage to obtain first verification information;

if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used for indicating the first memory cell passing the verification of the first verification voltage.

Optionally, the control logic is further configured to: comparing the second sensing potential with a second preset voltage to obtain second verification information;

and if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used for indicating a second storage unit passing the verification of the second verification voltage.

Optionally, the control logic is further configured to: comparing the third sensing potential with a third preset voltage to obtain third verification information;

wherein if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used for indicating a third memory cell that passes verification of the third verification voltage.

Optionally, the first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

Optionally, the control logic is further configured to: applying a first bit line voltage to a first bit line connected to a first forced cell, applying a second bit line voltage to a second bit line connected to a second forced cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first, second, and third verification information; the first bit line voltage is larger than the ground voltage and smaller than the programming-inhibited bit line voltage, and the second bit line voltage is larger than the first bit line voltage.

Optionally, the first forcing unit is a storage unit of the first storage unit except for the second storage unit and the third storage unit;

the second forcing unit is a storage unit in the second storage unit except the third storage unit.

Optionally, the first sensing circuit comprises a first latch for storing the first verification information; the second sensing circuit comprises a second latch for storing the second verification information; the third sensing circuit includes a third latch for storing the third verification information.

A second aspect of the embodiments of the present application provides a verification method, including:

precharging a sensing node to a predetermined initial voltage;

changing a sensing time point to make the sensing node present at least three different potentials;

controlling a first sensing circuit, a second sensing circuit and a third sensing circuit to respectively obtain first verification information, second verification information and third verification information according to at least three different potentials of the sensing node;

Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; the controlling the first sensing circuit, the second sensing circuit and the third sensing circuit to obtain first verification information, second verification information and third verification information according to at least three different potentials of the sensing node respectively comprises:

after the first verification information is obtained, the sensing node is charged to a preset initial voltage again, and the sensing time point is changed so that the sensing node presents at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense at least two different potentials of the sensing node to obtain second verification information and third verification information.

after the second verification information is obtained, the sensing node is charged to a preset initial voltage again, and the sensing time point is changed so that the sensing node presents at least two different potentials; the first sensing circuit and the third sensing circuit respectively sense at least two different potentials of the sensing node to obtain first verification information and third verification information.

Optionally, the changing the sensing time point to make the sensing node present at least three different potentials comprises:

discharging the sensing node after precharging the sensing node to a predetermined initial voltage, and changing a sensing time point during the discharging of the sensing node to enable the sensing node to present at least three different potentials;

Optionally, the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node respectively includes:

comparing the first sensing potential with a first preset voltage to obtain first verification information;

Optionally, the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, further includes:

comparing the second sensing potential with a second preset voltage to obtain second verification information;

comparing the third sensing potential with a third preset voltage to obtain third verification information;

Optionally, a first bit line voltage is applied to a first bit line connected to a first forced cell, a second bit line voltage is applied to a second bit line connected to a second forced cell, a program-inhibited bit line voltage is applied to a third bit line connected to the third memory cell, and a program voltage is applied to a selected word line, according to the first verification information, the second verification information, and the third verification information; the first bit line voltage is greater than a ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

Optionally, the method further comprises: storing the first verification information to a first latch in a first sensing circuit;

storing the second verification information to a second latch in a second sensing circuit;

storing the third verification information to a third latch in a third sensing circuit.

A third aspect of embodiments of the present application provides a memory system, including:

a controller and the storage device of the first aspect; the controller is coupled to the storage device and is used for controlling the storage device.

The application discloses a storage device, a verification method and a storage system, wherein the storage device comprises: the memory cell array, the memory cell in the memory cell array is arranged according to the row and the column; a sensing circuit coupled to the memory cell array, including a first sensing circuit, a second sensing circuit and a third sensing circuit coupled to the sensing node; a control logic coupled to the memory cell array and the sensing circuit, the control logic configured to precharge the sensing node to a predetermined initial voltage and to change a sensing time point so that the sensing node assumes at least three different potentials; the first sensing circuit, the second sensing circuit and the third sensing circuit respectively sense at least three different potentials of the sensing node to obtain first verification information, second verification information and third verification information. According to the embodiment of the application, after the sensing node is precharged to the preset initial voltage, the sensing node is subjected to discharging operation, and then sensing is completed on different potentials, so that the charging times of the sensing node in the sensing process are reduced, and the verification time is saved.

Drawings

Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a sensing circuit provided by an embodiment of the present application;

FIG. 3 is a first timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 4 is a second timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 5 is a third timing diagram of the voltage at the sensing node according to an embodiment of the present disclosure;

FIG. 6 is a distribution diagram of threshold voltages of memory cells according to an embodiment of the present application;

fig. 7 is a schematic flowchart of a verification method according to an embodiment of the present application;

FIG. 8 is a block diagram of a memory system shown in accordance with an exemplary embodiment;

FIG. 9A is a schematic diagram of a memory card shown in accordance with an exemplary embodiment of the present application;

fig. 9B is a schematic diagram of a Solid State Drive (SSD) according to an example embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

Furthermore, the drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the steps. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In an embodiment of the present application, a memory device includes a memory Cell array, where memory cells in the memory Cell array are arranged in rows and columns, where the memory cells may be Single-Level Cell (SLC) types, Multi-Level Cell (MLC) types, triple-Level Cell (TLC) types, Quad-Level Cell (QLC) types, five-Level Cell (Penta-Level Cell, PLC) types, or higher Level types. Each SLC cell may store 1 bit of data, each MLC cell may store 2 bits of data, each TLC cell may store 3 bits of data, each QLC cell may store 4 bits of data, and each PLC cell may store 5 bits of data. Each memory cell may hold one of Q possible data states, where Q is a positive integer equal to or greater than 2, e.g., Q-2 for SLC, Q-4 for MLC, Q-8 for TLC, Q-16 for QLC, and Q-32 for PLC. The Q possible data states may include an erased state S (0) and programmed states S (1) through S (Q-1), where programmed state S (1) is the lowest programmed state and programmed state S (Q-1) is the highest programmed state. In one example, TLC can be programmed to one of 8 possible data states, where program state S (1) is the lowest program state and program state S (7) is the highest program state.

In a program verify operation of the memory device, one verify voltage corresponds to each program state. When at least one memory cell in the same program state is to be verified, a corresponding verification voltage is applied to the selected word line WL, and whether the memory cell passes the verification is determined based on the verification voltage and a predetermined voltage of the memory cell in the program state. Considering that the predetermined voltages corresponding to the programming states of different levels are different, it is necessary to perform a plurality of verification processes, and generally, the memory cell needs to be charged to a higher potential and then a plurality of discharging operations are performed, SO that the voltage at the Sensing Node SO (SO) corresponding to the memory cell at different stages is detected by the Sensing circuit, the Sensing result can be used to complete the verification of the memory cell, and the verification result can be stored in the latch of the page buffer for determining the programming result of the memory cell.

After the memory cell performs the programming operation, a corresponding verifying operation is required, the verifying operation includes an SO discharging process, and the charge accumulated at the sensing node SO can be discharged through the bit line BL and the channel. If the total amount of discharge during the predetermined discharge period is sufficient for a significant voltage drop to occur at the sense node SO, the threshold voltage of the corresponding memory cell can be considered to be lower than the verify voltage, which indicates that the memory cell is not verified and needs to be programmed and verified again. On the other hand, if the total amount of discharge during the predetermined discharge period is small, i.e., the amount of charge or voltage remaining after discharge is higher than the predetermined voltage, it indicates that the memory cell passes verification and is restricted from programming in the next programming cycle. However, in the current verification operation, the memory cells belonging to different programming states need to be verified by using different verification voltages, and in the process of discharging the node SO of the memory cell, multiple charging operations need to be performed, which results in a complicated verification process, resulting in an excessively long verification time and affects the programming efficiency.

In view of this, an embodiment of the present application provides a memory device, please refer to fig. 1, where fig. 1 is a schematic structural diagram of the memory device provided in the embodiment of the present application, and the memory device includes:

a memory cell array 110 in which memory cells in the memory cell array 110 are arranged in rows and columns;

a sensing circuit 120 coupled to the memory cell array 110, the sensing circuit 120 including a first sensing circuit 121, a second sensing circuit 122 and a third sensing circuit 123 coupled to a sensing node SO;

a control logic 140 coupled to the memory cell array 110 and the sensing circuit 120, the control logic 140 being configured to precharge the sensing node to a predetermined initial voltage and to change a sensing time point so that the sensing node assumes at least three different potentials; the first sensing circuit 121, the second sensing circuit 122 and the third sensing circuit 123 respectively sense at least three different potentials of the sensing node to obtain first verification information, second verification information and third verification information;

Here, the control logic 140 is connected to the memory cell array 110 through the sensing circuit 120 and the row decoder 130. The sensing circuit 120, row decoder 130, and control logic 140 may be implemented in peripheral circuits of the memory device.

In the present embodiment, the memory cell array 110 may be connected to the row decoder 130 via word lines WL0 to WLn-1, cell string selection lines SSL, and ground selection lines GSL. Memory cell array 110 may also be connected to sense circuit 120 via bit lines BL 0-BLm-1. The memory cell array 120 may include a plurality of memory cell strings. Each memory cell string may be connected to a bit line via a cell string selection transistor SST. The memory cell array 110 may be formed of a memory plane (plane) including a plurality of memory blocks (blocks), each of which may include a plurality of memory pages (pages), each of which may include a plurality of memory cells (cells). In addition, although the memory device is illustrated as a flash memory device as an example, it is understood that the present application is not limited to the flash memory device and may be applied to any type of non-volatile memory, for example, a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read Only Memory (EPROM), an erasable programmable read only memory (EEPROM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Resistive Random Access Memory (RRAM), a Ferroelectric Random Access Memory (FRAM), and the like.

The sense circuit 120 may function as a write driver or as a sense amplifier depending on the mode of operation. During a program operation, the sensing circuit 120 may transmit a bit line voltage corresponding to a memory cell to be programmed to a bit line of the memory cell array 110. During a read operation, the sensing circuit 120 may sense data stored in a selected memory cell through the sensing node. The sensing circuit 120 may latch the verification data and output the verification data to the outside.

For example, the first sensing circuit may include a first latch to store the first verification information; the second sensing circuit may include a second latch to store second verification information; the third sensing circuit may include a third latch to store third verification information.

The row decoder 130 may select any one of the memory blocks of the memory cell array 110 in response to the address ADDR. The row decoder 130 may select any one of the word lines of the selected memory block. The row decoder 130 may transmit a word line voltage to a word line of a selected memory block.

The control logic 140 may receive a program command CMD and may output various control signals for controlling the sensing circuit 120 and the row decoder 130 to perform a program operation in response to the program command CMD. In addition, the control logic 140 is further configured to discharge the sensing node SO after precharging the sensing node SO to a predetermined initial voltage, change a sensing time point during the discharge of the sensing node SO to make the sensing node SO assume at least three different potentials, and compare the at least three different potentials with different preset voltages to obtain first verification information, second verification information, and third verification information. The potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential.

Fig. 2 is a circuit diagram of a sensing circuit provided in an embodiment of the present application, where the sensing circuit 120 includes a first sensing circuit, a second sensing circuit and a third sensing circuit, where the first sensing circuit includes a first latch 1211 for storing first verification information, the second sensing circuit includes a second latch 1221 for storing second verification information, and the third sensing circuit includes a third latch 1231 for storing third verification information.

In a specific example, the first latch 1211 and the second latch 1221 may store information about a bit line forcing operation (forcing operation) corresponding to different bit line voltages required to be applied to the respective bit lines during programming controlled by the program command CMD, and in the present embodiment, 4 different bit line voltages may be latched during programming by the first latch 1211 and the second latch 1221. A detailed description thereof will be described later with reference to fig. 6 and the like.

In an embodiment of the present application, the sensing circuit further includes: a first precharge circuit 124 for generating a first bit line voltage; the first precharge circuit 124 is connected to the bit line through the sense node SO; the first precharge circuit 124 is configured to apply a first bit line voltage greater than a ground voltage and less than a program-inhibited bit line voltage to a first bit line connected to the first forced cell. It should be noted that the first precharge circuit 124 is further configured to apply a program-inhibited bit line voltage to a third bit line connected to a third memory cell. Here, the third memory cell is a program-inhibited memory cell.

In an embodiment of the present application, the sensing circuit further includes: a second precharge circuit 125 for generating a second bit line voltage, the second precharge circuit 125 being connected to the bit line through the sense node SO; the second precharge circuit 125 is configured to apply a second bit line voltage greater than the first bit line voltage to a second bit line connected to the second forced cell.

It should be noted that the bit lines in the memory cell array are connected to the sensing node, the first precharge circuit and the second precharge circuit through transistors, and the bit lines can be conducted to the sensing node, the first precharge circuit and the second precharge circuit by applying bias signals to the transistors, such as VPASS-HV, VBLBIAS or VBLBIAS2, so as to program and verify the corresponding memory cells.

Fig. 3 is a first voltage timing diagram of a sensing node according to a specific example of the present application, and referring to fig. 3, a control logic is configured to precharge the sensing node to a predetermined initial voltage by applying a precharge signal Prech-sel, discharge and stop discharging the sensing node SO by a control signal Vsoblk, and discharge the sensing node SO when the control signal Vsoblk is at a high level; when the control signal Vsoblk is at a low level, the sensing node SO stops discharging. At time t1, charging the sensing node SO by applying the precharge signal Prech-sel SO that the sensing node SO reaches a predetermined initial voltage, and discharging the sensing node SO at time t2, after a first predetermined sensing time elapses, the first latch may be caused to sense first verification information according to a first sensing potential of the sensing node SO by the signal Rst _2 being 1; at time t3, the sensing node SO is charged again by applying the precharge signal Prech-sel SO to make the sensing node SO reach the predetermined initial voltage again, and the sensing node SO is discharged at time t4, after the second predetermined sensing time elapses, the second latch can be made to sense the second verification information according to the second sensing potential of the sensing node SO by the signal Rst _3 being 1; the sensing node SO is discharged again at time t5, and after the third predetermined sensing time elapses, the third latch may be caused to sense the third verification information according to the third sensing potential of the sensing node SO by the signal Set _ s being 1. Here, the first sensing potential is greater than the second sensing potential, which is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the second predetermined sensing time and the third predetermined sensing time correspond to different sensing time points.

In some embodiments, referring again to fig. 3, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; after obtaining the first verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point to make the sensing node assume at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense and obtain second verification information and third verification information according to at least two different potentials of the sensing node.

In this embodiment, obtaining the first verification information includes: comparing the first sensing potential with a first preset voltage to obtain first verification information; if the first sensing potential is greater than or equal to a first preset voltage, the first verification information is used for indicating a first storage unit passing the verification of the first verification voltage; on the contrary, if the first sensing potential is smaller than the first preset voltage, the first verification information is used for indicating the memory cells which fail to be verified by the first verification voltage. Here, the first verify voltage is a voltage for distinguishing a program state of the memory cell.

The sensing node is precharged to a predetermined initial voltage, the voltage at the sensing node is lower than the predetermined initial voltage after a discharge for a first predetermined sensing time, the sensing node is recharged to the predetermined initial voltage after first verification information is obtained, and second verification information is obtained after a discharge for a second predetermined sensing time. Here, the first predetermined sensing time and the second predetermined sensing time are different. In some embodiments, the first predetermined sensing time is less than the second predetermined sensing time.

The sensing node is charged at the initial moment and after the first sensing, at least three times of verification operations can be completed only by two times of charging operations, the charging times of the sensing node in the sensing process are reduced, and the verification time is saved.

In some embodiments, referring to fig. 4, fig. 4 is a second voltage timing diagram of a sensing node according to an embodiment of the present disclosure, where a potential of the sensing node corresponding to the first verification information is greater than a potential of the sensing node corresponding to the second verification information; after obtaining the second verification information, the control logic is further configured to recharge the sensing node to the predetermined initial voltage and change the sensing time point to make the sensing node assume at least two different potentials; the first sensing circuit and the third sensing circuit respectively sense at least two different potentials of the sensing node to obtain first verification information and third verification information.

In this embodiment, obtaining the second verification information includes: comparing the second sensing potential with a second preset voltage to obtain second verification information; if the second sensing potential is greater than or equal to a second preset voltage, the second verification information is used for indicating a second storage unit passing the verification of the second verification voltage; on the contrary, if the second sensing potential is smaller than the second preset voltage, the second verification information is used for indicating the memory cell which does not pass the verification of the second verification voltage. Here, the second verify voltage is a voltage for distinguishing a program state of the memory cell.

Referring to fig. 4, the sensing node is precharged to a predetermined initial voltage by applying the precharge signal Prech-sel, and the sensing node SO is discharged and stopped from being discharged by the control signal Vsoblk. At time t1, charging the sensing node SO by applying the precharge signal Prech-sel SO that the sensing node SO reaches the predetermined initial voltage, and discharging the sensing node SO at time t2, after a second predetermined sensing time elapses, the second latch may be caused to sense the second verification information according to the second sensing potential of the sensing node SO by the signal Rst _3 being 1; at time t3, the sensing node SO is charged again by applying the precharge signal Prech-sel SO to make the sensing node SO reach the predetermined initial voltage again, and the sensing node SO is discharged at time t4, after the first predetermined sensing time elapses, the first latch may be caused to sense the first verification information according to the first sensing potential of the sensing node SO by the signal Rst _2 being 1; at time t5, the sensing node SO is discharged again, and after the fourth predetermined sensing time elapses, the third latch can sense the third verification information according to the third sensing potential of the sensing node SO by the signal Set _ s being 1. Here, the first sensing potential is greater than the second sensing potential, which is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the second predetermined sensing time and the fourth predetermined sensing time correspond to different sensing time points.

In the embodiment, at least three verification operations can be completed only by two charging operations, so that the charging times of the sensing nodes in the sensing process are reduced, the verification time is saved, the first sensing potential with larger potential difference is discharged to the third sensing potential, the potential change is more obvious, and the sensing accuracy is improved.

In some embodiments, referring to fig. 5, fig. 5 is a third timing diagram of the voltage of the sensing node according to an embodiment of the present disclosure. The potential of the sensing node corresponding to the first verification information is larger than the potential of the sensing node corresponding to the second verification information; after obtaining the first verification information, the control logic is further configured to change the sensing time point to make the sensing node present at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense and obtain second verification information and third verification information according to at least two different potentials of the sensing node.

In the present embodiment, the sensing node is precharged to a predetermined initial voltage by applying the precharge signal Prech-sel, and the sensing node SO is discharged and stopped from being discharged by the control signal Vsoblk. At time t1, charging the sensing node SO by applying the precharge signal Prech-sel SO that the sensing node SO reaches a predetermined initial voltage, and discharging the sensing node SO at time t2, after a first predetermined sensing time elapses, the first latch may be caused to store first verification information sensed from the first sensing potential of the sensing node SO by the signal Rst _2 being 1; discharging the sensing node SO again at time t3, and after a fifth predetermined sensing time, sensing the second verification information by the second latch according to the second sensing potential of the sensing node SO by the signal Rst _3 being 1; at time t4, the sensing node SO is discharged again, and after the third predetermined sensing time elapses, the third latch can sense the third verification information according to the third sensing potential of the sensing node SO by the signal Set _ s being 1. Here, the first sensing potential is greater than the second sensing potential, which is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the fifth predetermined sensing time and the third predetermined sensing time correspond to different sensing time points.

It should be noted that fig. 3-5 illustrate an example of changing the sensing time point to make the sensing node assume three different potentials.

According to the embodiment of the application, the sensing node is charged at the initial moment, at least three times of verification operations on the sensing node can be completed only by one-time charging operation, the charging times of the sensing node in the sensing process are reduced, the verification time is saved, and the programming efficiency is improved.

In this embodiment, taking an ISPP (Incremental Step-Pulse Programming) Programming scheme of a 3D NAND flash memory device as an example, in different Programming stages of an ISPP Programming process, in order to optimize threshold voltage distribution and relatively more intensively distribute the threshold values of the memory cells in the threshold voltage regions of the corresponding data states, bit lines of the memory cells of different bit lines are biased by different bit line voltages, i.e. bit line forcing operation (forcing operation) is implemented, so that even though the Programming voltages Vpgm of the gates (applied by word lines) of the memory cells of different bit lines are the same, the Programming effect is different, and the threshold voltage difference of the memory cells with larger threshold voltage difference after being programmed is reduced and relatively approaches to the ideal threshold voltage region of the corresponding data state.

FIG. 6 is a distribution diagram of threshold voltages of memory cells according to an embodiment of the present application. Here, Vfc1 is a first verify voltage, Vfc2 is a second verify voltage, and Vvfy is a third verify voltage. Referring to fig. 6, the first latch may include first verification information DL corresponding to the first verification voltage Vfc1 as force information for the first force operation. The first verify voltage Vfc1 may be less than the third verify voltage Vvfy. In example embodiments of the present application, a memory cell having a voltage greater than the first verify voltage Vfc1 is a first memory cell that passes the verification of the first verify voltage, a memory cell having a voltage greater than the second verify voltage Vfc2 is a second memory cell that passes the verification of the second verify voltage, and a memory cell having a voltage greater than the third verify voltage Vvfy is a third memory cell that passes the verification of the third verify voltage. The memory cells having the threshold voltages greater than the first verify voltage Vfc1 and less than the third verify voltage Vvfy may be memory cells to be forced, where the memory cells to be forced include a first Forcing Cell (Forcing Cell) and a second Forcing Cell, while the memory cells having the threshold voltages greater than the first verify voltage Vfc1 and less than the second verify voltage Vfc2 may be first Forcing cells to be first forced, and the memory cells having the threshold voltages greater than the second verify voltage Vfc2 and less than the third verify voltage Vvfy may be second Forcing cells to be second forced. The storage unit of the first storage unit except the second storage unit and the third storage unit is a first forcing unit to be subjected to a first forcing operation. In other words, the first memory cell includes a first forced cell to be subjected to a first forced operation, a second forced cell to be subjected to a second forced operation, and a third memory cell to be inhibited from programming. When the threshold voltage is greater than the first verification voltage Vfc1, the second latch may store "1" as the first verification information DL. Also, the memory cell having a threshold voltage smaller than the first verify voltage Vfc1 is a program cell rather than a forced cell, and the first latch may store "0" as the first verify information DL.

The second latch may include second verification information DM corresponding to the second verification voltage Vfc2 as force information for the second force operation. The second verify voltage Vfc2 may be less than the third verify voltage Vvfy and greater than the first verify voltage Vfc 1. In example embodiments of the present application, memory cells having threshold voltages greater than the second verify voltage Vfc2 and less than the third verify voltage Vvfy may be memory cells to be subjected to a second force operation, referred to herein as second force cells. In other words, the second memory cell includes a second forced cell to which the second forced operation is to be performed and a third memory cell to which the program is to be inhibited. When the threshold voltage is greater than the second verification voltage Vfc2, the second latch may store "1" as the second verification information DM. Also, the memory cell having a threshold voltage smaller than the second verification voltage Vfc2 is a memory cell that does not perform the second forced operation, the second latch may store "0" as the second verification information DM.

The third latch may store third verify information DS corresponding to the third verify voltage Vvfy. In example embodiments of the present application, the memory Cell having a threshold voltage greater than the third verify voltage Vvfy may be an Inhibiting Cell (Inhibiting Cell), referred to herein as a third memory Cell, and the third latch may store "1" as the third verify information DS. Also, the memory Cell having a threshold voltage level smaller than the third verify voltage Vvfy may be a program Cell (PGM Cell), and the third latch may store "0" as the third verify information. In other words, the program unit includes a memory unit performing a normal program operation, a first forced unit, and a second forced unit. Note that the third verify voltage Vvfy may also be referred to as a program verify voltage Vvfy.

The first latch may store information to distinguish a memory cell to be subjected to a bit line force operation and a memory cell to be subjected to a program inhibit operation, i.e., distinguishing information to distinguish a memory cell to be subjected to a normal program operation and a memory cell to be subjected to a bit line force operation and a program inhibit operation from each other, among memory cells based on the first verify voltage Vfc 1.

The second latch may store information used to distinguish a memory cell to be subjected to the second forced operation and a memory cell to be subjected to the program inhibit operation, that is, distinguishing information that a memory cell to be subjected to the normal program operation and the first forced operation and a memory cell to be subjected to the second forced operation and the program inhibit operation are distinguished from each other, among memory cells, based on the second verifying voltage Vfc 2.

The third latch may latch information to distinguish a memory cell to be subjected to a program inhibit operation among memory cells, i.e., distinguishing information to distinguish a memory cell to be subjected to a program operation and a memory cell to be subjected to a program inhibit operation from each other, based on the third verify voltage Vvfy.

In this embodiment, based on the first verification information, the second verification information, and the third verification information, a programming method of forcibly operating two bit lines for different memory cells in one programming process can be implemented, and thus, the memory cells can be prevented from being over-programmed, thereby reducing the width of threshold voltage distribution of the plurality of memory cells and improving the accuracy of the programming operation.

In some embodiments, the control logic is further configured to: applying a first bit line voltage to a first bit line connected to the first forcing unit, applying a second bit line voltage to a second bit line connected to the second forcing unit, applying a program-inhibited bit line voltage to a third bit line connected to the third memory unit, and applying a program voltage to a selected word line, according to the first verification information, the second verification information, and the third verification information; the first bit line voltage is greater than the ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forcing unit is a storage unit other than the second storage unit and the third storage unit in the first storage unit; the second forcing unit is a storage unit except the third storage unit in the second storage unit. In some embodiments, the control logic is further configured to: according to the first, second, and third verification information, a normal program bit line voltage Vprog (e.g., a ground voltage Vgnd) is applied to the memory cells performing a normal program operation. Here, the program-inhibited bit line voltage Vinh may be a power supply voltage Vdd, the first bit line voltage being greater than a ground voltage (normal program bit line voltage Vprog) and less than the program-inhibited bit line voltage Vinh, and the second bit line voltage being greater than the first bit line voltage and less than the program-inhibited bit line voltage Vinh.

In some embodiments, the first forcing unit is a storage unit of the first storage unit other than the second storage unit and the third storage unit; the second forcing unit is a storage unit in the second storage unit except the third storage unit.

In a program process such as ISPP, when a program operation is performed by applying a same program voltage Vpgm to memory cells of a selected row, the sensing circuit may apply a corresponding bit line voltage to the corresponding memory cells using first verification information DL, second verification information DM, and third verification information DS, so that the memory cells may be distinguished from a bit line forcing operation. In other words, in the present embodiment, the classified program control is performed on the different memory cells, the memory cells may be classified into the normal program cell, the first forced cell to be subjected to the first bit line forcing operation, the second forced cell to be subjected to the second bit line forcing operation, and the third memory cell to be subjected to the program inhibiting operation, and the classified program control is performed on the 4 types of memory cells using different bit line voltages.

During the program operation, if only one forced bit line voltage (which is greater than the normal program bit line voltage Vprog and less than the program-inhibited bit line voltage Vinh) is added to perform the program operation on the plurality of forced cells in addition to the two bit line voltages of the program-inhibited bit line voltage Vinh (e.g., Vdd) and the normal program bit line voltage Vprog (e.g., ground voltage Vgnd), although a program operation having a certain differentiation in the degree of programming may be achieved, the threshold voltage distribution of the plurality of memory cells after being programmed may not be sufficiently narrow. Therefore, in the program operation of the present embodiment, in addition to using both the program inhibited bit line voltage Vinh (e.g., VDD) and the normal program bit line voltage Vprog (e.g., ground voltage Vgnd), a program operation with a finer program level differentiation is performed on a plurality of memory cells using the first bit line voltage and the second bit line voltage, both of which are greater than the normal program bit line voltage Vprog and less than the program inhibited bit line voltage Vinh.

In some embodiments, the information stored in the corresponding latch may also be updated based on the verify results of the memory cell. Specifically, the information stored in the first latch is updated according to the first verification information of the storage unit; updating the information stored in the second latch according to the second verification information of the storage unit; and updating the information stored in the third latch according to the third verification information of the storage unit.

An embodiment of the present application provides a verification method, please refer to fig. 7, where fig. 7 is a schematic flowchart of the verification method provided in the embodiment of the present application, and the verification method includes:

s701, precharging a sensing node to a preset initial voltage;

s702, changing the sensing time point to make the sensing node present at least three different potentials;

s703, controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense at least three different potentials of the sensing node to obtain first verification information, second verification information, and third verification information, respectively.

The method includes the steps of discharging a sensing node SO after the sensing node SO is precharged to a preset initial voltage based on control information, changing a sensing time point during the discharging of the sensing node SO to enable the sensing node SO to present at least three different potentials, and comparing the at least three different potentials with different preset voltages to obtain first verification information, second verification information and third verification information. The potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential.

In one example, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; after the first verification information is obtained, the sensing node is charged again to a predetermined initial voltage, and a sensing time point is changed to make the sensing node assume at least two different potentials, whereby second verification information and third verification information can be obtained.

In another example, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; after the second verification information is obtained, the sensing node is charged again to a predetermined initial voltage, and a sensing time point is changed to make the sensing node assume at least two different potentials, whereby the first verification information and the third verification information can be obtained.

The sensing node is charged at the initial moment and after the first sensing, the verification operation can be completed for three times only by two charging operations, the charging times of the sensing node in the sensing process is reduced, and the verification time is saved.

In some embodiments, the changing a sensing time point to cause the sensing node to assume at least three different potentials includes: discharging the sensing node after precharging the sensing node to a predetermined initial voltage, and changing a sensing time point during the discharging of the sensing node to enable the sensing node to present at least three different potentials; the potential of the sensing node corresponding to the first verification information is a first sensing potential; the potential of the sensing node corresponding to the second verification information is a second sensing potential; the potential of the sensing node corresponding to the third verification information is a third sensing potential.

In some embodiments, the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, includes: comparing the first sensing potential with a first preset voltage to obtain first verification information; if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used for indicating the first memory cell passing the verification of the first verification voltage.

In some embodiments, the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, further includes: comparing the second sensing potential with a second preset voltage to obtain second verification information; and if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used for indicating a second storage unit passing the verification of the second verification voltage.

In some embodiments, the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, further includes: comparing the third sensing potential with a third preset voltage to obtain third verification information; wherein if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used for indicating a third memory cell that passes verification of the third verification voltage.

In some embodiments, the first verify voltage is less than the second verify voltage, which is less than the third verify voltage.

In this embodiment, the memory cell with the threshold voltage greater than the first verification voltage and less than the third verification voltage is the first forcing unit, the memory cell with the threshold voltage greater than the second verification voltage and less than the third verification voltage is the second forcing unit, and the memory cell with the threshold voltage greater than the third verification voltage is the inhibiting unit, and the programming operation is not performed.

In some embodiments, a first bit line voltage is applied to a first bit line connected to a first forced cell, a second bit line voltage is applied to a second bit line connected to a second forced cell, a program-inhibited bit line voltage is applied to a third bit line connected to a third memory cell, and a program voltage is applied to a selected word line, according to first, second, and third verification information; the first bit line voltage is greater than the ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forcing unit is a storage unit other than the second storage unit and the third storage unit in the first storage unit; the second forcing unit is a storage unit except the third storage unit in the second storage unit.

In some embodiments, the first verification information is stored to a first latch in a first sensing circuit; storing the second verification information to a second latch in a second sensing circuit; storing the third verification information to a third latch in a third sensing circuit.

In some embodiments, as shown in FIG. 8, FIG. 8 is a block diagram of a memory system shown herein according to an exemplary embodiment. The memory system may be applied to a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. The host 801 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) that may be an electronic device. The device 802 may be a memory system of an electronic device having a controller 804 and one or more storage 803.

In some embodiments, a controller 804 is coupled to the storage 803 and the host 801 and is configured to control the storage 803. Storage 803 (e.g., a NAND flash memory device) may store more than a single bit of information into each memory cell in multiple levels (also referred to as states) in order to increase storage capacity and reduce cost per bit. The controller 804 may manage data stored in the storage 803 and communicate with the host 801. In some implementations, the controller 804 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the controller 804 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. The controller 804 may be configured to control operations (e.g., read, erase, and program operations) of the storage device 803. The controller 804 may also be configured to manage various functions with respect to data stored or to be stored in the storage 803, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the controller 804 is also configured to process an Error Correction Code (ECC) with respect to data read from the storage 803 or written to the storage 803. The controller 804 may also perform any other suitable function, such as formatting the storage 803. The controller 804 may communicate with an external device (e.g., the host 601) according to a particular communication protocol. For example, the controller 804 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, a Multi Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Fi rewire protocol, and the like.

The embodiment of the application also provides a memory system, which comprises a controller and the memory device; the controller is coupled to the storage device and is used for controlling the storage device.

The storage device and the one or more storage devices may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system may be implemented and packaged into different types of end electronic products.

In one example, as shown in FIG. 9A, a controller 804 and a single storage 803 may be integrated into a memory card 900 a. The memory card 900a may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, mini SD, microSD, SDHC), a UFS, and the like.

In another example, as shown in fig. 9B, controller 804 and plurality of storage 803 may be integrated into SSD 900B. In some embodiments, the storage capacity and/or operating speed of SSD900b is greater than the storage capacity and/or operating speed of memory card 900 a.

Of course, in other examples, the memory system may also include multiple storage devices and a corresponding plurality of controllers, which are not enumerated.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and other division manners may be implemented in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other forms.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network modules; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional modules in the embodiments of the present application may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module; the integrated module can be realized in a hardware form, and can also be realized in a form of hardware and a software functional module.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory device, comprising:

2. The memory device according to claim 1, wherein a potential of the sense node corresponding to the first verification information is larger than a potential of the sense node corresponding to the second verification information;

3. The memory device according to claim 1, wherein a potential of the sense node corresponding to the first verification information is larger than a potential of the sense node corresponding to the second verification information;

4. The memory device according to claim 2 or 3, wherein the control logic is specifically configured to discharge the sensing node after precharging the sensing node to a predetermined initial voltage, change a sensing time point during the discharge of the sensing node to make the sensing node assume at least three different potentials;

5. The storage device of claim 4, wherein the control logic is further configured to: comparing the first sensing potential with a first preset voltage to obtain first verification information;

6. The storage device of claim 5, wherein the control logic is further configured to: comparing the second sensing potential with a second preset voltage to obtain second verification information;

7. The storage device of claim 6, wherein the control logic is further configured to: comparing the third sensing potential with a third preset voltage to obtain third verification information;

8. The memory device of claim 7, wherein the first verify voltage is less than the second verify voltage, and wherein the second verify voltage is less than the third verify voltage.

9. The storage device of claim 8,

the control logic is further configured to: applying a first bit line voltage to a first bit line connected to a first forced cell, applying a second bit line voltage to a second bit line connected to a second forced cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first, second, and third verification information; the first bit line voltage is greater than a ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

10. The storage device of claim 9,

the first forcing unit is a storage unit except the second storage unit and the third storage unit in the first storage unit;

11. The memory device according to claim 1, wherein the first sensing circuit includes a first latch for storing the first verification information; the second sensing circuit comprises a second latch for storing the second verification information; the third sensing circuit includes a third latch for storing the third verification information.

12. A method of authentication, comprising:

precharging a sensing node to a predetermined initial voltage;

13. The verification method according to claim 12, wherein a potential of the sense node corresponding to the first verification information is larger than a potential of the sense node corresponding to the second verification information; the controlling the first sensing circuit, the second sensing circuit and the third sensing circuit to obtain first verification information, second verification information and third verification information according to at least three different potentials of the sensing node respectively comprises:

14. The verification method according to claim 12, wherein a potential of the sense node corresponding to the first verification information is larger than a potential of the sense node corresponding to the second verification information; the controlling the first sensing circuit, the second sensing circuit and the third sensing circuit to obtain first verification information, second verification information and third verification information according to at least three different potentials of the sensing node respectively comprises:

15. The verification method according to claim 13 or 14, wherein the changing of the sensing time point to cause the sensing node to assume at least three different potentials comprises:

16. The method of claim 15, wherein the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, comprises:

17. The method of claim 16, wherein the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, further comprises:

18. The method of claim 17, wherein the controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information according to at least three different potentials of the sensing node, respectively, further comprises:

19. The method of claim 18, wherein the first verify voltage is less than the second verify voltage, and wherein the second verify voltage is less than the third verify voltage.

20. The authentication method of claim 19, further comprising:

applying a first bit line voltage to a first bit line connected to a first forced cell, applying a second bit line voltage to a second bit line connected to a second forced cell, applying a program-inhibited bit line voltage to a third bit line connected to the third memory cell, and applying a program voltage to a selected word line, according to the first, second, and third verification information; the first bit line voltage is greater than a ground voltage and less than the program-inhibited bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

21. The authentication method according to claim 20,

the first forcing unit is a storage unit in the first storage unit except the second storage unit and the third storage unit;

22. The authentication method of claim 12, further comprising:

storing the first verification information to a first latch in a first sensing circuit;

23. A memory system comprising a controller and the memory device of any one of claims 1 to 11; the controller is coupled to the storage device and is used for controlling the storage device.