CN115148155A

CN115148155A - Display panel and display device

Info

Publication number: CN115148155A
Application number: CN202210970041.8A
Authority: CN
Inventors: 王亚威; 张鼎
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2022-10-04
Anticipated expiration: 2041-03-22
Also published as: CN113053309A; CN113053309B

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel includes a pixel circuit including a first pixel circuit and a second pixel circuit; the first region includes a first pixel circuit, the second region includes a second pixel circuit, and the first pixel circuit and the second pixel circuit are electrically connected to the light emitting device, respectively; the density of the first pixel circuits in the first region is less than the density of the second pixel circuits in the second region; the first area is provided with a dummy hole, and the dummy hole at least penetrates through part of the film layer in the display panel. The dummy holes can be used as a hydrogen gas discharge channel, so that the difference between the transistor characteristics in the first pixel circuit and the transistor characteristics in the second pixel circuit is reduced, and the display unevenness of the display panel is improved.

Description

Display panel and display device

The application is a divisional application with an application date of 2021, 03 and 22 months, an application number of 202110300575.5, and a name of "display panel and display device".

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

Organic Light-Emitting diodes (OLEDs) have the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed, and become one of the research hotspots in the display field at present. Organic light emitting diodes are used as current driving devices in the display field, and complex pixel circuits are required to be arranged for providing driving current for the light emitting diodes so as to control the light emission of the light emitting diodes. In the prior art, for example, in a scheme of a camera under a screen or a scheme of a display area having a hole, there may be areas with different pixel circuit arrangement densities in a display panel, and due to the influence of a manufacturing process, there may be differences in basic characteristics of thin film transistors in the areas with different pixel circuit densities, which shows that display unevenness may occur in display performance.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, and aims to solve the technical problem of uneven display in the prior art.

In a first aspect, an embodiment of the present invention provides a display panel, including:

a pixel circuit including a first pixel circuit and a second pixel circuit;

the first region includes a first pixel circuit, the second region includes a second pixel circuit, and the first pixel circuit and the second pixel circuit are electrically connected to the light emitting device, respectively; the density of the first pixel circuits in the first region is less than the density of the second pixel circuits in the second region;

the first area is provided with a dummy hole, and the dummy hole penetrates through at least part of the film layer in the display panel;

the first region includes a transition region and a semi-transmissive region, the transition region is located between the second region and the semi-transmissive region, the first pixel circuit is located in the transition region, wherein the dummy hole is disposed in the semi-transmissive region.

In a second aspect, an embodiment of the present invention further provides a display device, including the display panel provided in any embodiment of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: in the first area with lower pixel circuit density, the dummy hole is arranged and penetrates through part of the film layer in the display panel, and the dummy hole is not used for connecting circuit components, so that in the hydrogenation process, the dummy hole can be used as a channel of a transistor in the first pixel circuit and a channel for discharging hydrogen in the grid insulating layer, thereby increasing the channels for discharging hydrogen in the first area, reducing the difference between the characteristics of the transistors in the pixel circuits in the two areas caused by the different pixel circuit densities in the two areas, and improving the phenomenon of uneven display.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on the drawings without inventive labor.

Fig. 1 is a partial schematic view of a display panel according to an embodiment of the invention;

fig. 2 is a schematic structural diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a first area layout of a display panel according to an embodiment of the present invention;

FIG. 4 isbase:Sub>A schematic cross-sectional view taken at line A-A' of FIG. 3;

FIG. 5 is another schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 6 is a schematic cross-sectional view taken along line B-B' of FIG. 3;

FIG. 7 is another cross-sectional view taken at line B-B' of FIG. 3;

FIG. 8 is another schematic cross-sectional view taken along line B-B' of FIG. 3;

FIG. 9 is a partial view of a first area of another display panel according to an embodiment of the present invention;

FIG. 10 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 11 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 12 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 13 is a simplified diagram illustrating a portion of a first region of a display panel according to an embodiment of the present invention;

FIG. 14 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 15 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 16 is a simplified partial schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 18 is a pixel circuit layout diagram in a first area of another display panel according to an embodiment of the present invention;

fig. 19 is a schematic view of a display device according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The embodiment of the invention provides a display panel which can be applied to the schemes that a display screen is provided with a blind hole or the display screen is provided with a through hole, a camera (or other optical components) under the screen and the like. Dummy holes are arranged in the area of the display panel with smaller pixel circuit density, the dummy holes can be used as a hydrogen discharge channel, the difference between transistor characteristics in the areas with different pixel circuit density can be reduced, and the display unevenness of the display panel can be improved.

Fig. 1 is a partial schematic view of a display panel according to an embodiment of the invention. Fig. 2 is a schematic structural diagram of a pixel circuit in a display panel according to an embodiment of the present invention, and fig. 3 is a schematic layout diagram of a first region in a display panel according to an embodiment of the present invention. Fig. 4 isbase:Sub>A schematic cross-sectional view of fig. 3 at the position of linebase:Sub>A-base:Sub>A'.

As shown in fig. 1, the display panel includes a first area A1 and a second area A2, the first area A1 includes a first pixel circuit 10a (only simplified illustration in the figure), the second area A2 includes a second pixel circuit 10b (only simplified illustration in the figure), and the first pixel circuit 10a and the second pixel circuit 10b are respectively electrically connected to a light emitting device (not illustrated in the figure); the density of the first pixel circuits 10a in the first area A1 is smaller than the density of the second pixel circuits 10b in the second area A2. That is, in the embodiment of the present invention, there is a difference between the pixel circuit arrangement density in the first area A1 and the pixel circuit arrangement density in the second area A2.

In an embodiment, the density of the pixel circuits in the first area A1 is set to be smaller than the density of the pixel circuits in the second area A2, so that the light transmittance of the first area A1 can be increased, and when the scheme is applied to an under-screen camera, the camera is set to correspond to the first area A1 when the display device is assembled. In another embodiment, the display panel has a through hole penetrating through the display panel in the thickness direction of the display panel, the area where the through hole is located is the first area A1, and when the display device is assembled, a camera, a receiver and other devices can be arranged in the through hole. In another embodiment, the display panel has a blind hole, the light emitting device may not be disposed in the blind hole region, the blind hole region does not perform display, the region where the blind hole is located is the first region A1, and when the display device is assembled, the optical device may be disposed under the first region A1.

As illustrated in fig. 1, the first area A1 has dummy holes Vo, and the arrangement of the dummy holes Vo in fig. 1 is only schematically illustrated and is not intended to limit the present invention. In the embodiment of the invention, the dummy hole Vo at least penetrates through a part of the film layer in the display panel.

The display panel is in a multi-film layer stacked structure, and the dummy holes Vo defined in the embodiment of the invention are film layer through holes which are not used for connecting circuit components. The circuit components interconnected in the pixel circuits may be located in different structural layers of the display panel, and vias may need to be made in the insulating layer in order to achieve electrical connection between them. A true hole is included in the pixel circuit for connection of circuit components.

Fig. 2 illustrates a structure of a pixel circuit, and the same circuit structure can be used for both the first pixel circuit 10a and the second pixel circuit 10 b. Fig. 3 illustrates the wiring of the pixel circuit in the first region A1, and the wiring of the pixel circuit in the display panel is understood in conjunction with fig. 2 and 3.

As shown in fig. 2 and 3, the pixel circuit 10 includes a driving transistor Tm, a data writing transistor T1, a threshold compensation transistor T2, a gate reset transistor T3, an electrode reset transistor T4, a first light emission control transistor T5, and a second light emission control transistor T6. The display panel includes first scan lines S1, second scan lines S2, light emission control signal lines E, power signal lines P, reset signal lines Ref, and data lines D. A control end of the gate reset transistor T3 is electrically connected to the first scan line S1, a first pole of the gate reset transistor T3 is electrically connected to the reset signal line Ref, a second pole of the gate reset transistor T3 is connected to the first node N1, and a control end of the driving transistor Tm is connected to the first node N1. The control terminal of the data writing transistor T1 is connected to the second scan line S2, the first pole thereof is connected to the data line D, the second pole thereof is connected to the second node N2, and the first pole of the driving transistor Tm is connected to the second node N2. The control terminal of the threshold compensating transistor T2 is connected to the second scan line S2, the first pole thereof is connected to the third node N3, the second pole of the driving transistor Tm is connected to the third node N3, and the second pole of the threshold compensating transistor T2 is connected to the first node N1. A control terminal of the first light emission controlling transistor T5 and a control terminal of the second light emission controlling transistor T6 are both connected to the light emission control signal line E, a first pole of the first light emission controlling transistor T5 is connected to the power signal line P, and a second pole of the first light emission controlling transistor T5 is connected to the second node N2; a first pole of the second light emission controlling transistor T6 is connected to the third node N3, and a second pole of the second light emission controlling transistor T6 is connected to a first electrode of the light emitting device. A control terminal of the electrode reset transistor T4 is connected to the second scan line S2, a first pole of the electrode reset transistor T4 is connected to the reset signal line Ref, and a second pole of the electrode reset transistor T4 is connected to the first electrode of the light emitting device.

Fig. 2 schematically shows only the circuit configuration of the first pixel circuit, which is not intended to limit the present invention. The transistors in the pixel circuit structure diagram shown in fig. 2 are all illustrated as P-type, and the types of the transistors in the pixel circuit are not limited in the present invention. In addition, in the pixel circuit wiring illustrated in fig. 3, both the threshold compensation transistor T2 and the gate reset transistor T3 are double-gate transistors.

As illustrated in fig. 2 and 3, the pixel circuit further includes a first capacitor Co, a first plate of which is electrically connected to the power signal line P, a second plate of which is connected to a fourth node N4, the fourth node N4 being an intermediate node of two of the threshold compensation transistors T2. The first capacitor Co can stabilize the potential of the fourth node N4, and when the pixel circuit operates in a light-emitting stage, the leakage current of the threshold compensation transistor T2 to the first node N1 can be reduced, so that the potential of the first node N1 is stabilized, and the stability of the driving current is ensured.

Fig. 3 illustrates the dummy aperture Vo and the real aperture K, wherein the relative positions of the dummy aperture Vo and the first pixel circuit 10a are only schematically shown, and the relationship between the size of the dummy aperture Vo and the size of the real aperture K is not limited. The true hole K in the pixel circuit 10 is an opening of an insulating layer in the array layer, the true hole K is used for connecting a circuit component, such as a true hole K1 illustrated in the figure, and the true hole K1 is used for electrically connecting a transistor in the pixel circuit with a first electrode of a light emitting device.

The pixel circuit wiring pattern illustrated in fig. 3 corresponds to a structure in which only the array layer is illustrated, and the cross-sectional view illustrated in fig. 4 shows a film layer structure in the thickness direction of the display panel. As shown in fig. 4, the display panel includes a substrate 1 and an array layer 2, a pixel circuit 10 is located on the array layer 2, the array layer 2 at least includes a semiconductor layer 11, a first functional metal layer 12, a second functional metal layer 13 and a third functional metal layer 14, which are located on the substrate 1, wherein active layers of transistors in the pixel circuit 10 and connection lines between some of the transistors are located on the semiconductor layer 11, the first scan line S1, the second scan line S2, a light emission control signal line E is located on the first functional metal layer 12, one plate of a pixel capacitor Cst, and a reset signal line Ref is located on the second functional metal layer 13, and a power signal line P and a data line D are located on the third functional metal layer 14. The dummy hole Vo illustrated in fig. 4 penetrates the insulating layer in contact with the third functional metal layer 14 and extends in the direction of the semiconductor layer 11. The figure shows a first connecting line X1, the first connecting line X1 is located on the third functional metal layer 14, one end of the first connecting line X1 is connected to the first pole of the electrode reset transistor T4, and the other end of the first connecting line X1 is connected to the reset signal line Ref, so that the first pole of the electrode reset transistor T4 is electrically connected to the reset signal line Ref.

The display panel further comprises a display layer 3, an encapsulation structure 4 and a cover plate layer 5 on top of the array layer 2. The display layer 3 includes a pixel defining layer (not shown in the drawings) for spacing adjacent light emitting devices 31 and the light emitting devices 31. In one embodiment, light emitting device 31 is an organic light emitting device; in another embodiment, the light emitting device 31 is an inorganic light emitting device. The light emitting device 31 includes a first electrode 31a, a light emitting layer 31b, and a second electrode 31c, which are sequentially stacked. The second pole of the transistor in the pixel circuit is electrically connected to the first electrode 31a through the real hole K1. Specifically, the first electrode 31a is a reflective electrode, and the second electrode 31c is a transparent electrode.

In one embodiment, the package structure 4 is a rigid package, and the package structure 4 includes a package cover. In another embodiment, the encapsulation structure 4 is a flexible encapsulation, and the encapsulation structure 4 comprises at least one inorganic encapsulation layer and at least one organic encapsulation layer arranged in a stack.

With continued reference to the first capacitor Co structure illustrated in fig. 3, a first plate (not labeled) of the first capacitor Co is located on the second functional metal layer 13, that is, the first plate of the first capacitor Co and the reset signal line Ref are located on the same layer. The first plate of the first capacitor Co is connected to the power signal line P through a real hole K2, and the first plate of the first capacitor Co overlaps with a portion of the semiconductor layer, which is multiplexed as the second plate of the first capacitor Co.

Fig. 3 illustrates a pixel circuit structure including 9 true holes K in total. In some embodiments, the first capacitor is not included in the pixel circuit structure, and the pixel circuit includes 8 real holes in total. That is, the number of true holes in the pixel circuit is related to the way the pixel circuit is routed in the display panel. In the manufacturing process of the display panel, the true holes in the pixel circuits can be used as a hydrogen gas exhaust channel, and the density of the first pixel circuits in the first area A1 is less than that of the second pixel circuits in the second area A2, so that the density of the true holes in the first area A1 is less than that of the true holes in the second area A2. The hydrogen content of the channel of the transistor and the hydrogen content of the gate insulating layer in the first pixel circuit 10a are different from the hydrogen content of the channel of the transistor and the hydrogen content of the gate insulating layer in the second pixel circuit 10b after the hydrogenation process for display panel fabrication, thereby causing a difference between the characteristics of the transistor in the first pixel circuit 10a and the characteristics of the transistor in the second pixel circuit 10 b. In the embodiment of the invention, the dummy hole Vo is arranged in the first area A1, the dummy hole Vo penetrates through a part of the film layers in the display panel, and the dummy hole Vo is not used for connecting circuit components, so that in the hydrogenation process, the dummy hole Vo can be used as a channel of the transistor in the first pixel circuit 10a and a channel for discharging hydrogen in the gate insulating layer, thereby increasing the channel for discharging hydrogen in the first area A1, reducing the difference between the characteristics of the transistor in the first pixel circuit 10a and the characteristics of the transistor in the second pixel circuit 10b caused by the density difference of the pixel circuits in the two areas, and improving the phenomenon of uneven display.

In a display panel provided by an embodiment of the present invention, a first pixel circuit is electrically connected to a light emitting device, and a second pixel circuit is electrically connected to a light emitting device.

In another display panel provided by the embodiment of the invention, one first pixel circuit is electrically connected with two light emitting devices, and one second pixel circuit is electrically connected with two light emitting devices.

Fig. 4 illustrates only one structure of the dummy holes Vo. Based on the design concept of the present invention, the dummy holes Vo may penetrate through a portion of the film layers in the array layer 2, or the dummy holes Vo penetrate through a portion of the film layers in the display layer 3. In addition, in the embodiment of the present invention, the arrangement position and the arrangement density of the dummy holes Vo in the first area A1 are also designed. The following examples are given by way of illustration.

Specifically, the display panel provided by the embodiment of the invention includes a first functional layer located on one side of the semiconductor layer 11 away from the substrate 1, and the dummy hole Vo penetrates through the first functional layer and extends towards the direction of the substrate 1. In the fabrication of the display panel, a substrate 1 is provided, and then an array layer 2, a display layer 3, and other structures are sequentially fabricated on the substrate 1. The dummy hole Vo is disposed above the semiconductor layer 11, and the dummy hole Vo of A1 in the first region can serve as a path for discharging hydrogen in the hydrogenation process, so that a difference between characteristics of the transistor in the first pixel circuit and characteristics of the transistor in the second pixel circuit can be reduced, and a display unevenness phenomenon can be improved. In the embodiment of the present invention, the first functional layer may be any one of the insulating layers in the array layer, or the first functional layer may be a pixel defining layer in the display layer or an electrode layer in the display layer.

In some embodiments, the first functional layer is located on the side of the light emitting device 31 close to the substrate 1. The dummy holes Vo are arranged below the film layer where the light emitting devices 31 are located, the dummy holes Vo are close to the semiconductor layer 11, the structures above the display layer and the display layer cannot be affected by the manufacturing of the dummy holes Vo, the dummy holes Vo can be manufactured in the same process of the real holes in the pixel circuits, and the process is simple.

Specifically, as shown in fig. 4, the display panel further includes a first metal layer M1, where the first metal layer M1 is a metal layer closest to the light emitting device 31 on a side close to the substrate 1; the third functional metal layer 14 is multiplexed into the first metal layer M1. The first functional layer G is in contact with the first metal layer M1; the first functional layer G is located on a side of the first metal layer M1 close to the substrate 1, that is, the first functional layer G is an insulating layer on the side of the first metal layer M1 close to the substrate 1. An array layer 2 is manufactured on a substrate 1, pixel circuits are positioned in the array layer 2, the array layer 2 comprises conductive layers and insulating layers positioned between the adjacent conductive layers, wherein the conductive layers comprise metal layers and semiconductor layers, and the conductive layers and the insulating layers can be called functional layers.

In the pixel circuit, some transistors do not need to be connected through a real hole, for example, the first pole of the threshold compensation transistor T2 and the first pole of the second emission control transistor T6 are both located in the semiconductor layer 11, and the connection between the two poles does not need a via hole.

While some transistor-to-transistor connections or transistor-to-signal line connections need to be made through the real aperture K, such as the second pole of the threshold compensation transistor T2 electrically connected to the control terminal of the driving transistor Tm. The control terminal (i.e. the gate) of the driving transistor Tm is located on the first functional metal layer 12, the second pole of the threshold compensation transistor T2 is located on the semiconductor layer 11, and when the array layer 2 is fabricated, an opening is not directly fabricated on the insulating layer below the first functional metal layer 12 and is connected to the second pole of the threshold compensation transistor T2. As the second connection line X2 illustrated in fig. 3, the second connection line X2 is respectively connected to the second pole of the threshold compensation transistor T2 and the control terminal of the driving transistor Tm through one real hole K to realize electrical connection between the second pole of the threshold compensation transistor T2 and the control terminal of the driving transistor Tm. The second connection line X2 is located in the first metal layer M1, and a punching process for manufacturing the insulating layer is performed before the process of the first metal layer M1. The second connection line X2 is equivalent to a bridge line for connecting circuit components located on different metal layers. The bridge line is located on the metal layer closest to the light emitting device 31 above the substrate 1.

In the display panel provided by the embodiment of the invention, the bridge line in the pixel circuit is connected to the real hole K of the circuit component, the first pole of the transistor is connected to the real hole K of the signal line, and the second pole of the transistor is connected to the real hole K of the light-emitting device 31, which can be manufactured in the same punching process, so that the punching process is saved. In the embodiment of the present invention, the dummy via Vo is disposed to penetrate through the first functional layer G and extend toward the substrate 1, the first functional layer G is located on one side of the first metal layer M1 close to the substrate 1, and the first metal layer M1 is a metal layer on the substrate 1 and closest to the light emitting device 31, so that the dummy via Vo and the real via K in the pixel circuit can be fabricated in the same process, and the dummy via Vo is added in the first area A1 as a hydrogen discharge channel to improve and reduce the difference between the transistor characteristic in the first pixel circuit 10a and the transistor characteristic in the second pixel circuit 10b, without adding a new process.

Specifically, the manufacturing process of the display panel includes a hydrogenation process, which is intended to discharge hydrogen in the transistor active layer and the gate insulating layer in contact with the active layer under a certain high temperature condition. In one embodiment, after the insulating layer punching process, a hydrogenation process is performed before the process of the first metal layer M1.

With continued reference to fig. 4, the array layer 2 further includes a planarization layer 21, and the planarization layer 21 is formed after the process of the first metal layer M1 to provide a relatively flat substrate for the light emitting device 31. The first electrode 31a of the light emitting device 31 is connected to the via electrode in the first metal layer M1 through the opening O on the planarization layer 21, and the via electrode in the first metal layer M1 is connected to the corresponding transistor through the real hole K1, so as to electrically connect the pixel circuit and the first electrode 31 a.

In one embodiment, as shown in fig. 4, the dummy hole Vo penetrates all the insulating layers between the semiconductor layer 11 and the first metal layer M1. In the display panel, a semiconductor layer, a gate insulating layer and a first functional metal layer are sequentially arranged on a substrate, wherein a control end of a transistor in a pixel circuit is positioned on the first functional metal layer, and the hydrogen content in the semiconductor layer and the hydrogen content in the gate insulating layer influence the characteristics of the transistor.

The pixel circuit wiring diagram in the first area A1 shown in fig. 3 is a schematic plan view, and the connection relationship between the circuit components of the pixel circuit is shown in fig. 3, but the position of the dummy hole Vo in fig. 3 is only shown schematically, and the film layer through which the dummy hole Vo penetrates cannot be shown. The structure of the film layer at the tangent position in fig. 3 is schematically illustrated in the related embodiment, so as to illustrate the film layer through which the dummy hole Vo penetrates.

In another embodiment, FIG. 5 is another schematic cross-sectional view taken at line A-A' of FIG. 3. As shown in fig. 5, the dummy hole Vo penetrates the first functional layer G and extends in the direction of the substrate 1, and the dummy hole Vo penetrates a portion of the insulating layer between the semiconductor layer 11 and the first metal layer M1. The hole depth of the dummy hole Vo in this embodiment is small as compared with the embodiment of fig. 4, and the dummy hole Vo does not penetrate through to the semiconductor layer 11. In the hydrogenation process, the unfinished display panel is placed in a certain high-temperature environment, and hydrogen can move in the structural layer under the high-temperature condition, so that the dummy hole Vo arranged in the embodiment can also be used as a hydrogen discharge channel to reduce the difference between the transistor characteristics in the first pixel circuit and the transistor characteristics in the second pixel circuit.

In another embodiment, FIG. 6 is a schematic cross-sectional view taken at the location of line B-B' of FIG. 3. As shown in fig. 6, the substrate 1, the array layer 2, and the display layer 3 in the display panel. The display layer 3 includes a pixel defining layer 32 and light emitting devices 31, wherein the pixel defining layer 32 is used to space adjacent light emitting devices 31. The array layer 2 includes a semiconductor layer 11, a first functional metal layer 12, a second functional metal layer 13, a third functional metal layer 14, and a planarization layer 21 on the substrate 1, the planarization layer 21 being on the third functional metal layer 14. In this embodiment, the dummy hole Vo extends in the direction of the substrate 1 through the first functional layer G, which is located on the side of the first metal layer M1 away from the substrate 1, and is reused as the planarization layer 21.

As can be understood from the above description of the embodiment of fig. 4, the first electrode 31a of the light emitting device 31 needs to be connected to the transistor in the pixel circuit below through the opening O on the planarization layer 21, and the display panel process includes a process of forming an opening in the planarization layer 21. The dummy hole Vo in the embodiment of fig. 6 can be formed in the same process as the opening O of the planarization layer 21 without adding a new process.

The dummy hole Vo is illustrated in fig. 6 to penetrate all the insulating layers between the planarization layer 21 and the semiconductor layer 11. In another embodiment, the dummy hole Vo extends through the planarization layer 21 and toward the substrate 1, and the dummy hole Vo extends through a portion of the insulating layer between the planarization layer 21 and the semiconductor layer 11.

Specifically, in the embodiment of fig. 6, the dummy hole Vo and the light emitting device 31 do not overlap, so as to avoid the influence on the conductivity of the first electrode 31a when the first electrode 31a is fabricated on the dummy hole Vo.

Specifically, the dummy hole Vo does not overlap with the semiconductor layer 11 in a direction perpendicular to the plane of the substrate 1. In the pixel circuit, since a partial region of the semiconductor layer 11 serves as an active layer of the transistors and a partial region serves as a connection line between the transistors, the semiconductor layer 11 has a specific pattern shape when the display panel is viewed from a top view (see the schematic diagram in fig. 3). The dummy hole Vo is not overlapped with the semiconductor layer 11, on one hand, the design of the dummy hole Vo does not need to change the pattern shape of the semiconductor layer 11, and thus, the process of the semiconductor layer 11 is not affected; on the other hand, in the original punching process in the multiplexing array layer 2 for manufacturing the dummy holes Vo, after the punching process, a metal layer is usually laid on the whole surface, so that the dummy holes Vo are filled with a metal material, and on the premise of not changing the process of the semiconductor layer 11, if the dummy holes Vo and the semiconductor layer 11 are arranged to overlap, the metal material in the dummy holes Vo affects the conductivity of the semiconductor layer 11 overlapping with the dummy holes Vo, and further affects the operation of the pixel circuit, so that the operating performance of the first pixel circuit 10a in the first area A1 is different. The dummy holes Vo are set in consideration of the above factors, so that the influence on the process of the array layer 2 is small, and the difference in driving performance between different first pixel circuits 10a in the first area A1 is avoided.

In another embodiment, FIG. 7 is another schematic cross-sectional view taken at the location of line B-B' of FIG. 3. The first functional layer G is multiplexed into the pixel defining layer 32. The dummy hole Vo penetrates the pixel defining layer 32 and extends in the direction of the substrate 1. The pixel defining layer 32 is used to space the adjacent light emitting devices 31, and when the display panel is manufactured, the first electrode 31a is first manufactured on the array layer 2, then the pixel defining layer material on the whole surface is manufactured, then the pixel defining layer material is etched to form an opening, the opening exposes the first electrode 31a, and then the light emitting layer 31b and the second electrode 31c are sequentially manufactured. That is, the fabrication of the pixel defining layer 32 includes a process of forming an opening in the pixel defining layer material. In this embodiment, the dummy hole Vo can be formed by multiplexing the opening process of the pixel defining layer, and only the mask used in the opening process needs to be designed without adding a new process.

Further, as described in conjunction with the embodiment of fig. 4 and fig. 6, it can be understood that the first metal layer M1 in the array layer 2 includes a punching process before the process, and the first electrode 31a also includes a punching process before the process. In one embodiment, the dummy hole Vo in the embodiment of fig. 7 is formed through three punching processes, and the dummy hole Vo penetrates at least the pixel defining layer 32, the planarization layer 21 contacting the first electrode 31a and adjacent to one side of the substrate 1, and the insulating layer contacting the first metal layer M1 and adjacent to one side of the substrate 1.

In another embodiment, FIG. 8 is another schematic cross-sectional view taken at the location of line B-B' of FIG. 3. As shown in fig. 8, the light emitting device 31 includes a first electrode 31a, a light emitting layer 31b, and a second electrode 31c stacked over the substrate 1, wherein a partial region of the first functional layer G is multiplexed as the second electrode 31c, and a dummy hole Vo penetrates the first functional layer G and extends toward the substrate 1. In the conventional structure, the second electrode 31c is located on the entire surface of the film, but in the embodiment of the present invention, the film where the second electrode 31c is located has openings at least in the first region A1, and the openings extend toward the substrate 1, so that hydrogen in the semiconductor layer 11 and in the gate insulating layer above the semiconductor layer 11 can swim between the films in the hydrogenation process and is discharged outward through the openings (i.e., the dummy holes Vo), that is, the channels through which hydrogen is discharged in the first region A1 are increased, thereby reducing the difference between the transistor characteristics in the first pixel circuit 10a and the transistor characteristics in the second pixel circuit 10b, and improving the display non-uniformity problem.

The dummy hole Vo is illustrated in fig. 8 to penetrate all the insulating layers between the second electrode 31c and the semiconductor layer 11, and in another embodiment, the dummy hole Vo penetrates only a portion of the insulating layers between the second electrode 31c and the semiconductor layer 11.

In some embodiments, in the equal area region, the sum of the number of the real holes K and the dummy holes Vo in the first region A1 is n1, and the number of the real holes K in the second region A2 is n2; wherein, n1/n2 is more than or equal to 1/9 and less than or equal to 1.5. When the equal-area regions of the first region A1 and the second region A2 are defined for comparison, a region occupied by one pixel circuit may be defined as the equal-area region. In one embodiment, within the same area region, n1/n2=1/9; the number of the true holes K in the second area A2 in the area occupied by one pixel circuit is 9, and then the total number of the dummy holes Vo and the true holes in the first area A1 is 1. In one embodiment, within the same area region, n1/n2=1; the number of true holes in the second area A2 is 9 in an area occupied by one pixel circuit, and the total number of the dummy holes Vo and the true holes in the first area A1 is 9. The dummy holes Vo are provided in the first area A1 so that the number of holes (true holes plus dummy holes) in the first area A1 and the number of true holes K in the second area A2 in the same area are close to each other, and it is possible to increase the path through which hydrogen is discharged in the first area A1, thereby reducing the difference between the characteristics of the transistors in the first pixel circuit and the characteristics of the transistors in the second pixel circuit due to the difference in the density of the pixel circuits in the two areas.

In some embodiments, the dummy holes Vo in the first region A1 are spaced from the semiconductor layer 11 in a direction perpendicular to the substrate 1, so that hydrogen in the semiconductor layer 11 and hydrogen in the gate insulating layer need to move in a plurality of layers to be discharged from the dummy holes Vo, where n1/n2>1 is provided, and it can be said that the density of holes (both the dummy holes and the true holes are defined as holes) in the first region A1 in the same area is greater than the density of true holes in the second region A2. The discharge amount of hydrogen is increased by increasing the number of dummy holes Vo provided to reduce the difference between the characteristics of the transistors in the first pixel circuit and the characteristics of the transistors in the second pixel circuit.

When the dummy holes Vo are arranged in the first area A1, circuit components and some signal lines in the pixel circuit need to be avoided so as to prevent the dummy holes Vo from affecting the circuit performance. Furthermore, the arrangement of n1/n2 is less than or equal to 1.5, so that the complexity of circuit wiring in the first area A1 caused by excessive arrangement of the dummy holes Vo can be avoided on the premise of ensuring that the dummy holes Vo are used as a hydrogen discharge channel in the hydrogenation process.

Specifically, fig. 9 is a partial schematic view of a first area of another display panel according to an embodiment of the present invention, as shown in fig. 9, a first area A1 includes a pixel area Q1 and a non-pixel area Q2, a light emitting device 31 is located in the pixel area Q1, the pixel area Q1 is a pixel light emitting area in the display area, and the non-pixel area Q2 is shown in the figure and is disposed around the pixel area Q1. The dummy holes Vo are located in the non-pixel region Q2, that is, in a direction perpendicular to the substrate 1, the dummy holes Vo do not overlap with the light emitting device 31, and the arrangement of the dummy holes Vo does not affect the flatness of the first electrode 31a, so that the display effect is prevented from being affected by dispersion caused by poor flatness of the first electrode 31 a.

In some embodiments, a dummy pixel circuit is further disposed in the first area, and fig. 10 is a partial simplified schematic diagram of another display panel according to an embodiment of the present invention, as shown in fig. 10, a first area A1 includes a dummy pixel circuit 10x, and a sum of densities of the first pixel circuit 10a and the dummy pixel circuit 10x in the first area A1 is less than a density of the second pixel circuit 10b in the second area A2. The circuit structure of the dummy pixel circuit 10x is the same as or different from that of the first pixel circuit 10a, and the dummy pixel circuit 10x includes a true hole K connecting circuit parts, but the dummy pixel circuit 10x is not electrically connected to the light emitting device 31. Specifically, the dummy pixel circuit 10x is not connected to the first electrode of the light emitting device through the true hole K1 as illustrated in fig. 3 and 4, so that the dummy pixel circuit 10x does not drive the light emitting device to emit light. The dummy pixel circuit 10x is provided in the first area A1, the true hole K in the dummy pixel circuit 10x can also serve as a passage for discharging hydrogen in the semiconductor layer and hydrogen in the gate insulating layer, and since the circuit structure of the dummy pixel circuit 10x is the same as that of the first pixel circuit 10a, the provision of the dummy pixel circuit 10x can also improve the influence of the abrupt change in pattern density at the transition between the first area A1 and the second area A2 on the etching.

The number of the real holes in the dummy pixel circuit 10x is the same as that of the real holes in one first pixel circuit 10a, the arrangement of the dummy pixel circuit 10x has obvious effect on improving the characteristic difference of the transistors in the pixel circuits in two smaller areas, but the circuit structure in the dummy pixel circuit 10x is relatively complete, so that the space occupied by the whole dummy pixel circuit is larger, and compared with the space occupied by a single dummy hole Vo is relatively smaller, so that the position where the dummy hole Vo can be arranged is more flexible. The embodiment of fig. 10 considers the above factors together, and arranges the dummy pixel circuit 10x and the dummy hole Vo in the first area A1 at the same time, and uses the dummy pixel circuit 10x to improve the influence of the abrupt change of the pattern density on the etching when the transition between the first area A1 and the second area A2, and uses the dummy hole Vo and the real hole K in the dummy pixel circuit 10x to increase the hydrogen discharge path in the first area A1, so as to ensure that the transistor characteristics in the first pixel circuit 10a and the transistor characteristics in the second pixel circuit 10b are substantially consistent, and improve the problem of the display unevenness.

In another embodiment, fig. 11 is a partially simplified schematic diagram of another display panel according to an embodiment of the present invention, as shown in fig. 11, the first area A1 includes a transition area A1G and a semi-transparent area A1T, the transition area A1G is located between the second area A2 and the semi-transparent area A1T, and the first pixel circuit 10a is located in the transition area A1G. The arrangement density of the light emitting devices in the semi-transparent area A1T is smaller than that of the light emitting devices in the transition area A1G, and the arrangement density of the light emitting devices in the transition area A1G is smaller than that of the light emitting devices in the second area A2. Wherein, a dummy hole Vo is provided at least at one end of the transition area A1G near the second area A2. The semi-transparent area A1T is not provided with a pixel circuit, the pixel circuit for driving the light-emitting device in the semi-transparent area A1T is arranged in the transition area A1G, so that the light transmittance of the semi-transparent area A1T is increased while the light-emitting device in the semi-transparent area A1T is driven, the display panel provided by the embodiment can be applied to a camera scheme under a screen, and when the display device is assembled, the camera is arranged below the semi-transparent area A1T. When the camera shooting function is not called, the first pixel circuit 10a in the transition area A1G drives the light-emitting device in the semi-transparent area A1T to emit light so as to ensure that the display area displays a complete image picture. When the camera shooting function is called, the ambient light can penetrate through the display panel at the position of the semi-transparent area A1T and is received by the camera so as to finish shooting and imaging. The display unevenness problem caused by the difference between the transistor characteristics of the second pixel circuit 10b and the transistor characteristics of the first pixel circuit 10a due to the difference between the pixel circuit densities in the second area A2 and the first area A1 is relatively obvious at the boundary position between the second area A2 and the first area A1, and in this embodiment, the dummy hole Vo is provided at least at one end of the transition area A1G close to the second area A2, so that the luminance difference at the boundary position between the second area A2 and the transition area A1G during display is weakened, and at least the area with a large display luminance difference can be improved.

Further, dummy holes Vo are disposed in the transition area A1G near one end of the second area A2 and in the transition area A1G, so as to improve the characteristics of the transistors in all the first pixel circuits 10a in the first area A1, and to greatly improve the display non-uniformity problem.

In one embodiment, the sum of the hole arrangement densities of the virtual holes Vo and the real holes K in the transition area A1G is R1, and the hole arrangement density of the real holes K in the second area A2 is R2; wherein, R1/R2 is more than or equal to 1/3 and less than or equal to 1. The pixel circuit arrangement density in the transition area A1G is smaller than the pixel circuit arrangement density in the second area A2, and the difference between the transistor characteristics in the first pixel circuit 10a and the transistor characteristics in the second area A2 in the transition area A1G is reduced by providing the dummy holes Vo in the transition area A1G to increase the discharge path of hydrogen in the transition area A1G. The larger the number of the dummy holes Vo provided in the transition area A1G, the better the effect of improving the variation in the characteristics of the transistors in the pixel circuits located in the two areas.

The first pixel circuit 10a is located in the transition area A1G, and no pixel circuit is disposed in the semi-transparent area A1T, so that during manufacturing, an abrupt change of an etching pattern exists at a junction position between the transition area A1G and the semi-transparent area A1T, so that a difference exists in driving performance between the first pixel circuit 10a close to the semi-transparent area A1T and the first pixel circuit 10a far from the semi-transparent area A1T, and a difference exists between luminance of a light emitting device driven by the first pixel circuit 10a near the boundary position and luminance of a light emitting device driven by the first pixel circuit 10a at other positions. Further, fig. 12 is a partially simplified schematic diagram of another display panel according to an embodiment of the present invention, as shown in fig. 12, a dummy hole Vo is disposed at an end of the semi-transmissive area A1T close to the transition area A1G; the hole arrangement density of the dummy holes Vo in the partial semi-permeable area A1T provided with the dummy holes Vo is R3; wherein, R3/R1 is more than or equal to 1/3 and less than or equal to 1. The dummy hole Vo is arranged at one end, close to the transition area A1G, in the semi-transparent area A1T, so that the difference of driving performance between the first pixel circuit 10a close to the semi-transparent area A1T and the first pixel circuit 10a far away from the semi-transparent area A1T is improved, the difference of driving performance between the first pixel circuits 10a in the transition area A1G is smaller, and the display unevenness caused by the difference of driving performance between different first pixel circuits 10a is improved. In addition, the dummy holes Vo are provided only at the semi-transmissive area A1T near the transition area A1G to minimize the influence of the dummy holes Vo on the light transmittance of the semi-transmissive area A1T.

In some embodiments, the dummy holes in the semi-transmissive region are distributed in the same manner as the real holes and/or the dummy holes in the transition region in an equal area region, wherein the equal area region is not limited to an area region occupied by one pixel circuit. In one embodiment, dummy holes are not disposed in the transition region near the semi-transparent region, and only the real holes in the first pixel circuit are included in the transition region near the semi-transparent region, so that the dummy holes in the semi-transparent region are disposed in the same manner as the real holes in the first pixel circuit. In another embodiment, dummy holes are disposed in the transition area near the semi-transparent area, and the transition area near the semi-transparent area includes the dummy holes and the real holes in the first pixel circuit, and the dummy holes in the semi-transparent area are disposed in the same manner as the dummy holes and the real holes in the transition area.

Specifically, taking the example that no dummy hole is disposed at a position of the transition region close to the semi-transparent region, fig. 13 is a simplified schematic diagram of a portion of the first region in another display panel according to an embodiment of the present invention. As shown in fig. 13, the distribution of the dummy holes Vo in the semi-transmissive area A1T is the same as the distribution of the real holes K in the first pixel circuit 10a. The dummy apertures Vo are provided at positions of the semi-transmissive region A1T near the transition region A1G in this embodiment to improve a difference in driving performance between the first pixel circuits 10a near the semi-transmissive region A1T and the first pixel circuits 10a farther from the semi-transmissive region A1T, so that the difference in driving performance between the first pixel circuits 10a within the transition region A1G is small. In addition, the dummy holes Vo can be manufactured in the same process as the real holes K in the pixel circuit, and the distribution mode of the dummy holes Vo in the semi-transparent area A1T and the distribution mode of the holes in the transition area A1G are the same in the same area, so that the design of the mask plate in the punching process can be simplified.

The display panel also comprises a connecting signal line which extends from the second area to the transition area; the dummy hole does not overlap the connection signal line in a direction perpendicular to a plane of the display panel. Specifically, fig. 14 is a partially simplified schematic diagram of another display panel according to an embodiment of the present invention. The pixel circuit structure illustrated in fig. 14 is slightly different from that of the pixel circuit illustrated in fig. 3, and the pixel circuit in fig. 14 does not include the first capacitor Co. As shown in fig. 14, the display panel includes signal lines Xx extending in a first direction x and signal lines Xy extending in a second direction y, the first direction x and the second direction y intersecting each other. As will be understood from the above description of the pixel circuit of fig. 3, the signal lines Xx include first scan lines, second scan lines, reset signal lines, and emission control signal lines; the signal lines Xy include data lines and power signal lines.

In the local position illustrated in fig. 14, the boundary between the second area A2 and the transition area A1G extends substantially along the second direction y, a part of the signal line Xx in the display panel extends from the second area A2 into the transition area A1G, and the part of the signal line Xx provides a signal to simultaneously drive the second pixel circuit 10b in the second area A2 and the first pixel circuit 10a in the transition area A1G. The connection signal line LX extending from the second area A2 into the transition area A1G is indicated, and when the dummy via Vo is disposed at a position of the transition area A1G close to the second area A2, the dummy via Vo does not overlap with the connection signal line LX, so as to avoid a bad influence of the metal layer laid after the punching process of the dummy via Vo on the conductivity of the connection signal line LX.

In another embodiment, the second area A2 is at least half-surrounded by the first area A1, and a partial boundary between the second area A2 and the transition area A1G extends substantially along the second direction y, so that a part of the signal line Xy extends from the second area A2 to the transition area A1G, and the dummy aperture Vo is disposed at a position of the transition area A1G close to the second area A2, and the dummy aperture Vo does not overlap with the signal line Xy.

In an embodiment, fig. 15 is a partially simplified schematic diagram of another display panel according to an embodiment of the present invention. As shown in fig. 15, taking as an example that the boundary between the second region A2 and the first region A1 extends substantially in the second direction y, the display panel includes a signal line Xx extending in the first direction x and a signal line Xy extending in the second direction y, and as understood in conjunction with the pixel circuit structure illustrated in the embodiment of fig. 3 described above, the signal line Xx includes the first scanning line S1, the second scanning line S2, the emission control signal line E, and the reset signal line Ref, and the signal line Xy includes the power supply signal line P and the data line D. The pixel circuit is electrically connected to the signal line, and the structure of the pixel circuit is shown in the figure as a simplified illustration. The signal lines include a first signal line 1X, a second signal line 2X, and a third signal line 3X. The first signal line 1X, the second signal line 2X, and the third signal line 3X transmit signals of the same kind, where the signals of the same kind refer to signals that perform the same function when driving the pixel circuits to operate, for example, the light emission control signal lines that drive different pixel circuit rows belong to signal lines that transmit signals of the same kind, and the reset signal lines that drive different pixel circuit rows also belong to signal lines that transmit signals of the same kind.

As illustrated in fig. 15, the first signal line 1X extends from within the second area A2 into the first area A1; a partial line segment of the first signal line 1X located in the first area A1 is electrically connected to the plurality of first pixel circuits 10a, and a partial line segment of the first signal line 1X located in the second area A2 is electrically connected to the plurality of second pixel circuits 10 b. The second signal line 2X is located in the second area A2, the second signal line 2X is electrically connected to the plurality of second pixel circuits 10b, and the second signal line 2X is cut off at a position where the second area A2 is close to the first area. The third signal line 3X is located in the first region A1, and the third signal line 3X is electrically connected to the plurality of first pixel circuits 10a.

A dummy hole Vo is provided in the first area A1 near the second area A2, and at least one third signal line 3X is electrically connected to the first signal line 1X through the first bridge line 71. At least one second signal line 2X is electrically connected to the first signal line 1X through the second bridge line 72 at a position where the second area A2 is close to the first area A1. Fig. 15 illustrates that the first signal line 1X, the second signal line 2X, and the third signal line 3X are all reset signal lines, and this embodiment can reduce the number of signal lines extending from the second area A2 to the first area A1 at the boundary position between the first area A1 and the second area A2, so that the space of the first area A1 can be saved, and the saved space can be used to dispose a larger number of dummy holes Vo. Moreover, the reset signal line Ref supplies a constant voltage signal when the driving pixel circuit operates, and the arrangement in the embodiment of fig. 15 does not affect the driving performance of the reset signal line Ref to the pixel circuit, and can reduce the voltage drop on the reset signal line Ref in the display panel.

In another embodiment, the first signal line, the second signal line, and the third signal line are all power signal lines. The second region A2 is at least half-surrounded with the first region A1, and a part of the boundary between the second region A2 and the transition region A1G extends substantially along the second direction y, so that a part of the signal line Xy extends from the second region A2 to the transition region A1G, the part of the power signal line P extends from the second region A2 to the first region A1, and the part of the power signal line P within the second region A2 is cut off at a position close to the first region A1; the power supply signal lines P within the first area A1 are turned off at a position near the second area A2, and the power supply signal lines P driving different pixel circuit columns are connected through bridge lines near a boundary position of the second area A2 and the first area A2, so that the number of signal lines extending from the second area A2 to the first area A1 at the boundary position of the first area A1 and the second area A2 can be reduced, thereby saving space for disposing a greater number of dummy holes Vo.

In an embodiment, fig. 16 is a partially simplified schematic diagram of another display panel according to an embodiment of the present invention. As shown in fig. 16, the signal lines in the display panel include a fourth signal line 4X, and the fourth signal line 4X includes a first line segment 4Xa, a second line segment 4Xb, and a third line segment 4Xc; the first line segment 4Xa is located in the first area A1, and the first line segment 4Xa is electrically connected to the plurality of first pixel circuits 10 a; the second line segment 4Xb is located in the second region A2, and the second line segment 4Xb is electrically connected to the plurality of second pixel circuits 10 b; the third line segment 4Xc is located in the first area A1 near the second area A2, and one end of the third line segment 4Xc is connected to the first line segment 4Xa and the other end is connected to the second line segment 4Xb. The position of the first area A1, which is close to the second area A2, is provided with a dummy hole Vo, and the line width d3 of the third line segment 4Xc is smaller than the line width d1 of the first line segment 4Xa and smaller than the line width d2 of the second line segment 4 Xb; the third line segment 4Xc has a line thickness greater than that of the first line segment 4Xa and greater than that of the second line segment 4Xb. In this embodiment, the fourth signal line 4X extends from the second area A2 to the first area A1, and the line width of a part of the line segment (i.e., the third line segment 4 Xc) of the fourth signal line 4X located in the first area A1 and near the second area A2 is narrowed, so that a space can be saved in the first area A1 and near the second area A2 to dispose the dummy hole Vo. Meanwhile, the line thickness of the third line segment 4Xc is increased to ensure that the overall resistance change of the fourth signal line 4X is small, thereby avoiding the influence on the voltage signal transmitted by the fourth signal line 4X.

The characteristic performance of the driving transistor and the characteristic performance of the threshold compensation transistor in the pixel circuit have a large influence on the driving current for driving the light emitting device to emit light. In the embodiment of the present invention, the dummy holes Vo provided in the first area A1 include a first dummy hole adjacent to the driving transistor Tm in the first pixel circuit 10a, and the hydrogen content in the driving transistor Tm is improved by the dummy hole to reduce the difference between the characteristics of the driving transistor Tm in the first pixel circuit 10a and the characteristics of the driving transistor Tm in the second pixel circuit 10b, thereby improving the display unevenness.

In another embodiment, the dummy holes Vo include a second dummy hole adjacent to the threshold compensation transistor T2 in the first pixel circuit 10a. The hydrogen content in the threshold compensation transistor T2 is improved by the dummy hole to reduce the difference between the characteristics of the threshold compensation transistor T2 in the first pixel circuit 10a and the characteristics of the threshold compensation transistor T2 in the second pixel circuit 10b, thereby improving display unevenness.

In another embodiment, the dummy holes Vo include a first dummy hole adjacent to the driving transistor Tm in the first pixel circuit 10a and a second dummy hole adjacent to the threshold compensating transistor T2 in the first pixel circuit 10a.

In an embodiment, fig. 17 is a partial schematic view of another display panel provided in an embodiment of the invention, and fig. 17 illustrates a partial semi-transparent region A1T and a transition region A1G, where the first pixel circuit 10a is located in the transition region A1G, the arrangement density of the light emitting devices 31 in the semi-transparent region A1T is less than the arrangement density of the light emitting devices 31 in the transition region A1G, a part of the first pixel circuit 10a-1 is used for driving the light emitting devices 31 in the transition region A1G, and the remaining part of the first pixel circuit 10a-2 is used for driving the light emitting devices 31 in the semi-transparent region A1T. In a conventional display panel structure, a pixel circuit is disposed below a light emitting device that it drives, and a transistor in the pixel circuit substantially overlaps a first electrode of the light emitting device in a direction perpendicular to the display panel. In the embodiment of fig. 17, since the pixel circuit for driving the light emitting device 31 in the semi-transmissive region A1T is disposed in the transition region A1G, the transistors in the first pixel circuit 10a in the transition region A1G may not overlap with the light emitting device 31, and since the transistors in the first pixel circuit 10a may not overlap with the light emitting device 31, ambient light or light emitted by the light emitting device 31 may be reflected and refracted to irradiate channels of the transistors, which may cause the characteristics of the transistors to change, and further cause the driving performance of the first pixel circuit 10a to be irradiated to change, which shows that display unevenness occurs in the display performance.

Further, fig. 18 is a pixel circuit wiring diagram in the first area of another display panel according to an embodiment of the present invention, and the structure of the pixel circuit in fig. 18 can be understood with reference to the embodiment of fig. 3, which is not described herein again. As shown in fig. 18, a light-shielding layer 90 is provided above the driving transistor Tm and the threshold compensation transistor T2 in the pixel circuit, and the light-shielding layer 90 is located on the side of the transistor structure away from the substrate. The light incident on the driving transistor Tm and the threshold compensation transistor T2 is shielded by the light shielding layer 90, so that the driving performance of the first pixel circuit is prevented from being changed due to illumination, and the problem of display unevenness is solved.

Specifically, the light shielding layer 90 and the first electrode 31a of the light emitting device 31 are located in the same layer, and the light shielding layer 90 and the first electrode 31a are manufactured in the same process, so that the design of the light shielding layer 90 does not need to add a new process, and the overall thickness of the display panel is not affected.

Fig. 17 is illustrated such that the first pixel circuit 10a-2 does not overlap the light emitting device 31. In some embodiments, after the pixel circuit for driving the light emitting device 31 in the semi-transmissive region A1T is disposed in the transition region A1G, the arrangement of the first pixel circuit in the transition region A1G needs to be designed, and it is also possible that some transistors in the first pixel circuit 10a-1 for driving the light emitting device 31 in the transition region A1G do not overlap with the light emitting device.

Fig. 19 is a schematic view of a display device according to an embodiment of the present invention, and as shown in fig. 19, the display device includes a display panel 100 according to any embodiment of the present invention. The structure of the display panel has been described in the above embodiments, and is not described herein again. The display device in the embodiment of the invention can be any equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, a television, an intelligent wearable product and the like.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, comprising:

a pixel circuit including a first pixel circuit and a second pixel circuit;

a first region including the first pixel circuit and a second region including the second pixel circuit, the first and second pixel circuits being electrically connected to a light emitting device, respectively;

the density of the first pixel circuits in the first region is less than the density of the second pixel circuits in the second region;

the first area is provided with a dummy hole which penetrates through at least part of the film layer in the display panel;

2. The display panel according to claim 1,

the pixel circuit is provided with a real hole which is used for connecting a circuit component;

in the area with the same area, the sum of the number of the real holes and the number of the dummy holes in the first area is n1, and the number of the real holes in the second area is n2; wherein the content of the first and second substances,

1/9≤n1/n2≤1.5。

3. the display panel according to claim 1, comprising:

the semiconductor layer and the first functional layer are positioned on one side, far away from the substrate, of the substrate in sequence; the dummy hole penetrates through the first functional layer and extends towards the direction of the substrate.

4. The display panel according to claim 3,

the first functional layer is located on a side of the light emitting device close to the substrate.

5. The display panel according to claim 4,

the display panel further comprises a first metal layer which is the metal layer closest to the light-emitting device on the side close to the substrate; wherein, the first and the second end of the pipe are connected with each other,

the first functional layer is in contact with the first metal layer; the first functional layer is located on one side of the first metal layer close to the substrate, or the first functional layer is located on one side of the first metal layer far away from the substrate.

6. The display panel according to claim 5,

the dummy hole penetrates all the insulating layers between the semiconductor layer and the first metal layer.

7. The display panel according to claim 6, wherein the dummy hole does not overlap with the semiconductor layer in a direction perpendicular to a plane of the substrate.

8. The display panel according to claim 3,

the first functional layer is multiplexed as a pixel definition layer.

9. The display panel according to claim 3,

the light emitting device includes a first electrode, a light emitting layer, and a second electrode stacked over the substrate, wherein a partial region of the first functional layer is multiplexed as the second electrode.

10. The display panel according to claim 1,

the first region includes a pixel region where the light emitting device is located and a non-pixel region;

the dummy hole is located in the non-pixel region.

11. The display panel according to claim 1,

the pixel circuit has a true hole for connecting a circuit component;

the pixel circuit further includes a dummy pixel circuit located in the first region, the dummy pixel circuit not being electrically connected to the light emitting device; the dummy pixel circuit comprises the true aperture;

the sum of the densities of the first pixel circuits and the dummy pixel circuits in the first area is smaller than the density of the second pixel circuits in the second area.

12. The display panel according to claim 1,

the dummy hole is arranged at least in one end of the transition area close to the second area.

13. The display panel according to claim 12,

the display panel comprises a connecting signal line, and the connecting signal line extends from the second area to the transition area; in a direction perpendicular to a plane of the display panel, the dummy hole does not overlap the connection signal line.

14. The display panel according to claim 12, wherein the pixel circuit has a true hole for connecting a circuit part;

the sum of the hole arrangement densities of the dummy holes and the real holes in the transition area is R1, and the hole arrangement density of the real holes in the second area is R2; wherein, R1/R2 is more than or equal to 1/3 and less than or equal to 1.

15. The display panel according to claim 14,

the dummy hole is arranged at one end, close to the transition area, in the semi-transparent area; the hole arrangement density of the dummy holes in the partial semi-transparent area in which the dummy holes are arranged is R3;

wherein, R3/R1 is more than or equal to 1/3 and less than or equal to 1.

16. The display panel according to claim 15,

in the area with the same area, the dummy holes in the semi-transparent area are distributed in the same mode as the real holes and/or the dummy holes in the transition area.

17. The display panel according to claim 1,

the display panel includes signal lines, the pixel circuits are electrically connected to the signal lines,

the signal lines include a first signal line, a second signal line and a third signal line; the first signal line, the second signal line and the third signal line transmit signals of the same kind;

the first signal line extends from within the second region to within the first region; a partial line segment of the first signal line located in the first region is electrically connected to the plurality of first pixel circuits, and a partial line segment of the first signal line located in the second region is electrically connected to the plurality of second pixel circuits;

the second signal line is located in the second region, the second signal line is electrically connected to the plurality of second pixel circuits, and the second signal line is turned off at a position where the second region is close to the first region;

the third signal line is located in the first region, and the third signal line is electrically connected to the plurality of first pixel circuits;

the dummy hole is arranged at a position, close to the second area, of the first area, and at least one third signal line is electrically connected with the first signal line through a first bridging line at the position.

18. The display panel according to claim 1,

the signal lines include a fourth signal line including a first line segment, a second line segment, and a third line segment;

the first line segment is positioned in the first area and is electrically connected with the first pixel circuits;

the second line segment is positioned in the second area and is electrically connected with the second pixel circuits;

the third line segment is positioned at the position of the first area close to the second area, one end of the third line segment is connected with the first line segment, and the other end of the third line segment is connected with the second line segment;

the dummy hole is arranged at a position, close to the second area, of the first area, and the line width of the third line segment is smaller than the line width of the first line segment and smaller than the line width of the second line segment; the line thickness of the third line segment is larger than that of the first line segment and larger than that of the second line segment.

19. The display panel according to claim 1,

the first pixel circuit includes a drive transistor and a threshold compensation transistor,

the dummy holes include a first dummy hole adjacent to the driving transistor; and/or the dummy holes include a second dummy hole adjacent to the threshold compensation transistor.

20. The display panel according to claim 1, wherein one of the first pixel circuits is electrically connected to one of the light emitting devices, and one of the second pixel circuits is electrically connected to one of the light emitting devices.

21. The display panel according to claim 1, wherein the dummy hole is not provided at a position of the transition region near the semi-transmissive region.

22. A display device characterized by comprising the display panel according to any one of claims 1 to 21.