CN115145541A - Random number generation circuit and method, true random number generator - Google Patents

Random number generation circuit and method, true random number generator Download PDF

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Publication number
CN115145541A
CN115145541A CN202210913322.XA CN202210913322A CN115145541A CN 115145541 A CN115145541 A CN 115145541A CN 202210913322 A CN202210913322 A CN 202210913322A CN 115145541 A CN115145541 A CN 115145541A
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signal
circuit
random number
signals
output
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刘雷波
杨明凯
杨博翰
魏少军
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Wuxi Research Institute of Applied Technologies of Tsinghua University
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Wuxi Research Institute of Applied Technologies of Tsinghua University
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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Abstract

The invention provides a random number generation circuit, which is applied to the technical field of circuits and comprises the following steps: the device comprises a signal generating circuit, a signal amplifying circuit and a signal converting circuit, wherein the signal generating circuit is used for generating a pair of signals with phase difference, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, the signal amplifying circuit is a time amplifier, and the signal converting circuit is used for converting the pair of signals after phase difference amplification into original random numbers and then outputting the original random numbers. The invention also provides a random number generation method and a true random number generator, wherein the problem that the resolution is limited by the delay limit of the standard unit of the digital circuit is solved by using the signal amplification circuit for generating the random number and amplifying the clock jitter intensity by using the signal amplification circuit.

Description

Random number generation circuit and method, true random number generator
Technical Field
The invention relates to the technical field of circuits, in particular to a random number generation circuit and method and a true random number generator.
Background
The design of True Random Number Generators (TRNG) has been the focus of recent cryptology research. TRNG designs have a trade-off between high entropy and high throughput. High entropy requires accumulation of sufficient clock jitter strength, and the square of the rate at which clock jitter strength accumulates is proportional to time.
For the TRNG (ERO-TRNG) based on the basic ring oscillator and the TRNG derived from the TRNG, on the premise of ensuring that the entropy value is not changed, the required clock jitter intensity can be reduced by increasing the sampling rate, so that the throughput is greatly improved. At present, in the conventional TRNG design, for the part of the original random number, there is a disadvantage that the resolution is limited by the delay limit of the standard unit of the digital circuit, so that the throughput cannot be further improved.
Disclosure of Invention
The invention mainly aims to provide a random number generation circuit and method and a true random number generator, wherein the resolution is not limited by the delay limit of a standard unit of a digital circuit.
To achieve the above object, a first aspect of embodiments of the present invention provides a random number generation circuit, including:
the signal generating circuit, the signal amplifying circuit and the signal converting circuit;
the signal generating circuit comprises two input ends and two output ends, the two input ends of the signal generating circuit are both connected with the external signal input end, and the signal generating circuit is used for generating a pair of signals with phase difference;
the signal amplifying circuit comprises two input ends and two output ends, the two input ends of the signal amplifying circuit are connected with the two output ends of the signal generating circuit one by one, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, and the signal amplifying circuit is a time amplifier;
the signal conversion circuit comprises two input ends and an output end, the two input ends of the signal conversion circuit are connected with the two output ends of the signal amplification circuit one by one, and the signal conversion circuit is used for converting the pair of signals after the phase difference amplification into original random numbers and then outputting the original random numbers.
In an embodiment of the invention, the time difference between the rising edges of the pair of signals with the phase difference is Δ T in The time difference of the rising edges of the pair of signals after phase difference amplification is delta T out Then Δ T out ＝G·ΔT in And G is the amplification factor of the signal amplification circuit.
In an embodiment of the present invention, the signal generating circuit includes two first ring oscillators with the same components and topology.
In an embodiment of the present invention, each of the first ring oscillators includes a plurality of not gates and a nand gate connected in series in sequence, one input end of the nand gate is connected to the external signal input end, and an output end of the nand gate is connected to the input end of the signal amplifying circuit.
In an embodiment of the present invention, the signal amplifying circuit includes two time amplifying units having the same components and the same topology.
In an embodiment of the present invention, the time amplification unit includes:
the second ring oscillator comprises a plurality of adjustable NAND gates which are sequentially connected in series, and one output end of the signal generation circuit is connected with one input end of any one adjustable NAND gate;
the input end of the NOT gate is connected with the output end of any one of the adjustable NAND gates;
an edge detector having an input coupled to the output of the not gate and an output coupled to the input of the time-to-digital converter, the edge detector configured to generate an enable signal for the second ring oscillator and an output signal if the periodically amplified signal is detected, or the edge detector configured to generate an output signal if the periodically amplified signal is detected, the output signal being one of the pair of signals after phase difference amplification.
In an embodiment of the present invention, the adjustable nand gate includes:
the enabling signals of 1 of the N +1 NAND gates connected in parallel are kept high, the enabling signals of the N NAND gates connected in parallel are the external signals, and N is a positive integer larger than 0.
In an embodiment of the present invention, the edge detector includes:
the D input end of one D flip-flop of the two D flip-flops is connected with a high level, the clock end of the D flip-flop is connected with the output end of the NOT gate, the D input end of the other D flip-flop of the two D flip-flops is connected with the Q output end of the D flip-flop, the clock end of the other D flip-flop is connected with the output end of the NOT gate, and the Q output end of the other D flip-flop is connected with the input end of the signal conversion circuit;
the Q output end of the D trigger is connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the external signal.
In an embodiment of the present invention, the signal conversion circuit includes:
the delay chain comprises two input ends and a plurality of output ends, the two input ends of the delay chain are respectively connected with the two output ends of the signal amplification circuit one by one, and the delay chain is used for sampling the pair of signals to obtain digital signals;
and the priority encoder comprises a plurality of input ends and an output end, the input ends of the priority encoder are respectively connected with the output ends of the delay chain one by one, and the priority encoder is used for detecting a first edge bit in the digital signal segment and outputting the least significant bit of the first edge bit as an original random number.
The second aspect of the present disclosure also provides a random number generation method applied to a random number generation circuit, where the random number generation circuit includes a signal generation circuit, a signal amplification circuit, and a signal conversion circuit, which are connected in sequence, and the signal amplification circuit is a time amplifier, and the method includes:
generating, by the signal generation circuit, a pair of signals having a phase difference;
amplifying, by the signal amplification circuit, a phase difference of the pair of signals;
and converting the pair of signals after the phase difference amplification into original random numbers through the signal conversion circuit and then outputting the original random numbers.
In an embodiment of the invention, the time difference between the rising edges of the pair of signals with the phase difference is Δ T in The time difference of the rising edges of the pair of signals after phase difference amplification is delta T out Then Δ T out ＝G·ΔT in And G is the amplification factor of the signal amplification circuit.
A third aspect of the present disclosure further provides a true random number generator, including the random number generating circuit and the original random number processing circuit of the first aspect;
the random number generating circuit is used for generating an original random number;
the original random number processing circuit is used for processing the original random number to generate an external random number.
According to an embodiment of the present invention, a random number generation circuit provided by the present invention includes: the signal generating circuit comprises two input ends and two output ends, the two input ends of the signal generating circuit are connected with an external signal input end, the signal generating circuit is used for generating a pair of signals with phase difference, the signal amplifying circuit comprises two input ends and two output ends, the two input ends of the signal amplifying circuit are connected with the two output ends of the signal generating circuit one by one, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, the signal converting circuit comprises two input ends and one output end, the two input ends of the signal converting circuit are connected with the two output ends of the signal amplifying circuit one by one, and the signal converting circuit is used for converting the pair of signals after phase difference amplification into original random numbers and outputting the original random numbers. The signal amplifying circuit is used for generating random numbers, and the clock jitter intensity is amplified by the signal amplifying circuit, so that the problem that the resolution is limited by the delay limit of a standard unit of a digital circuit is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a random number generation circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a phase difference between a pair of signals generated by a signal generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a signal amplifying circuit (EN = 1) according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a signal amplifying circuit (EN = 0) according to an embodiment of the present invention;
fig. 6 is a timing diagram of a signal amplifying circuit according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a signal conversion circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a signal conversion circuit according to an embodiment of the present invention;
fig. 9 is a flowchart illustrating a random number generating method according to an embodiment of the present invention;
FIG. 10 is a block diagram of a true random number generator according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a random number generation circuit and method, a true random number generator, which can be applied to the field of data encryption or generate a key, and can also be used for generating an initial vector, a session key, a challenge in challenge-response authentication, a mask for resisting side channel attack and the like, wherein the random number generation circuit comprises: the signal generating circuit comprises two input ends and two output ends, the two input ends of the signal generating circuit are connected with an external signal input end, the signal generating circuit is used for generating a pair of signals with phase difference, the signal amplifying circuit comprises two input ends and two output ends, the two input ends of the signal amplifying circuit are connected with the two output ends of the signal generating circuit one by one, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, the signal amplifying circuit is a time amplifier, the signal converting circuit comprises two input ends and one output end, the two input ends of the signal converting circuit are connected with the two output ends of the signal amplifying circuit one by one, and the signal converting circuit is used for converting the pair of signals after the phase difference is amplified into original random numbers and outputting the original random numbers. The signal amplifying circuit is used for generating random numbers, and the clock jitter intensity is amplified by using the signal amplifying circuit, so that the problem that the resolution is limited by the delay limit of a standard unit of a digital circuit is solved.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The features of the embodiments and examples described below may be combined with each other without conflict between the embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a random number generation circuit according to an embodiment of the present invention, the random number generation circuit includes:
the device comprises a signal generating circuit, a signal amplifying circuit and a signal converting circuit.
The signal generating circuit comprises two input ends and two output ends, wherein the two input ends of the signal generating circuit are connected with the external signal input end, and the signal generating circuit is used for generating a pair of signals with a phase difference.
The signal amplifying circuit comprises two input ends and two output ends, the two input ends of the signal amplifying circuit are connected with the two output ends of the signal generating circuit one by one, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, and the signal amplifying circuit is a time amplifier.
The signal conversion circuit comprises two input ends and an output end, the two input ends of the signal conversion circuit are connected with the two output ends of the signal amplification circuit one by one, and the signal conversion circuit is used for converting the pair of signals after phase difference amplification into original random numbers and outputting the original random numbers.
In the invention, a time amplifier with an amplification range of 0 to dozens of picoseconds can be selected, and the performance indexes of high gain (amplification factor) and high linearity can be ensured to be met as much as possible in the amplification range. Further, a time amplifier with a small time required for completing one amplification can be selected.
According to the embodiment of the invention, a pair of signals with phase difference are generated by a signal generating circuit, the phase difference of the pair of signals is amplified by a signal amplifying circuit, the pair of signals after the phase difference amplification is converted into the original random number by a signal converting circuit and then output, the signal amplifying circuit is used for generating the random number, the clock jitter intensity is amplified by a time amplifier, and the problem that the resolution is limited by the delay limit of a standard unit of a digital circuit is solved.
In an embodiment of the present invention, the signal generating circuit includes two first ring oscillators with the same components and topology. According to the embodiment, the signal generating circuit generates a pair of signals with phase difference due to clock jitter by two first ring oscillators with the same components and consistent topological structures, so that the purpose of eliminating the influence of global noise is achieved, and the safety risk brought by channel measurement attack is further reduced.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention, in which each of first ring oscillators (RO 1 and RO 2) in the signal generating circuit includes a plurality of not gates and a nand gate connected in series in sequence, one input end of the nand gate is connected to the external signal input end, and an output end of the nand gate is connected to the input end of the signal amplifying circuit.
It is understood that this embodiment is only one possible specific structure of the first ring oscillator, and those skilled in the art can make any other adaptive changes to the internal structure of the first ring oscillator, on the premise of ensuring that the signal generating circuit includes two first ring oscillators with the same component and topology, for example, the first ring oscillators each include three not gates connected in series in sequence, or the first ring oscillators each include three nand gates connected in series in sequence, and so on.
Specifically, two first ring oscillators with the same components and consistent topological structures form a signal generating circuit. The period of the first ring oscillator is subject to clock jitter due to noise sources present in the electronic components. Since other noise sources are difficult to analyze or easy to manipulate by an attacker, only gaussian noise is analyzed, and the influence of other noise is defined as a deterministic component, and after a period of oscillation, the phase difference of a pair of signals conforms to a gaussian distribution, as shown in fig. 3.
In an embodiment of the present invention, the signal amplifying circuit includes two time amplifying units having the same components and topology. According to the present embodiment, the signal amplification circuit realizes a function of further amplifying the phase difference between a pair of signals by two time amplification units having the same constituent elements and having the same topology.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a signal amplifying circuit according to an embodiment of the present invention, in which time amplifying units in the signal amplifying circuit include:
and the second ring oscillator comprises a plurality of adjustable NAND gates (TD, tunable NAND) which are sequentially connected in series, and one output end of the signal generation circuit is connected with one input end of any one adjustable NAND gate.
And the input end of the NOT gate is connected with the output end of any one of the adjustable NAND gates. As shown in fig. 4, i.e. the input terminal of the not-gate is connected to the output terminal of the first TD.
An edge detector having an input connected to the output of the not gate and an output connected to the input of the time-to-digital converter, the edge detector being configured to generate an enable signal for the second ring oscillator and to generate an output signal if the periodically amplified signal is detected, or the edge detector being configured to generate an output signal if the periodically amplified signal is detected, the output signal being one of the pair of signals after phase difference amplification.
It is understood that this embodiment is only one possible specific structure of the time amplifier, and those skilled in the art may make any other adaptive changes to the internal structure of the time amplifier or use any other time amplifier that meets the requirements, on the premise that the time amplifier includes two time amplifying units with the same component devices and the same topology.
In an embodiment of the present invention, the adjustable nand gate includes: the NAND gates are connected in parallel, the enable signals of 1 of the N +1 NAND gates connected in parallel are kept high, the enable signals of the N NAND gates connected in parallel are the external signals, and N is a positive integer greater than 0.
In one embodiment of the present invention, the edge detector includes: the D input end of one D flip-flop of the two D flip-flops is connected with a high level, the clock end of the one D flip-flop is connected with the output end of the NOT gate, the D input end of the other D flip-flop of the two D flip-flops is connected with the Q output end of the one D flip-flop, the clock end of the other D flip-flop is connected with the output end of the NOT gate, the Q output end of the other D flip-flop is connected with the input end of the signal conversion circuit, the Q output end of the one D flip-flop is connected with the input end of the NOT gate, and the output end of the NOT gate is connected with the external signal.
In the present invention, as shown in fig. 4 (nand gate Nx in fig. 4 represents N parallel nand gates), the signal amplifying circuit used in the present invention is composed of two second ring oscillators having the same topology and capable of realizing cycle switching and an edge detector. The edge detector is used for generating output signals outn and outp finally output from two output ends of the signal amplifying circuit, and can also generate an enable signal EN. The second ring oscillator includes a plurality of TDs connected in series. The N +1 NAND gates with the enable signal EN are connected in parallel to form TD, wherein the N +1 NAND gates are divided into two groups: ND1 and ND2, with only one nand gate in ND1, the enable signal is always high, and N nand gates in ND2, controlled by the enable signal EN. Two input signals inn, inp with a time difference in rising edge from two output terminals of the signal generating circuit are respectively connected to the input of the TD in the time amplifier.
In the present invention, as shown in fig. 4, an operation schematic diagram of the signal amplifying circuit in the case of EN =1 is shown, fig. 5 is an operation schematic diagram of the signal amplifying circuit in the case of EN =0 according to an embodiment of the present invention, and fig. 6 is a timing schematic diagram of the signal amplifying circuit according to an embodiment of the present invention. When the rising edge of the signal inn arrives and the rising edge of inp does not arrive, the enable signal EN is 1, ND1 and ND2 in TD can work normally, the charging and discharging capacity of the node is strongest, the two ring oscillators oscillate at the maximum frequency, and the time difference delta T of the rising edges of the two input signals inn and inp is in Conversion into a signal T Ro1 And T Ro2 Phase difference phi between in The output signals outn, outp remain at 0. After the rising edge of the signal inp arrives, after a certain delay, the enable signal EN of the ND2 jumps from 1 to 0, and all ND2 gates in the td cannot work normally (shown by a dotted line), as shown in fig. 5. At this time, the charging and discharging capability of the corresponding node is weakest, so that the periods of the two ring oscillators are lengthened by N +1 times. Finally, the edge detector captures the signal after the periodic amplification to generate output signals outn and outp, and the signal T is generated in the process of switching the ring oscillator from high frequency to low frequency Ro1 And T Ro2 The period after switching is increased to (N + 1) times the original period, and the delay time difference of the corresponding rising edge of the output signal is also amplified to (N + 1) times the original period.
In an embodiment of the invention, the time difference between the rising edges of the pair of signals with the phase difference is Δ T in The time difference of the rising edges of the pair of signals after phase difference amplification is delta T out Then Δ T out ＝G·ΔT in And G is the amplification factor of the signal amplification circuit. That is, Δ T out And Δ T in There is a linear relationship between them.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a signal conversion circuit according to an embodiment of the present invention, the signal conversion circuit includes:
and the delay chain comprises two input ends and a plurality of output ends, the two input ends of the delay chain are respectively connected with the two output ends of the signal amplification circuit one by one, and the delay chain is used for sampling the pair of signals to obtain the digital signals.
The priority encoder comprises a plurality of input ends and an output end, the input ends of the priority encoder are respectively connected with the output ends of the delay chain one by one, and the priority encoder is used for detecting a first edge bit in the digital signal segment and outputting the least significant bit of the first edge bit as an original random number.
It can be understood that this embodiment is only one possible specific structure of the signal conversion circuit, and those skilled in the art can make any other adaptive changes to the internal structure of the signal conversion circuit on the premise of ensuring that the signal conversion circuit can convert the pair of signals after the phase difference amplification into the original random number and output the original random number. For example, as shown in fig. 7, the delay chain includes m not gates and m D flip-flops, m not gates are sequentially connected in series, m D flip-flops are sequentially connected in series, D input terminals of m D flip-flops are connected to output terminals of m not gates one by one, an input terminal of a first not gate is connected to one input terminal of the time amplifier, and clock terminals of m D flip-flops are connected to another input terminal of the time amplifier. In yet another example, a plurality of not gates are connected to one D flip-flop.
In this embodiment, the signal conversion circuit structure is shown in fig. 7, and includes a delay chain and a priority encoder. The signals outn and outp are a pair of signals (amplified oscillation signals) subjected to phase difference amplification by the signal amplification circuit. Since the unit with the smallest delay in the ASIC circuit is a not gate (inverter), the time-to-digital converter uses an inverter and a DFF to form a delay chain. After amplification by the time-to-digital converter, the signal is fed into a delay chain of m inverters and sampled by a set of DFFs. The output of each set of DFFs represents a fraction of the distance the rising edge of the signal outp has traveled in the inverter when outn has come after amplification of the phase difference. And sampling the oscillation signal amplified by the delay difference by using an inverter delay chain, thereby completing the conversion of the signal from time to digital. The priority encoder consists of a 2-input exclusive nor gate and a 2-input exclusive nor gate. The priority encoder detects a first edge position in the segment, in which even bits are encoded as "0" and odd bits are encoded as "1", and takes the Least Significant Bit (LSB) of the first edge position as an original random number.
In this embodiment, the delay of the delay chain is greater than the rise edge delay difference of the signals outn and outp under the worst condition, so as to prevent the situation that the edge position is not sampled, and improve the robustness. The expected result of a delay chain is a series of "01" interspersed with either "00" or "11". However, some flip-flops may be driven into a metastable state due to timing violations in sampling, thereby creating "bubbles". Bubbles can be generated when certain DFFs are driven into a metastable state. Thus, having the priority encoder always encode the first edge present in a segment ignores other edges, but achieves the effect of filtering out "bubbles". As shown in fig. 8.
Referring to fig. 9, fig. 9 is a schematic flowchart of a random number generating method according to an embodiment of the present invention, where the random number generating method is applied to a random number generating circuit, the random number generating circuit includes a signal generating circuit, a signal amplifying circuit, and a signal converting circuit, which are connected in sequence, and the random number generating circuit may be the random number generating circuit shown in any one of fig. 1 to 8, and the method includes the following operations:
an operation S910 of generating a pair of signals having a phase difference by the signal generating circuit;
an operation S920 of amplifying, by the signal amplifying circuit, a phase difference of the pair of signals;
in operation S930, the pair of signals after the phase difference amplification is converted into an original random number by the signal conversion circuit and then output.
In an embodiment of the present invention, a pair of signals having a phase difference is generated by the signal generating circuit, and the phase difference conforms to a gaussian distribution.
In an embodiment of the invention, the time difference between the rising edges of the pair of signals with the phase difference is Δ T in The time difference of the rising edges of the pair of signals after phase difference amplification is delta T out Then Δ T out ＝G·ΔT in And G is the amplification factor of the signal amplification circuit.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the random number generation method described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a true random number generator according to an embodiment of the present invention, where the true random number generator includes the random number generating circuit shown in any one of fig. 1 to 8 and an original random number processing circuit, the random number generating circuit is configured to generate an original random number, and the original random number processing circuit is configured to process the original random number to generate an external random number.
The intuitive description of true random number generators refers to carriers that use unpredictable phenomena as sources of entropy to generate random numbers. The true random number generator can be composed of four parts of a digital noise source, post-processing, entropy source testing and online testing. The digitized noise source includes an entropy source and an entropy extraction module. The entropy source is the device that generates unpredictable random behavior and is the only unpredictable part of the true random number generator. An analog signal with unpredictability generated by an entropy source generates an original random number through an entropy extraction module. The original random number may be used for internal testing. The original random number will typically have some statistical drawbacks, such as an offset (the probabilities of "0" and "1" are not equal) compared to the ideal case and an autocorrelation between the output bits. Therefore, the original statistical defects can be reduced or even eliminated through post-processing, and the external random numbers are generated. The entropy extraction module and the post-processing module are well defined and are usually implemented in the form of digital circuits. It is particularly emphasized that the entropy extraction module and the post-processing module do not generate new randomness. In-line testing, also known as embedded testing or continuous testing, is used to detect defects in the original random numbers generated. And the entropy source detection is used for quickly detecting faults in the running process of the entropy source. According to the embodiment of the invention, the random number generating circuit can replace the digital noise source to generate the original random number, and the problem that the resolution is limited by the delay limit of the standard unit of the digital circuit is solved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the circuit may be divided into only one logic function, and may be implemented in other ways, for example, multiple circuits or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or circuits, and may be in an electrical, mechanical or other form.
The circuits described as separate parts may or may not be physically separate, and parts shown as circuits may or may not be physical circuits, may be located in one place, or may be distributed over a plurality of network circuits. Part or all of the circuits can be selected according to actual needs to achieve the purpose of the scheme of the embodiment.
In addition, functional circuits in the embodiments of the present application may be integrated into one processing circuit, or each circuit may exist alone physically, or two or more circuits may be integrated into one circuit. The integrated circuit can be realized in a hardware form, and can also be realized in a software functional circuit form. The integrated circuit, if implemented in software functional circuitry and sold or used as a stand-alone product, may be stored in a computer readable storage medium.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, service circuit, or data center to another website site, computer, service circuit, or data center by wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device including one or more available media integrated service circuits, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.
The technical solutions provided by the present invention are introduced in detail, and the present invention applies specific examples to explain the principles and embodiments of the present invention, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A random number generation circuit, comprising:
the signal generating circuit, the signal amplifying circuit and the signal converting circuit;
the signal generating circuit comprises two input ends and two output ends, the two input ends of the signal generating circuit are both connected with an external signal input end, and the signal generating circuit is used for generating a pair of signals with phase difference;
the signal amplifying circuit comprises two input ends and two output ends, the two input ends of the signal amplifying circuit are connected with the two output ends of the signal generating circuit one by one, the signal amplifying circuit is used for amplifying the phase difference of the pair of signals, and the signal amplifying circuit is a time amplifier;
the signal conversion circuit comprises two input ends and an output end, the two input ends of the signal conversion circuit are connected with the two output ends of the signal amplification circuit one by one, and the signal conversion circuit is used for converting the pair of signals after the phase difference amplification into original random numbers and then outputting the original random numbers.
2. The random number generating circuit of claim 1, wherein the signal generating circuit comprises two first ring oscillators that are identical in component parts and identical in topology.
3. The random number generating circuit of claim 2, wherein each of said first ring oscillators includes a plurality of not-gates and a nand-gate connected in series in sequence, one input of said nand-gate being connected to said external signal input, an output of said nand-gate being connected to an input of said signal amplifying circuit.
4. The random number generation circuit of claim 1, wherein the signal amplification circuit comprises two time amplification units having the same component and topology.
5. The random number generation circuit according to claim 4, wherein the time amplification unit includes:
the second ring oscillator comprises a plurality of adjustable NAND gates which are sequentially connected in series, and one output end of the signal generation circuit is connected with one input end of any one adjustable NAND gate;
the input end of the NOT gate is connected with the output end of any one of the adjustable NAND gates;
an edge detector having an input coupled to the output of the not gate and an output coupled to the input of the time-to-digital converter, the edge detector configured to generate an enable signal for the second ring oscillator and an output signal if the periodically amplified signal is detected, or the edge detector configured to generate an output signal if the periodically amplified signal is detected, the output signal being one of the pair of signals after phase difference amplification.
6. The random number generation circuit of claim 5, wherein the adjustable NAND gate comprises:
the enabling signals of 1 of the N +1 parallel NAND gates are kept high, the enabling signals of the N parallel NAND gates are the external signals, and N is a positive integer larger than 0.
7. The random number generation circuit according to claim 5 or 6, wherein the edge detector comprises:
the D input end of one of the two D flip-flops is connected with a high level, the clock end of the one D flip-flop is connected with the output end of the NOT gate, the D input end of the other of the two D flip-flops is connected with the Q output end of the one D flip-flop, the clock end of the other D flip-flop is connected with the output end of the NOT gate, and the Q output end of the other D flip-flop is connected with the input end of the signal conversion circuit;
the Q output end of the D trigger is connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the external signal.
8. The random number generation circuit of claim 1, wherein the signal conversion circuit comprises:
the delay chain comprises two input ends and a plurality of output ends, the two input ends of the delay chain are respectively connected with the two output ends of the signal amplification circuit one by one, and the delay chain is used for sampling the pair of signals to obtain digital signals;
and the priority encoder comprises a plurality of input ends and an output end, the input ends of the priority encoder are respectively connected with the output ends of the delay chain one by one, and the priority encoder is used for detecting a first edge bit in the digital signal segment and outputting the least significant bit of the first edge bit as an original random number.
9. A random number generation method is applied to a random number generation circuit, the random number generation circuit comprises a signal generation circuit, a signal amplification circuit and a signal conversion circuit which are sequentially connected, the signal amplification circuit is a time amplifier, and the method comprises the following steps:
generating, by the signal generation circuit, a pair of signals having a phase difference;
amplifying, by the signal amplification circuit, a phase difference of the pair of signals;
and converting the pair of signals after the phase difference amplification into original random numbers through the signal conversion circuit and then outputting the original random numbers.
10. A true random number generator comprising the random number generating circuit of any one of claims 1 to 8 and a raw random number processing circuit;
the random number generating circuit is used for generating an original random number;
the original random number processing circuit is used for processing the original random number to generate an external random number.
CN202210913322.XA 2022-07-29 2022-07-29 Random number generation circuit and method, true random number generator Pending CN115145541A (en)

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CN202210913322.XA CN115145541A (en) 2022-07-29 2022-07-29 Random number generation circuit and method, true random number generator

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