CN115145108A

CN115145108A - EUV (extreme ultraviolet) grade substrate, EUV mask base plate, EUV mask plate and manufacturing method thereof

Info

Publication number: CN115145108A
Application number: CN202211075952.0A
Authority: CN
Inventors: 季明华; 董于虎; 黄早红
Original assignee: Shanghai Chuanxin Semiconductor Co ltd
Current assignee: Shanghai Chuanxin Semiconductor Co ltd
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2022-10-04
Anticipated expiration: 2042-09-05
Also published as: KR102609547B1; CN115145108B; JP7296183B1; JP2024036280A

Abstract

The invention provides an EUV (extreme ultraviolet) grade substrate, an EUV mask base plate, an EUV mask plate and a manufacturing method thereof, wherein an organic polymer material layer with a negative thermal expansion coefficient is covered on a substrate, induced crack treatment is carried out on the organic polymer material layer to form corresponding cracks, and a Spin-on Carbon layer (SOC) is further covered in the cracks and on the surface of the organic polymer material layer, so that the thermal expansion coefficient of the surface of the EUV grade substrate is less than or equal to 0.1 ppm/DEG C, and further the EUV grade substrate, the EUV mask base plate and the EUV mask plate with low cost, high performance and low defects can be obtained.

Description

EUV (extreme ultraviolet) grade substrate, EUV mask base plate, EUV mask plate and manufacturing method thereof

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to an EUV (extreme ultraviolet) grade substrate, an EUV mask base plate, an EUV mask plate, a manufacturing method of the EUV mask plate and a substrate.

Background

With the continuous development of the integrated circuit manufacturing industry, advanced photolithography techniques such as extreme ultraviolet lithography (EUVL) have been widely used. Among them, EUV reticles (photo masks) are important components in the lithographic process. In the photolithography process, a photoresist layer such as a photoresist is coated on a surface of a wafer, after the photoresist layer is dried, a pattern on an EUV reticle is exposed on the photoresist layer by a specific light source (for example, extreme ultraviolet EUV) through an exposure apparatus, then, the exposed photoresist layer is developed by a developer, and the developed photoresist layer pattern is used as a mask to perform processes such as etching on the wafer, and finally, the pattern on the EUV reticle is transferred onto the wafer.

Since EUV lithography uses a reflective optical system, the accuracy of EUV lithography is affected by slight thermal expansion of EUV reticles, and it is therefore critical to produce low thermal expansion, high flatness EUV grade substrates, EUV mask reticles, and EUV reticles.

Disclosure of Invention

The invention aims to provide an EUV (extreme ultraviolet) grade substrate, an EUV mask base plate, an EUV mask plate and a manufacturing method thereof, which can be beneficial to reducing the defects of the EUV mask plate and further improving the EUV photoetching effect.

To achieve the above object, the present invention provides a method of manufacturing an EUV grade substrate, comprising:

providing a substrate, wherein the substrate is a quartz substrate with a thermal expansion coefficient less than or equal to 1 ppm/DEG C;

forming a layer of organic polymeric material having a negative coefficient of thermal expansion on the substrate, the layer of organic polymeric material having a coefficient of thermal expansion of-10 ppm/DEG C to 0 ppm/DEG C, the layer of organic polymeric material having a modulus of elasticity less than the modulus of elasticity of the substrate;

subjecting the organic polymer material layer to a crack-inducing treatment to form respective cracks;

and spin-coating a carbon material with a positive thermal expansion coefficient on the surface of the organic polymer material layer to form a spin-coating carbon layer which fills the corresponding crack and has a flat surface so as to form the EUV level substrate, wherein the thermal expansion coefficients of the spin-coating carbon layer and the organic polymer material layer are mutually compensated, so that the thermal expansion coefficient of the surface of the EUV level substrate is less than or equal to 0.1 ppm/DEG C.

Optionally, the ratio of the elastic modulus of the organic polymer material layer to the substrate is 0.1-0.9.

Optionally, the organic polymer material layer includes a polyimide material containing an amide structure.

Optionally, forming a layer of organic polymer material having a negative coefficient of thermal expansion on the substrate comprises: spin coating or depositing an organic polymeric material on the surface of the substrate to a desired thickness; curing the organic polymer material to form the organic polymer material layer.

Optionally, the step of curing the organic polymer material comprises: and baking and curing the organic polymer material for multiple times at different temperatures in a vacuum or nitrogen or inert gas atmosphere in a temperature decreasing manner to form the organic polymer material layer.

Optionally, the step of performing crack induction treatment on the organic polymer material layer includes: and baking the organic polymer material layer for multiple times to form corresponding cracks inside the organic polymer material layer.

Optionally, the temperature range of each baking in the induced crack treatment is 100-250 ℃, and the baking time is 1-3 hours.

Optionally, the thickness of the organic polymer material layer is from 20nm to 100nm; and/or the size of the crack is 2 nm-50 nm.

Based on the same inventive concept, the invention also provides a manufacturing method of the EUV mask base plate, which comprises the following steps:

forming an EUV level substrate by adopting the manufacturing method of the EUV level substrate;

and sequentially forming a reflecting film stack layer and an absorbing layer on the spin-coated carbon layer of the EUV substrate to form an EUV mask base plate.

Alternatively, the method for manufacturing the EUV mask blank, after forming the reflective film stack layer on the spin-on carbon layer and before forming the absorber layer, further comprising: forming a cover layer on the reflective film stack layer; and the number of the first and second groups,

after forming the absorption layer, further comprising: back to the spun-on carbon layer on the substrate a back side conductive layer is formed on the surface of the substrate.

Based on the same inventive concept, the invention also provides a manufacturing method of the EUV mask, which comprises the following steps:

forming an EUV mask base plate by adopting the manufacturing method of the EUV mask base plate;

etching an absorber layer of the EUV mask substrate to form a first pattern in the absorber layer;

etching the absorbing layer and the reflecting film stack layer of the EUV mask base plate at the periphery of the first pattern, and stopping etching on the surface of the spin-coated carbon layer of the EUV mask base plate to form a second pattern.

Based on the same inventive concept, the present invention also provides an EUV grade substrate comprising:

a substrate, which is a quartz substrate having a coefficient of thermal expansion of 1 ppm/DEG C or less;

a layer of organic polymeric material having a negative coefficient of thermal expansion formed on the substrate, and having a coefficient of thermal expansion of-10 ppm/DEG C to 0 ppm/DEG C, the layer of organic polymeric material having a modulus of elasticity less than that of the substrate, the layer of organic polymeric material having corresponding cracks formed therein;

a removable spin-on carbon layer formed on a surface of the organic polymer material layer and filling the corresponding cracks, the spin-on carbon layer having a positive coefficient of thermal expansion and compensating for a coefficient of thermal expansion of the organic polymer material layer such that a coefficient of thermal expansion of an EUV level substrate surface is less than or equal to 0.1ppm/° C.

Optionally, the material of the organic polymer material layer includes a polyimide material containing an amide structure.

Based on the same inventive concept, the present invention also provides an EUV mask blank, comprising:

an EUV-grade substrate according to the present invention;

a reflective film stack layer formed on a spin-on carbon layer of the EUV level substrate;

and the absorption layer is formed on the reflection film stack layer.

Alternatively to this, the first and second parts may, the EUV mask blank further comprises:

a cover layer formed between the top reflective film of the reflective film stack layer and the absorber layer; and a back conductive layer formed on a surface of the EUV level substrate facing away from the reflective film stack layer.

Based on the same inventive concept, the invention also provides an EUV mask blank, which is provided with the EUV mask base plate, and the EUV mask blank is also provided with a first pattern and a second pattern, wherein the first pattern is formed in the absorption layer of the EUV mask base plate, and the second pattern penetrates through the absorption layer and the reflection film stack layer of the EUV mask base plate and exposes the surface of the spin-coated carbon layer of the EUV mask base plate.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. the near-zero Coefficient of Thermal Expansion (CTE) of the surface of the EUV substrate is achieved by forming an organic polymer material layer having a negative coefficient of thermal expansion on a substrate of DUV-grade or lower quartz glass or the like, subjecting the organic polymer material layer to a crack-inducing treatment to form respective cracks therein, further spin-coating a carbon material (having a positive coefficient of thermal expansion) on the organic polymer material layer and filling the cracks, repairing the defects, forming a flat, smooth surface to a degree of planarization with a surface defect size of less than 10nm, and causing the coefficients of thermal expansion CTE of the organic polymer material layer and the spin-coated carbon layer to compensate each other.

2. The spin-coated carbon layer can be used as a regenerated 'sacrificial layer', can be easily removed through oxygen plasma ashing, and can be recycled for manufacturing a new EUV mask without reducing the surface quality of the EUV mask so as to further reduce the manufacturing cost of the new EUV mask. Among them, the spin-coated carbon layer includes Brewer Science, inc. in the United states, which has been commercially available.

Drawings

FIG. 1 is a schematic cross-sectional view of an EUV reticle of the prior art.

Fig. 2 to 4 are schematic structural diagrams of five typical defects in an existing EUV reticle or EUV mask substrate.

FIG. 5 is a flow diagram of a method of fabricating an EUV level substrate in accordance with an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional structure of a method of manufacturing an EUV class substrate in accordance with an embodiment of the present invention.

Fig. 7-8 are schematic diagrams of spin-on carbon layer fill capability and surface planarization.

FIG. 9 is a schematic cross-sectional view of an EUV mask blank manufacturing method according to an embodiment of the present invention.

FIG. 10 is a schematic flow chart of a method of fabricating an EUV reticle according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of an EUV reticle manufacturing method according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view illustrating a substrate recycling method according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on …," it can be directly on, adjacent, connected, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, sections and/or processes, these elements, components, regions, layers, sections and/or processes should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, portion and/or process from another element, component, region, layer, portion and/or process. Thus, a first element, component, region, layer, section and/or process discussed below could be termed a second element, component, region, layer, section and/or process without departing from the teachings of the present invention.

Spatially relative terms such as "under …", "under …", "under …", "over …", "over", "on top", "on bottom", "on front", "on back", etc., may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "under" or "beneath" or "under" or "on the bottom surface or" on the back surface of "other elements or features would then be oriented" on "or" top "or" right "the other elements or features. Thus, the exemplary terms "below …", "below …" and "behind …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As described in the background, it is critical to manufacture low cost, low defect, high performance EUV reticles.

EUV reticles are used for the key components of EUV lithography (EUVL) systems. EUV lithography employs a scanner that uses light in the Extreme Ultraviolet (EUV) region (i.e., exposure light) having a wavelength of about 1nm to about 100nm, for example, 13.6nm. Since the optical material is opaque to EUV radiation, EUV reticles are reflective reticles. The blank for EUV reticles typically has a substrate (e.g., glass or quartz, etc.), a reflective film stack (e.g., of Mo and Si alternately stacked, also known as a reflective structure) for reflecting exposure light, and an absorber (which may be a single layer film or a multilayer film) for absorbing the exposure light and which is etched into a prescribed pattern (i.e., a circuit pattern) required for integrated circuit fabrication, stacked in that order. The absorber layer has a low EUV reflectivity, for example less than 3-5%.

Referring to fig. 1 to 4, a conventional EUV mask blank (also called EUV mask blank, blank EUV reticle) generally includes a substrate 100, a reflective film stack 101, a capping layer 102, and an absorber layer 103, and the conventional EUV reticle forms a first pattern 103a and a second pattern 104 in the EUV mask blank.

The inventor researches and discovers that the EUV lithography technology is very sensitive to defects of EUV mask substrates and EUV reticles, wherein one of the sources of the defects is defects induced by surface defects (such as pits, slits, trenches, bumps, contamination particles or scratches, etc.) of the substrate 100, and specifically includes: a) A first type of defects 101a, which are caused by existing pit (pits) (or slits, scratches) defects 100a with a large size (> 10nm size) on the surface of the substrate 100, as shown in fig. 2, the pit defects 100a on the substrate 100 are formed on the surface of the substrate 100 by Chemical Mechanical Polishing (CMP) and cleaning processes, and are induced in the film layers of the reflective film stack layer 101 deposited directly upward from the substrate 100, thereby forming first type of defects 101a; b) A second type of defects 101b caused by bump defects or contaminant particles with larger sizes (> 10 nm) existing on the surface of the substrate 100, as shown in fig. 3, the bump defects 101b or contaminant particles on the substrate 100 are formed on the surface of the substrate 100 by Chemical Mechanical Polishing (CMP), cleaning, and other processes, and are induced from the substrate directly upward to each film layer of the reflective film stack layer 101 deposited upward, and during the upward induction, the defect size may be increased due to stress, thickness variation, and other factors, so as to form the second type of defects 101b; c) A third type of defect 101c, which is caused by a defect 100c (a pit, a slit, a bump, a contaminant particle, a scratch, or the like) having a relatively large size (> 10nm size) existing on the surface of the substrate 100, is induced in each film layer of the reflective film stack layer 101 deposited upward from the substrate 100 in a direction directly upward, and may be shifted in position in a lateral direction due to stress, thickness variation, or the like during the upward induction, as shown in fig. 4, thereby forming a third type of defect 101c.

All of the above defects on the substrate surface can cause defects of the EUV reticle, thereby affecting the final effect of EUV lithography using the EUV reticle.

In the prior art, in order to reduce the defects introduced by the substrate 100, quartz glass having a relatively flat and smooth surface is generally selected. With the development of the technology, in order to solve the problem that defects are further introduced to the substrate 100 due to thermal expansion in the subsequent process, it is further proposed to use silicon, microcrystalline glass (Zerodur), ultra low expansion coefficient quartz glass (ULE, also called zero expansion glass) or the like instead of glass as the substrate 100.

However, no matter what material is used for the substrate 100 in the prior art, the synthesis difficulty and the processing cost are high, and the performance of the EUV mask is affected by defects on the surface of the substrate caused by the processes of Chemical Mechanical Polishing (CMP) and cleaning.

Accordingly, the invention provides an EUV grade substrate, an EUV mask blank and a manufacturing method thereof, which can provide an EUV grade substrate with a process surface with a thermal expansion coefficient close to 0, and further can manufacture the EUV grade substrate, the EUV mask substrate and the EUV mask blank with low cost, low thermal expansion and high flatness.

The following describes the technical solution of the present invention in detail with reference to fig. 5 to fig. 12 and the specific embodiment.

Referring to fig. 5, an embodiment of the invention provides a method for manufacturing an EUV substrate, which includes:

s11, providing a substrate, wherein the substrate is a quartz substrate with a thermal expansion coefficient less than or equal to 1 ppm/DEG C;

s12, forming an organic polymer material layer with a negative thermal expansion coefficient on the substrate, wherein the thermal expansion coefficient of the organic polymer material layer is-10 ppm/DEG C to 0 ppm/DEG C, and the elastic modulus of the organic polymer material layer is smaller than that of the substrate;

s13, carrying out induced crack treatment on the organic polymer material layer to form corresponding cracks;

s14, spin-coating a carbon material with a positive thermal expansion coefficient on the surface of the organic polymer material layer to form a spin-coating carbon layer which fills the corresponding crack and has a flat surface so as to form the EUV level substrate, wherein the thermal expansion coefficients of the spin-coating carbon layer and the organic polymer material layer are mutually compensated, so that the thermal expansion coefficient of the surface of the EUV level substrate is less than or equal to 0.1 ppm/DEG C.

Referring to fig. 6, in step S11, the substrate 200a may be a DUV-grade or lower quartz glass substrate made of a synthetic quartz glass material having a low positive thermal expansion coefficient, and a thermal expansion coefficient CTE at a corresponding operating temperature (e.g., DUV exposure temperature or EUV exposure temperature) of less than or equal to 1 ppm/degree c, for example. Among them, the DUV-grade quartz glass substrate is a standard substrate for 193nm, 248nm, or 365nm DUV lithographic blank mask reticles, which may have a high transmittance (e.g., greater than 80% transmittance) in the DUV range.

With continued reference to fig. 6, in step S12, first, the upper surface (i.e., the working surface) of the substrate 200a may be cleaned, and an organic polymer material having a negative thermal expansion coefficient may be deposited on the upper surface of the substrate 200a by spin coating or other suitable deposition process. The organic polymer material is then cured to form the desired organic polymer material layer 200b. Wherein the coefficient of thermal expansion of the organic polymer material layer 200b at an operating temperature (e.g., EUV exposure temperature) is, for example, -10 ppm/deg.c to 0 ppm/deg.c, and the elastic modulus of the organic polymer material layer 200b is smaller than that of the base 200a, thereby facilitating easy crack generation of the organic polymer material layer 200b in step S13 and facilitating the CTE of the finally formed EUV-grade substrate to be close to 0.

Alternatively, the ratio of the elastic moduli of the organic polymer material layer 200b and the substrate 200a is 0.1 to 0.9, thereby being more advantageous for the organic polymer material layer 200b to generate cracks in step S13.

The thickness of the organic polymer material layer 200b with negative thermal expansion coefficient can be set as required, for example, 20nm to 100nm, so that enough cracks can be formed in the subsequent step S13, and most of the formed cracks cannot penetrate through the organic polymer material layer 200b.

As an example, an organic polymer material is uniformly coated on the surface of the substrate 200a by using an automatic coating machine, and further placed in a high-temperature oven, and the organic polymer material with negative thermal expansion coefficient is subjected to multiple baking and curing at different temperatures (for example, 350 ℃, 250 ℃, 60 ℃) by using a step procedure cooling under a vacuum or nitrogen or inert gas atmosphere with a pressure of 10 torr to 200 torr, and finally cooled to room temperature to form the solid organic polymer material layer 200b.

Alternatively, the organic polymer material layer 200b having a negative thermal expansion coefficient is a polyimide material including an amide-containing structure, which may be a polyimide film or a polyamide-imide film, for example.

In other embodiments of the present invention, the organic polymer material may be selected from any suitable material, such as organic polymer materials having the formula R1- (C ≡ C) _n -R2, n is an integer multiple of 2, R1 and R2 can be polar or non-polar, inorganic or organic groups, the polar groups comprising O, S, N or P, such as hydroxyl, alkoxy, carboxyl, esterified hydroxyl, carbamate, urea, amide or imide groups, and the like.

With continued reference to fig. 6, in step S13, a crack-inducing treatment is performed on the cured organic polymer material layer 200b having a negative thermal expansion coefficient at a suitable temperature, so that the organic polymer material layer 200b is cracked to form a desired crack 200c.

As an example, in this step, the step of performing crack induction treatment on the organic polymer material layer 200b includes: the organic polymer material layer 200b is baked for a plurality of times, so that corresponding cracks are formed inside the organic polymer material layer 200b. And the temperature of each baking for the crack induction treatment is lower than the temperature at which the organic polymer material layer 200b is melted.

The principle that cracks can be induced to generate through a baking mode is as follows: the elastic modulus of the substrate 200a is many times that of the organic polymer material layer 200b (for example, the elastic modulus of the quartz glass of the substrate 200a is 7 times that of the polyimide in the organic polymer material layer 200 b), and the thermal expansion coefficient of the substrate 200a is positive to generate tensile stress, the thermal expansion coefficient of the organic polymer material layer 200b is negative to generate compressive stress, and the thermal expansion surface stresses of the substrate 200a and the organic polymer material layer 200b are opposite, so that when the cured organic polymer material layer 200b is baked, cracks 200c can be irreversibly formed in the organic polymer material layer 200b having a negative thermal expansion coefficient from room temperature to the baking temperature.

As an example, in the step, the temperature range of each baking in the crack induction treatment is 100 ℃ to 250 ℃, and the baking time is 1 hour to 3 hours. Specifically, for example, the organic polymer material layer 200b is baked in a furnace for 1 to 3 hours at a baking temperature (e.g., about 100 to 250 ℃) lower than the melting temperature (e.g., 400 ℃) of the organic polymer material layer 200b, and then after the baking temperature is cooled to room temperature or the like, the corresponding cracks 200c are formed in the organic polymer material layer 200b.

Of course, in other embodiments of the present invention, the organic polymer material layer 200b may be subjected to a crack inducing treatment in any other suitable manner to generate corresponding cracks, such as applying mechanical stress, surface scratching, and the like.

Preferably, in this step, the distribution density of the cracks 200c in the organic polymer material layer 200b is substantially uniform, and the size of the cracks 200c is from 2nm to 50nm.

It should be understood that the cracks 200c may vary in shape and size from the top surface of the substrate 200a to the top surface of the organic polymer material layer 200b having a negative coefficient of thermal expansion (as shown in fig. 6), there may be cracks 200c that may penetrate through the organic polymer material layer 200b, there may be cracks 200c that may not penetrate through the organic polymer material layer 200b, there may be cracks 200c that open on the top surface of the organic polymer material layer 200b, and there may be cracks 200c that open on the bottom surface of the organic polymer material layer 200b.

Referring to fig. 6, in step S14, a carbon material with a positive thermal expansion coefficient is spin-coated on the surface of the organic polymer material layer 200b by a spin-coating process to form a spin-coated carbon layer 201 filling the cracks 200c on the top surface of the organic polymer material layer 200b, wherein the spin-coated carbon layer 201 has a flat and smooth top surface, and the top surface of the spin-coated carbon layer 201 can be planarized to a surface defect size below 10nm. Thereby realizing an EUV-grade substrate. And the spin-on carbon layer 201 has a positive coefficient of thermal expansion and compensates for the coefficient of thermal expansion of the organic polymer material layer 200b such that the coefficient of thermal expansion of the EUV-grade substrate surface is less than or equal to 0.1ppm/° c (e.g., less than or equal to 0.01ppm/° c).

The specific process of forming the spin-on carbon layer 201 includes: wet cleaning the surface of the organic polymer material layer 200b having a negative thermal expansion coefficient; then, a spin coating process spin-coats a carbon material to a desired thickness on the surface of the organic polymer material layer 200b having a negative thermal expansion coefficient; next, soft baking the spin-coated carbon material at a first temperature (e.g., 100 ℃ C. To 200 ℃ C., such as 170 ℃ C.); thereafter, the spun-on carbon material is hard baked at a second temperature (e.g., 250 ℃ to 500 ℃) that is higher than the first temperature, thereby forming a spun-on carbon layer 201. The carbon material spin-coated on the surface of the organic polymer material layer 200b with the negative thermal expansion coefficient is heated at the first temperature and triggers a crosslinking reaction to partially crosslink the carbon main chain polymer therein, and the spin-coated carbon material is maintained to have a certain degree of reflux, which is beneficial to forming a more flat surface. Further, the spin-coated carbon material is heated at the second temperature and undergoes a more severe cross-linking reaction to further cross-link the carbon backbone polymer therein, and the reflow of the spin-coated carbon material is reduced, thereby finally forming the solid spin-coated carbon layer 201.

As an example, the spin-on carbon material (which has been commercialized by including Brewer Science, inc., USA) is a liquid spin-on carbon composition comprising a solvent, a carbon backbone polymer, for example, comprising at least one of propylene glycol methyl ether PGME, propylene glycol methyl ether acetate PGMEA, cyclopentanone, cyclohexanone, polyhydroxystyrene, polyacrylate, OR polymethylmethacrylate, and a crosslinking agent comprising A- (OR) _x 、A-(NR) _x 、A-(OH) _x 、A-(C＝C) _x And A- (C ≡ C) _x A is a single molecule, a polymer or a second polymer having a molecular weight ranging from 100 to 20000, R is a hydrocarbon group, a cycloalkyl group, a cycloalkylepoxy group or C ₃ -C ₁₅ A heterocyclic group; OR is an alkoxy, cycloalkoxy, carbonate, alkylcarbonate, alkylcarboxylate, tosylate OR mesylate group; NR is an alkylamido or alkylamino group; x ranges from 2 to 1000 or C ₃ -C ₁₅ A heterocyclic group; OR is alkoxy, cycloalkoxy, carbonate, alkyl carbonate,An alkylcarboxylate, tosylate or mesylate group, NR is an alkylamide or alkylamino group, and x ranges from 2 to 1000. The carbon backbone polymer and the crosslinking agent are uniformly dissolved in a solvent and spin-coated onto the surface of the organic polymer substrate 200. In some embodiments, the solvent is an organic solvent, for example, including at least one of a ketone, an alcohol, a polyol, an ether, a glycol ether, a cyclic ether, an aromatic hydrocarbon, an ester, a propionate, a lactate ester, an alkylene glycol monoalkyl ether, an alkyl lactate ester, an alkyl alkoxy propionate ester, a cyclic lactone, a ring-containing monoketone compound, an alkylene carbonate, an alkyl alkoxy acetate, an alkyl pyruvate, a lactate ester, an ethylene glycol alkyl ether acetate, diethylene glycol, propylene glycol alkyl ether acetate, an alkylene glycol alkyl ether ester, an alkylene glycol monoalkyl ester, and the like.

The spin-on carbon layer 201 formed therein is thick enough to fill and bury the defects such as cracks 200c on the top surface of the organic polymer material layer 200b having a negative thermal expansion coefficient, thereby improving the top surface to be flat enough to prevent the defects from inducing the defects of the reflective film stack layer 202 and the absorption layer 204 deposited later; on the other hand, the organic polymer material layer 200b is thin enough and opaque, and the thermal expansion coefficient of the surface of the EUV grade substrate is made to be close to 0 while the surface of the organic polymer material layer 200b with the negative thermal expansion coefficient is reset to be a new substrate which is flatter and has fewer defects, so that the manufacturing of an EUV mask base plate and an EUV mask plate with lower cost, fewer defects and higher performance can be facilitated.

As an example, in step S14, a liquid carbon material is spin-coated onto the surface of the organic polymer material layer 200b having a negative thermal expansion coefficient at a speed of 1500pm/60S until the thickness of the spin-coated carbon material satisfies a requirement; then, in N ₂ Soft baking the spin-coated carbon material at 100-200 ℃ for 1min-5min in an atmosphere; then, in N ₂ Hard baking is carried out on the spin-coated carbon material at 200-400 ℃ for 5-20min in an atmosphere, and finally a solid spin-coated carbon layer 201 with the thickness not more than 20nm (for example, 10nm or less than 10 nm) is formed, so that the EUV substrate is obtained.

In step S14, the spin-on carbon layer 201 is formed by spin-coating, which has a simple process and low cost, and has a stronger deep gap filling capability and a local and global planarization capability compared to a carbon layer formed by CVD, ALD, sputtering, or other methods, and can form a globally flat process surface (the top surface of which can be planarized to a dimension less than 10 nm) on the organic polymer material layer 200b having a negative thermal expansion coefficient. For example, the organic polymer material layer 200b with negative thermal expansion coefficient has different line widths of cracks (e.g., some of the gaps L1 are large and some of the gaps L2 are small in fig. 7), and the intervals of the cracks are also different in size (e.g., some of the gaps of the cracks W1 are large and some of the gaps of the cracks W2 are small in fig. 7), and the spin-coating carbon layer formed by the spin-coating method can fill the cracks and bury the gaps therein, and form a globally flat process surface. For another example, the crack on the top surface of the organic polymer material layer 200b with negative thermal expansion coefficient is a slit with high aspect ratio, as shown in fig. 8, after the spin-on carbon layer is formed by the spin-on method, the bottom of the crack of the organic polymer material layer 200b with negative thermal expansion coefficient can be filled with the feature of smaller carbon atom size, and after the crack is filled, a globally flat process surface is formed.

On the premise that a carbon layer with the same thickness as that formed by a spin coating method is formed, a carbon layer formed by other methods such as CVD, ALD, sputtering and the like has a defect as shown in fig. 7, and a problem of a pit or a convex hull is generated due to a sparse and dense effect of the defect, so that the degree of planarization of the top surface of the finally formed carbon layer is insufficient; in the defect case shown in fig. 8, the top surface of the finally formed carbon layer is not sufficiently planarized due to the problem of filling voids due to insufficient filling of the bottom of the slits or premature sealing of the slits, or the problem of generating pits or convex hulls on the top surface due to conformal deposition. That is, the carbon layer formed on the substrate by other methods such as CVD, ALD, sputtering, etc. cannot meet the requirement of the EUV mask or EUV mask with higher performance on the planarization degree of the top surface of the substrate, and does not achieve the technical effect of the present invention.

In addition, the spun-on carbon layer 201 also has a positive CTE (e.g., 2 ppm/deg.C) similar to that of the substrate 200 a; the organic polymer material layer 200b has a negative CTE (e.g., -1 ppm/c to-3 ppm/c), and the composite layer formed by the spun-on carbon layer 201 and the organic polymer material layer 200b can achieve mutual compensation of CTEs in an operating temperature range of about 100c to 200c (close to but below the bake temperature for crack 200c formation) such that the top surface of the EUV grade substrate has a CTE close to 0.

Moreover, because the unfilled cracks 200c still exist in the organic polymer material layer 200b with the negative thermal expansion coefficient after the spin-coated carbon layer 201 is formed, the unfilled cracks 200c can serve as structural strain points, so that the organic polymer material layer 200b can serve as a stress transition buffer layer in subsequent processes (such as deposition and etching of a reflective film stack layer and an absorption layer) to avoid generation of stress-induced defects, and good process conditions are provided for the subsequent processes, thereby reducing defects of a finally prepared EUV mask base plate or EUV reticle, remarkably improving the reflectivity of the reflective film stack layer (i.e. EUV bragg reflector) of the EUV reticle, eliminating hard defects and phase defects, and improving the resolution and contrast of the reflective EUV reticle.

Referring to fig. 6, the present embodiment further provides an EUV grade substrate for an EUV mask blank or an EUV reticle, which may be formed by the method for manufacturing an EUV grade substrate of the present embodiment, and includes a base 200a, an organic polymer material layer 200b having a negative thermal expansion coefficient and having a crack 200c, and a removable spin-on carbon layer 201 stacked in sequence.

The substrate 200a is a quartz substrate having a coefficient of thermal expansion of 1 ppm/DEG C or less. The organic polymer material layer 200b has a coefficient of thermal expansion of-10 ppm/DEG C to 0 ppm/DEG C, and the elastic modulus of the organic polymer material layer 200b is smaller than that of the substrate. As an example, the ratio of the elastic modulus of the organic polymer material layer 200b to the substrate 200a is 0.1 to 0.9. The organic polymer material layer 200b includes a polyimide material containing an amide structure.

The spun-on carbon layer 201 has a thickness of less than or equal to 20nm, such as 10nm. The spun-on carbon layer 201 is capable of burying surface defects (including cracks) of the organic polymer material layer 200b having a negative thermal expansion coefficient therein and providing a flat process surface. After the spin-on carbon layer 201 and the organic polymer material layer 200b are stacked, the thermal expansion coefficients of the spin-on carbon layer 201 and the organic polymer material layer 200b compensate each other such that the thermal expansion coefficient of the EUV-grade substrate surface is less than or equal to 0.1ppm/° c (e.g., less than or equal to 0.01ppm/° c).

Optionally, the thickness of the organic polymer material layer 200b is from 20nm to 100nm.

Optionally, the width of the crack 200c is 2nm to 50nm, and the depth of the crack 200c is 2nm to 50nm.

In addition, the spun-on carbon layer 201 can serve as a removable sacrificial layer that can be removed by an oxygen plasma ashing process when rework, recycling, and reuse of the EUV grade substrate are required.

Referring to fig. 9, the present embodiment further provides a method for manufacturing an EUV mask blank, which includes:

first, using the method of manufacturing an EUV level substrate according to the present invention, an EUV level substrate is formed, which includes a base 200a, an organic polymer material layer 200b having a crack 200c, and a spin-on carbon layer 201.

Then, a reflective film stack layer 202 is formed on the spun-on carbon layer 201 of the EUV-stage substrate. Referring to fig. 9, the reflective film stack 202 is generally required to have a high reflectivity to a specific wavelength of exposure light, for example, a reflectivity of more than 60%, preferably more than 65%, to 13.6nm euv light. In this embodiment, the reflective film stack layer 202 is mainly formed by alternately laminating a pair of first reflective films (not shown) and a pair of second reflective films (not shown), and is laminated in 40 to 50 pairs. The film thickness of the first reflecting film and the film thickness of the second reflecting film are respectively about 3nm to 4nm. The film thickness of the first reflective film and the second reflective film is any suitable material that achieves a high reflectance (e.g., greater than 70%) for extreme ultraviolet light of a specific wavelength (e.g., 13.6 nm). For example, the material of the first reflective film is silicon (Si), and the material of the second reflective film is molybdenum (Mo). For another example, the first reflective film is made of Mo, and the second reflective film is made of beryllium (Be). Specifically, the first reflective film and the second reflective film may be alternately formed by any suitable Deposition process such as sputtering (PVD), chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), plasma Enhanced ALD (PEALD), IBD (Ion Beam Deposition), JVD (Jet Vapor Deposition), and the like, thereby forming the desired reflective film stack Layer 202. In order to minimize thermal stress induced defects during the formation of the reflective film stack 202, the deposition temperature of each film layer in the reflective film stack 202 is as close to room temperature as possible, for example, between room temperature and 100 ℃.

Next, a cover layer 203 is formed on the surface of the reflective film stack layer 202. Specifically, the capping layer 203 is formed on the top surface of the reflective film stack layer 202 by any suitable deposition process such as sputtering (PVD), CVD, PECVD, ALD, PEALD, IBD, JVD, and the like. The capping layer 203 serves to prevent the reflective film stack layer 202 from being damaged by the etching process. The material may include ruthenium (Ru), ruthenium alloys (e.g., ruB, ruSi, or RuNb), or ruthenium oxides (e.g., ruO) ₂ Or RuNbO), which may have a single-layer film structure or a structure in which a plurality of films are laminated, and the thickness of the cover layer 203 is, for example, 2nm to 4nm. In other embodiments of the present invention, when the top film of the reflective film stack 202 is made of silicon, the fabrication of the cap layer 203 may be omitted, or a silicon film (i.e., the first reflective film on the top layer) is deposited as the cap layer 203 during the formation of the reflective film stack 202.

Thereafter, an absorber layer 204 may be formed on the top surface of the cap layer 203 by any suitable deposition process, such as sputtering (PVD), CVD, PECVD, ALD, PEALD, IBD, JVD, and the like. The absorption layer 204 may be a single-layer film structure or a composite structure formed by stacking multiple layers of films, and the material thereof includes at least one of cobalt (Co), tellurium (Te), hafnium (Hf), nickel (Ni), tantalum (Ta), chromium (Cr), a tantalum-based material, and a chromium-based material. The total thickness of the absorption layer 204 is, for example, 50nm to 75nm, and when the absorption layer 204 is a composite structure formed by stacking multiple layers of films, the thickness of a single-layer film therein is, for example, 3nm to 6nm. In order to minimize thermal stress induced defects during the formation of the reflective film stack 202, the deposition temperature of each film layer in the absorber layer 204 is as close to room temperature as possible, for example, between room temperature and 100 ℃.

With continued reference to fig. 9, a backside conductive layer 206 may optionally be deposited on the surface of the EUV-grade substrate facing away from the absorber layer 204 by any suitable deposition process such as sputtering, evaporation, CVD, PECVD, ALD, PEALD, molecular beam epitaxy, IBD, JVD, etc. The material of the back conductive layer 206 may include at least one conductive material of chromium, chromium-based materials (e.g., chromium nitride CrN or chromium oxynitride CrON), tantalum, or tantalum-based materials (e.g., tantalum boride TaB, tantalum oxide TaO, tantalum nitride TaN, tantalum boride TaBO, or tantalum nitride TaBN, etc.). The thickness of the back conductive layer 206 is, for example, 60nm to 75nm.

Thus, the production of the EUV mask blank is completed.

It should be understood that, in the embodiment, the back conductive layer 206 is formed after the deposition of the absorption layer 204, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the deposition of the back conductive layer 206 may be performed before the deposition of the reflective film stack layer 202, after the deposition of the reflective film stack layer 202 and before the deposition of the cover layer 203, or after the deposition of the cover layer 203 and before the deposition of the absorption layer 204.

The method for manufacturing the EUV mask blank according to the embodiment is based on the EUV-grade substrate of the present invention, and therefore, has the advantages of low thermal expansion and few defects, and is beneficial to improving the EUV lithography effect.

Referring to fig. 9, the present embodiment further provides an EUV mask blank, which is preferably manufactured by the method for manufacturing an EUV mask blank of the present embodiment. The EUV mask blank comprises an EUV substrate (i.e. comprising a substrate 200a, an organic polymer material layer 200b with cracks 200c, and a spin-on carbon layer 201) according to the present invention, a reflective film stack 202, and an absorber layer 204, which are stacked in sequence.

Alternatively, the reflective film stack layer 202 includes first and second reflective films stacked in alternating pairs, and the number of stacked first and second reflective films is 30 to 60 pairs.

Optionally, the EUV mask blank further comprises a capping layer 203 and a backside conductive layer 206. The capping layer 203 is formed between the top reflective film of the reflective film stack layer 202 and the absorber layer 204, and the backside conductive layer 206 is formed on the surface of the organic polymer substrate 200 facing away from the spun-on carbon layer 201.

In addition, the materials of the EUV-grade substrate, the reflective film stack layer 202, the absorber layer 204, the cap layer 203 and the backside conductive layer 206 may be selected as described in the above method for manufacturing the EUV mask blank of the present invention, and are not described herein again.

Based on the same inventive concept, referring to fig. 10, the present embodiment further provides a method for manufacturing an EUV mask, which includes:

s21, forming the EUV mask base plate by adopting the manufacturing method of the EUV mask base plate;

s22, etching an absorption layer of the EUV mask base plate to form a first pattern in the absorption layer;

s23, etching the absorbing layer and the reflecting film stack layer of the EUV mask base plate on the periphery of the first pattern, and stopping etching on the surface of the spin-coated carbon layer of the EUV mask base plate to form a second pattern.

The process of step S21 is the method for manufacturing the EUV mask blank of the present invention, and is not described herein again.

In step S22, referring to fig. 11, a hard mask layer 205 is formed on the top surface of the absorption layer 204 by any suitable deposition process, such as sputtering, CVD, PECVD, ALD, PEALD, IBD, JVD, etc. The hard mask layer 205 may be made of tantalum (Ta), a tantalum-based material (e.g., tantalum boride TaB, tantalum oxide TaO, tantalum nitride TaN, tantalum oxyboride TaB or tantalum oxynitride TaBN), silicon, a silicon-based material (e.g., silicon nitride SiN or silicon oxynitride SiON), ruthenium, or a ruthenium-based material (e.g., ruthenium boride RuB), and the hard mask layer 205 may have a thickness of, for example, 4nm to 20nm.

The deposition of the hard mask layer 205 may be performed after the deposition of the absorption layer 204 and before the deposition of the back conductive layer 206, or may be performed after the deposition of the absorption layer 204 and after the deposition of the back conductive layer 206.

In step S22, with continued reference to fig. 11, after depositing the hard mask layer 205, the following process is performed:

first, a first photoresist layer 207 is coated, and the first photoresist layer 207 is exposed and developed to pattern the first photoresist layer 207.

Then, using the patterned first photoresist layer 207 as a mask, the hard mask layer 205 is etched to the top surface of the absorption layer 204 by any suitable process such as atomic layer etching, plasma etching, etc. so as to transfer the pattern of the first photoresist layer 207 into the hard mask layer 205, thereby forming a patterned hard mask layer 205'.

Thereafter, the first photoresist layer 207 is removed by dry stripping such as plasma ashing (dry etching) or a suitable wet stripping process. For example, oxygen (O) is first used ₂ ) Dry ashing (dry ashing) the first photoresist layer 207 with various organic acids and inorganic sulfuric acid, H, at high temperature ₂ O ₂ Wet stripping (wet striping) the first photoresist layer 207 followed by an isopropyl alcohol (IPA) rinse and CO rinse ₂ The first photoresist layer 207 is removed by rinsing.

Next, the patterned hard mask layer 205' is used as a mask to etch the absorption layer 204 to the top surface of the cap layer 203 or the top surface of the reflective film stack 202 by an appropriate etching process such as atomic layer etching, so as to form a first pattern 204a in the absorption layer 204, wherein the first pattern 204a is a pattern of a circuit and/or a device required for manufacturing an integrated circuit.

Referring to fig. 11, in step S23, first, a second photoresist layer 208 is coated on the patterned hard mask layer 205' and the EUV mask blank, and the second photoresist layer 208 is exposed and developed to pattern the second photoresist layer 208, where the patterned second photoresist layer 208 can protect a formation region of the first pattern 204a of the EUV mask blank and expose a region of the EUV mask blank where the second pattern is to be formed, the region being located at the periphery of the first pattern 204 a.

Then, the hard mask layer 205', the absorber layer 204, the capping layer 203, and the reflective film stack layer 202 are etched by a suitable etching process such as atomic layer etching using the patterned second photoresist layer 208 as a mask, and the etching is stopped on the surface of the spun-on carbon layer 201 to form a second pattern 209, thereby obtaining the EUV reticle, wherein the second pattern 209 is a frame of the EUV reticle.

Then, the second photoresist layer 208 is removed by a dry photoresist removal process such as plasma ashing or a suitable wet photoresist removal process. And the hard mask layer 205' is further removed, thereby forming an EUV reticle having the first pattern 204a and the second pattern 209.

The method for manufacturing the EUV mask blank according to the embodiment is manufactured based on the EUV mask blank of the present invention, and therefore, the EUV mask blank with lower cost, fewer defects and higher performance can be manufactured.

Referring to fig. 11, the present embodiment further provides an EUV reticle, which is formed by using the method for manufacturing an EUV reticle of the present embodiment, and has not only the EUV mask substrate of the present embodiment but also a desired pattern. Specifically, as shown in the last drawing in fig. 11, the EUV reticle has a first pattern 204a and a second pattern 209, the first pattern 204a penetrates through the absorber layer 204 and is located above the top reflective film of the reflective film stack 202 of the EUV mask blank, and the second pattern 209 penetrates through the absorber layer 204 and the reflective film stack 202 of the EUV mask blank and exposes the top surface of the spun-on carbon layer 201 of the EUV mask blank. The first pattern 204a is a desired circuit pattern, and the second pattern 209 is a frame pattern required for the periphery of the circuit.

Furthermore, it is noted that, in the manufacturing process of the EUV mask blank and the EUV mask blank of the present invention, and in the process of performing EUV lithography using the EUV mask blank, if the corresponding operation is performed at a suitable ambient temperature (e.g., 100 ℃ to 200 ℃), the organic polymer material layer 200b may be used as a stress transition buffer layer due to the presence of the unfilled cracks 200c during the operation, thereby preventing the occurrence of unwanted deformation and defects and ensuring the effect of the corresponding operation.

Moreover, due to the existence of the spin-coated carbon layer 201The spun-on carbon layer 201 may be considered a regenerated "sacrificial layer" that is further passed through O ₂ And removing the plasma by ashing, and realizing the recovery and the reutilization of the substrate.

Referring to the body 12, taking recycling the substrate of the EUV reticle of the present invention as an example, the substrate recycling method of the present embodiment specifically includes: firstly, sequentially removing an absorption layer 204, a covering layer 203 and a reflective film stack layer 202 of the EUV mask by adopting any process such as wet etching, plasma etching, chemical mechanical polishing and the like to expose a spin-coated carbon layer 201 of the EUV mask; then, the spin-on carbon layer 201 is removed by plasma ashing to expose the surface of the organic polymer material layer 200b of the EUV reticle. Thereby recovering the substrate of the EUV reticle, which may be used to make a new EUV reticle or other device.

Optionally, in this embodiment, the backside conductive layer 206 on the surface of the substrate 200a facing away from the spun-on carbon layer 201 is also removed before the absorption layer 204 is removed, or after the reflective film stack layer 202 is removed and before the spun-on carbon layer 201 is removed, or after the spun-on carbon layer 201 is removed.

Further alternatively, a carbon material with a positive thermal expansion coefficient may be spin-coated again on the exposed surface of the organic polymer material 200b by the method of the above step S13 to form a new spin-coated carbon layer to repair the surface defects of the organic polymer material, thereby obtaining again the EUV grade substrate for EUV mask blank and EUV reticle of the present invention.

Obviously, in the present invention, the spin-coated carbon layer 201 is used as a sacrificial layer, has a thin thickness, can be easily removed by plasma ashing, does not cause a problem of lowering of surface smoothness, thermal expansion coefficient, and the like of the organic polymer material layer 200b due to damage to the surface of the organic polymer material layer 200b, can be used for recovery and reuse of a substrate in an EUV mask blank and an EUV reticle, has a low recovery cost, and can further reduce the manufacturing cost of a new EUV mask blank and an EUV reticle because a new EUV mask blank and an EUV reticle can be further manufactured by using a substrate recovered from an old EUV mask blank and an EUV reticle.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims

1. A method of manufacturing an EUV-grade substrate, comprising:

and spin-coating a carbon material with a positive thermal expansion coefficient on the surface of the organic polymer material layer to form a spin-coated carbon layer which fills the corresponding cracks and has a flat surface so as to form the EUV grade substrate, wherein the thermal expansion coefficients of the spin-coated carbon layer and the organic polymer material layer are mutually compensated, so that the thermal expansion coefficient of the surface of the EUV grade substrate is less than or equal to 0.1 ppm/DEG C.

2. The method of manufacturing an EUV-grade substrate according to claim 1, wherein the ratio of the elastic modulus of the organic polymer material layer to the base is 0.1 to 0.9.

3. The method of manufacturing an EUV-grade substrate according to claim 1, wherein the organic polymer material layer comprises a polyimide material containing an amide structure.

4. The method of manufacturing an EUV-grade substrate according to claim 1, wherein forming a layer of an organic polymer material having a negative thermal expansion coefficient on the substrate comprises: spin coating or depositing an organic polymeric material on the surface of the substrate to a desired thickness; curing the organic polymer material to form the layer of organic polymer material.

5. The method of manufacturing an EUV-grade substrate according to claim 4, wherein curing the organic polymer material comprises: and baking and curing the organic polymer material for multiple times at different temperatures in a vacuum or nitrogen or inert gas atmosphere in a temperature decreasing manner to form the organic polymer material layer.

6. The method of manufacturing an EUV-grade substrate according to claim 1, wherein the step of subjecting the layer of organic polymer material to a crack-inducing treatment comprises: and baking the organic polymer material layer for multiple times to form corresponding cracks inside the organic polymer material layer.

7. The method for manufacturing an EUV-grade substrate according to claim 6, wherein the temperature of each baking in the crack-inducing treatment ranges from 100 ℃ to 250 ℃, and the baking time ranges from 1 hour to 3 hours.

8. The method of manufacturing an EUV grade substrate according to any of claims 1~7 wherein the layer of organic polymer material has a thickness of from 20nm to 100nm; and/or the size of the crack is 2 nm-50 nm.

9. A method of manufacturing an EUV mask blank, comprising:

forming an EUV grade substrate using the method of manufacturing an EUV grade substrate of any of claims 1~8;

and sequentially forming a reflecting film stack layer and an absorbing layer on the spin-coated carbon layer of the EUV substrate so as to form an EUV mask base plate.

10. The method of manufacturing an EUV mask blank according to claim 9,

after forming the reflective film stack layer on the spin-on carbon layer and before forming the absorber layer, further comprising: forming a cover layer on the reflective film stack layer; and the number of the first and second groups,

after forming the absorption layer, further comprising: and forming a back conductive layer on the surface of the substrate, which faces away from the spin-coated carbon layer.

11. A method of manufacturing an EUV reticle, comprising:

forming an EUV mask blank using the method for manufacturing an EUV mask blank according to claim 9 or 10;

etching an absorber layer of the EUV mask blank to form a first pattern in the absorber layer;

12. An EUV class substrate comprising:

a layer of organic polymeric material having a negative coefficient of thermal expansion formed on the substrate, and having a coefficient of thermal expansion of-10 ppm/DEG C to 0 ppm/DEG C, the layer of organic polymeric material having a modulus of elasticity less than that of the substrate, the layer of organic polymeric material having a corresponding crack formed therein;

13. An EUV grade substrate according to claim 12, wherein the ratio of the elastic modulus of the layer of organic polymer material to the base is 0.1-0.9.

14. An EUV-grade substrate according to claim 12, wherein the material of the layer of organic polymer material comprises a polyimide material containing amide structures.

15. The EUV-grade substrate according to claim 12, wherein the layer of organic polymer material has a thickness of from 20nm to 100nm; and/or the size of the crack is 2 nm-50 nm.

16. An EUV mask blank, comprising:

an EUV-grade substrate as claimed in any one of claims 12 to 15;

and the absorption layer is formed on the reflection film stack layer.

17. The EUV mask blank of claim 16, further comprising:

18. An EUV reticle having an EUV mask blank according to any of claims 16 or 17, and further having a first pattern formed in an absorber layer of the EUV mask blank and a second pattern that penetrates the absorber layer and a reflective film stack layer of the EUV mask blank and exposes a surface of a spun-on carbon layer of the EUV mask blank.