CN115133889A - BD type pulse width modulation circuit for D type amplifier and modulation method thereof - Google Patents

Abstract

A BD type pulse width modulation circuit for a class D amplifier and a modulation method therein. The BD type Pulse Width Modulation (PWM) circuit for class D amplifier is used for converting a pair of input signals which are complementary to each other into a corresponding pair of output PWM signals, and the BD type PWM circuit modulates a basic modulation signal with the pair of input signals to generate the basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common mode level. The BD type pulse width modulation circuit modulates an offset modulation signal with the pair of input signals to generate an offset PWM signal, wherein the offset modulation signal and the basic modulation signal have an offset which is not 0. The BD type PWM circuit selects an offset PWM signal or a heavy duty PWM signal as the output PWM signal at the level of the pair of input signals, the heavy duty PWM signal being related to the basic PWM signal.

Description

BD type pulse width modulation circuit for D type amplifier and modulation method thereof

Technical Field

The present invention relates to a BD type pwm circuit for class D amplifier, and more particularly, to a BD type pwm circuit having a common mode transition function to reduce power consumption. The invention also relates to a modulation method for a class D amplifier.

Background

Fig. 1 shows a waveform diagram of an operation of a typical class D amplifier using BD type modulation, in which a pair of complementary input signals Vep and Ven modulate a basic modulation signal (triangle wave VTRI) to generate basic pwm signals PS1p and PS1n, so as to drive a load, PS1D is a differential mode signal of pwm signals PS1p and PS1n, and PS1c is a common mode signal of pwm signals PS1p and PS1n, the BD type modulation has an advantage of reducing the requirement of an output filter, however, in a light load condition, the duty ratio of the common mode signal PSOc is as high as 50%, so that ripple current and idle (idle) current are maximized, thereby causing additional power consumption and reducing conversion efficiency.

Fig. 2 shows another operating waveform diagram of a prior art class D amplifier using BD type modulation, which employs an asymmetric driving scheme, and the adjusted output PWM signals (PSOp and PSOn) are asymmetric to each other, thereby reducing the ripple current of the common mode signal PSOc, however, this prior art technique is liable to cause the duty ratio of the differential mode signal PSOd to be distorted, and further cause the distortion of the output signal.

Fig. 3 is a schematic diagram showing the operation waveforms of another prior art class D amplifier using BD type modulation, in which the paired input signals Vep and Ven are subjected to non-linear level adjustment according to their levels, thereby reducing the duty ratio of the common mode signal PSOc under light load, but the prior art is easily distorted due to the non-linear adjustment.

In view of the above, the present invention provides a BD type modulated class-D amplifier with common mode voltage adaptability transition, which can effectively reduce ripple current and idle current and maintain low output signal distortion.

Disclosure of Invention

In one aspect, the present invention provides a BD type PWM circuit for a class D amplifier for converting a pair of input signals complementary to each other into a corresponding pair of output PWM signals, the BD type PWM circuit comprising: a duty ratio adjusting circuit, for generating a plurality of relay PWM signals, wherein the plurality of relay PWM signals include a basic PWM signal, an offset PWM signal and a heavy duty PWM signal, each of the plurality of relay PWM signals has an in-phase sub-signal, an anti-phase sub-signal and a differential mode signal, wherein the differential mode signal is a difference between the in-phase sub-signal and the anti-phase sub-signal, the duty ratio adjusting circuit comprises: a basic comparison circuit for generating the basic PWM signal by modulating a basic modulation signal by the pair of input signals, wherein the pair of input signals and the basic modulation signal have the same common mode level; and an offset comparator circuit for generating the offset PWM signal by modulating an offset modulation signal with the pair of input signals, wherein the offset modulation signal and the basic modulation signal have an offset amount different from 0; a load detection circuit for determining whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal, wherein a light load signal is enabled when the level of the pair of input signals is lower than the light load threshold; and an output selection circuit for selecting the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, and selecting the heavy-load PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, so that the rms power of the pair of output PWM signals is less than the rms power of the basic PWM signal when the level of the pair of input signals is lower than the light-load threshold; wherein the override PWM signal is related to the base PWM signal.

In one embodiment, the load detection circuit periodically determines whether the in-phase sub-signal and the inverted sub-signal corresponding to the offset PWM signal have a pulse in a previous operation cycle to enable a light load signal according to an operation cycle, so as to indicate that the level of the pair of input signals is lower than the light load threshold.

In one embodiment, the heavy duty PWM signal corresponds to the basic PWM signal; or the plurality of relay PWM signals also comprise a single-side PWM signal, and the heavy-load PWM signal is corresponding to the single-side PWM signal; the duty ratio adjusting circuit further includes a single-side selection circuit for generating the in-phase sub-signal corresponding to the single-side PWM signal according to a positive value portion of the differential-mode signal corresponding to the basic PWM signal, and generating the inverted sub-signal corresponding to the single-side PWM signal according to a negative value portion of the differential-mode signal corresponding to the basic PWM signal.

In one embodiment, the override PWM signal is optionally the single-sided PWM signal or the basic PWM signal.

In one embodiment, the pair of output PWM signals is used to control a driving stage circuit to drive two terminals of a load in a PWM manner, and the override PWM signal is determined and selected to be the single-side PWM signal or the basic PWM signal according to a power source of the driving stage circuit, a level of the load, a temperature associated with the class D amplifier circuit, or the operating frequency, wherein the operating frequency corresponds to the operating period.

In one embodiment, the offset is related to the light load threshold.

In one embodiment, the basic modulation signal and the offset modulation signal are configured as a triangular wave or a sawtooth wave, respectively, wherein the basic modulation signal and the offset modulation signal are synchronized with the operation period.

In one embodiment, the absolute value of the offset is less than 1/2 for the peak-to-peak value of the basic modulation signal.

In one embodiment, the basic comparison circuit includes: a first comparator for comparing an in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and a second comparator for comparing the basic modulation signal with an inverted input signal of the pair of input signals to generate the inverted sub-signal of the basic PWM signal; the offset comparison circuit includes: a third comparator for comparing the in-phase input signal and the offset modulation signal of the pair of input signals to generate the in-phase sub-signal of the offset PWM signal; and a fourth comparator for comparing the offset modulation signal with the inverted input signal of the pair of input signals to generate the inverted sub-signal of the offset PWM signal.

In one embodiment, the load detection circuit includes: a first state circuit for triggering an in-phase pulse indication signal according to a pulse of the in-phase sub-signal of the offset PWM signal; a second state circuit for triggering an inverted pulse indication signal according to a pulse of the inverted sub-signal of the offset PWM signal; and a third state circuit for determining whether the in-phase pulse indication signal and the reverse-phase pulse indication signal are both enabled according to a frequency signal switched in the operation cycle to trigger enabling the light-load signal, thereby indicating that the level of the pair of input signals is lower than the light-load threshold.

In one embodiment, the single-side selection circuit includes: a first logic gate, for performing an and logic operation on an inverted sub-signal of the basic PWM signal and the in-phase sub-signal of the basic PWM signal to generate the in-phase sub-signal of the single-side PWM signal; and a second logic gate for performing an and logic operation on an inverted sub-signal of the in-phase sub-signal of the basic PWM signal and the inverted sub-signal of the basic PWM signal to generate the inverted sub-signal of the single-side PWM signal.

In another aspect, the present invention provides a BD type pulse width modulation method for a class D amplifier, for converting a pair of input signals complementary to each other into a corresponding pair of output PWM signals, the BD type pulse width modulation method comprising: s1: generating a plurality of relay PWM signals, wherein the plurality of relay PWM signals include a basic PWM signal, an offset PWM signal and a heavy duty PWM signal, each of the plurality of relay PWM signals has a corresponding in-phase sub-signal, an inverted sub-signal and a differential mode signal, wherein the differential mode signal is a difference between the in-phase sub-signal and the inverted sub-signal, and the step of generating the plurality of relay PWM signals includes: s11: modulating a basic modulation signal with the pair of input signals to generate the basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common mode level; and S12: modulating an offset modulation signal with the pair of input signals to generate the offset PWM signal, wherein the offset modulation signal and the basic modulation signal have an offset different from 0; s2: judging whether the level of the pair of input signals is lower than a light load threshold value according to the offset PWM signal; and S3: selecting the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, and selecting the heavy-load PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, so that the rms power of the pair of output PWM signals is less than the rms power of the basic PWM signal when the level of the pair of input signals is lower than the light-load threshold; wherein the override PWM signal is related to the base PWM signal.

In one embodiment, the step of determining whether the level of the pair of input signals is lower than a light load threshold comprises: periodically judging whether the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal have a pulse in the previous operation period according to an operation period to judge that the level of the pair of input signals is lower than the light load threshold.

In one embodiment, the heavy duty PWM signal corresponds to the basic PWM signal; or the plurality of relay PWM signals also comprise a single-side PWM signal, and the heavy-load PWM signal is corresponding to the single-side PWM signal; wherein the step of generating the plurality of relay PWM signals further comprises: the in-phase sub-signal corresponding to the single-side PWM signal is generated according to a positive value part of the differential mode signal corresponding to the basic PWM signal, and the reverse-phase sub-signal corresponding to the single-side PWM signal is generated according to a negative value part of the differential mode signal corresponding to the basic PWM signal.

In one embodiment, the pair of output PWM signals is used to control a driving stage circuit to drive two ends of a load in a PWM manner, and the heavy duty PWM signal is determined and selected to be the single-side PWM signal or the basic PWM signal according to a power source of the driving stage circuit, a level of the load, a temperature associated with the class-D amplifier circuit, or the operating frequency, wherein the operating frequency corresponds to the operating period.

In one embodiment, the step of generating the basic PWM signal includes: comparing an in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and comparing the basic modulation signal with an inverted input signal of the pair of input signals to generate the inverted sub-signal of the basic PWM signal; the step of generating the offset PWM signal includes: comparing the in-phase input signal and the offset modulation signal of the pair of input signals to generate the in-phase sub-signal of the offset PWM signal; and comparing the offset modulation signal with the inverted input signal of the pair of input signals to generate the inverted sub-signal of the offset PWM signal.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1 shows a waveform diagram of an operation of a typical class D amplifier using BD type modulation.

Fig. 2 shows a schematic diagram of the operating waveforms of another prior art class D amplifier using BD type modulation.

Fig. 3 shows a schematic diagram of the operating waveforms of another prior art class D amplifier using BD type modulation.

FIG. 4 is a signal waveform diagram of an embodiment of a class D amplifier according to the present invention.

Fig. 5 is a schematic circuit diagram of an embodiment of a BD type pwm circuit for a class D amplifier according to the present invention.

FIG. 6 is a schematic diagram of signal waveforms of an embodiment of a class D amplifier according to the present invention.

Fig. 7 is a schematic circuit diagram of another embodiment of a BD type pulse width modulation circuit for a class D amplifier according to the present invention.

Fig. 8 shows a schematic circuit diagram of another embodiment of the BD type pulse width modulation circuit for a class D amplifier according to the present invention.

Description of the symbols in the drawings

100: duty ratio adjusting circuit

1005: class D amplifier

110: basic comparison circuit

111, 112: comparator with a comparator circuit

120: offset comparison circuit

121, 122: comparator with a comparator circuit

20: driving circuit

200: load detection circuit

30: load(s)

305, 307, 308: output selection circuit

315, 317, 318, 325, 327, 328, 338, 348: multi-task device

50: BD type pulse width modulation circuit

CKs: frequency signal

Fs: frequency of operation

ILD: current level

PS1, PS1p, PS1 n: basic PWM signal

PS2, PS2p, PS2 n: offset PWM signal

PS3, PS3p, PS3 n: heavy duty PWM signal

PS1d, PS2d, PS4d, PSOd: differential mode signal

PS1c, PS2c, PS4c, PSOc: common mode signal

PS1p and PS1 n: basic PWM signal

PSO, PSOp, PSOn: outputting PWM signals

PVDD: power supply

SEL: selection signal

Sinp: inphase pulse indication signal

Sinv: inverted pulse indication signal

SLL: light load signal

Temp: temperature of

Ts, T1-T7: period of operation

Vcm1, Vcm 2: common mode level

Vep, Ven: input signal

Vos: offset amount

VTR 1: basic modulation signal

VTR 2: offset modulated signal

VTRI: basic modulation signal

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Referring to fig. 4 and 5, fig. 4 is a schematic diagram showing signal waveforms of a class D amplifier according to an embodiment of the present invention, and fig. 5 is a schematic diagram showing a circuit of a BD type pwm circuit for a class D amplifier according to an embodiment of the present invention.

As shown in fig. 4 and 5, the BD type PWM circuit 50 is used for the class D amplifier 1005, the BD type PWM circuit 50 is used for converting a pair of complementary input signals Vep and Ven into a corresponding pair of output Pulse Width Modulation (PWM) signals PSOp and PSOn, and controlling the driving circuit 20 to drive two ends of the load 30 (e.g., a speaker) in a pulse width modulation manner, and the BD type PWM circuit 50 includes a duty ratio adjusting circuit 100, a load detecting circuit 200, and an output selecting circuit 305.

The duty cycle adjusting circuit 100 is used to generate a plurality of intermediate (intermediate) PWM signals, which include a basic PWM signal PS1, an offset PWM signal PS2 and a heavy duty PWM signal PS3, wherein each intermediate PWM signal has a corresponding in-phase sub-signal, an inverted sub-signal, a differential mode signal and a common mode signal. The differential mode signal is the difference between the in-phase sub-signal and the anti-phase sub-signal, and the common mode signal is the average value of the in-phase sub-signal and the anti-phase sub-signal.

According to an embodiment of the present invention, as shown in fig. 5, the duty ratio adjusting circuit 100 includes a basic comparing circuit 110 and an offset comparing circuit 120.

The basic comparison circuit 110 is used for generating a basic PWM signal PS1 by modulating a basic modulation signal VTR1 with input signals Vep and Ven, which have the same common mode level Vcm1, specifically referred to as a common mode voltage, as shown in fig. 4 with the basic modulation signal VTR 1. The offset comparator circuit 120 is used for modulating the offset modulation signal VTR2 by the input signals Vep and Ven to generate the offset PWM signal PS2, wherein the offset modulation signal VTR2 and the basic modulation signal VTR1 have an offset Vos different from 0, i.e., the common mode level Vcm2 of the offset modulation signal VTR2 and the common mode level Vcm1 of the input signals Vep and Ven also have an offset Vos. In the embodiment of fig. 4, the offset Vos is greater than 0, i.e., the level of the offset modulation signal VTR2 is higher than the level of the basic modulation signal VTR1, however, this is not intended to limit the present invention, and the offset Vos may be less than 0 in other embodiments. In one embodiment, the absolute value of the offset Vos is less than 1/2 of the peak-to-peak value Vp-p of the base modulation signal VTR 1.

The load detection circuit 200 is used for periodically determining whether the in-phase sub-signal PS2p and the inverted sub-signal PS2n corresponding to the offset PWM signal PS2 have a pulse in the previous operation period Ts according to the operation period Ts of the clock signal CKs, so as to enable the light load signal SLL, which indicates that the levels of the input signals Vep and Ven are lower than a light load threshold, which is related to the offset Vos in one embodiment. In detail, as shown in fig. 4, the in-phase sub-signal PS2p and the anti-phase sub-signal PS2n corresponding to the offset PWM signal PS2 have a pulse in the operation periods T3 to T5, and therefore, the light load signal SLL is enabled in the operation periods T4 to T6.

It should be noted that the level of the input signals Vep, Ven is lower than a light load threshold, and particularly refers to the absolute value of the ac level of the input signals Vep, Ven. It should be noted that the light load may refer to a low level of the input signal, and may also refer to a low power of the input signal or the output signal.

The output selection circuit 305 is configured to select the offset PWM signal PS2 as the output PWM signals PSOp and PSOn when the light-load signal SLL is enabled (i.e., light-load), and select the heavy-load PWM signal PS3 as the output PWM signals PSOp and PSOn when the light-load signal SLL is disabled (i.e., heavy-load), so that the rms power of the output PWM signals is smaller than the rms power corresponding to the basic PWM signal PS1 when the levels of the input signals Vep and Ven are lower than the light-load threshold. The heavy duty PWM signal PS3 is related to the basic PWM signal PS1, and has various embodiments, which are described in detail below.

With continued reference to fig. 4 and 5, in an embodiment, the reload PWM signal PS3 corresponds to the basic PWM signal PS1, and when the light load signal SLL is disabled (indicating that the reload is performed, i.e., the levels of the input signals Vep, Ven are higher than the light load threshold), the output selection circuit 305 selects the basic PWM signal PS1 as the output PWM signal PSO (PSOp, PSOn).

In detail, in the present embodiment, the output selection circuit 305 includes multiplexers 315 and 325 for selecting the basic PWM signal PS1 during heavy load and selecting the offset PWM signal PS2 as the output PWM signal PSO during light load according to the light load signal SLL.

With reference to fig. 5, the basic comparison circuit 110 includes a first comparator 111 and a second comparator 112. The first comparator 111 compares the non-inverted input signal Vep with the basic modulation signal VTR1 to generate the non-inverted sub-signal PS1p of the basic PWM signal PS 1. The second comparator 112 is used for comparing the basic modulation signal VTR1 with the inverted input signal Ven to generate the inverted sub-signal PS1n of the basic PWM signal PS 1.

The offset comparing circuit 120 includes a third comparator 121 and a fourth comparator 122. The third comparator 121 compares the in-phase input signal Vep with the offset modulation signal VTR2 to generate the in-phase sub-signal PS2p of the offset PWM signal PS 2. The fourth comparator 122 compares the offset modulation signal VTR2 with the inverted input signal Ven to generate the inverted sub-signal PS2n of the offset PWM signal PS 2. In the above embodiment, the basic modulation signal VTR1 and the offset modulation signal VTR2 are compared with the input signal by their inverted signals.

The load detection circuit 200 includes a first state circuit (such as but not limited to a flip-flop) 210, a second flip-flop 220, and a third flip-flop 230. The first flip-flop 210 is used to trigger the in-phase pulse indication signal Sinp according to the pulse of the in-phase sub-signal PS2p of the offset PWM signal PS 2. The second flip-flop 220 is used for triggering the inverted pulse indication signal Sinv according to the pulse of the inverted sub-signal PS2n of the offset PWM signal PS 2. The third flip-flop 230 is used for determining whether the in-phase pulse indication signal Sinp and the inverted pulse indication signal Sinv are both enabled according to the clock signal CKs switched by the operation cycle Ts to trigger the enable light-load signal SLL, thereby indicating whether the levels of the input signals Vep and Ven are lower than the light-load threshold.

It should be noted that, the basic modulation signal VTR1 and the offset modulation signal VTR2 in the foregoing embodiment are configured as triangular waves, however, this is not intended to limit the invention, and in other embodiments, the basic modulation signal VTR1 and the offset modulation signal VTR2 may also be configured as sawtooth waves, for example. Further, as shown in fig. 4, the period of the triangular wave (or the sawtooth wave) is synchronized with the operation period Ts.

Referring to fig. 6 and 7, fig. 6 is a schematic diagram showing signal waveforms of an embodiment of a class D amplifier according to the present invention, and fig. 7 is a schematic diagram showing an embodiment of a BD type pwm circuit for a class D amplifier according to the present invention (BD type pwm circuit 70).

In this embodiment, the plurality of PWM signals further includes a single-side PWM signal PS4, the duty ratio adjusting circuit 100 further includes a single-side selection circuit 400, which is configured to generate an in-phase sub-signal PS4p corresponding to the single-side PWM signal PS4 according to a positive value portion of the differential mode signal PS1d corresponding to the basic PWM signal PS1, and generate an inverted sub-signal PS4n corresponding to the single-side PWM signal PS4 according to a negative value portion (in this embodiment, an absolute value) of the differential mode signal PS1d corresponding to the basic PWM signal PS 1.

As shown in fig. 6 and 7, in the present embodiment, the heavy duty PWM signal PS3 corresponds to the one-sided PWM signal PS4(PS4p, PS4n), and when the light duty signal SLL is disabled (indicating heavy duty, i.e., when the levels of the input signals Vep, Ven are higher than the light duty threshold), the output selection circuit 305 selects the one-sided PWM signal PS4(PS4p, PS4n) as the output PWM signal PSO (PSOp, PSOn).

In detail, the output selection circuit 307 includes multiplexers 317 and 327 for selecting the basic PWM signal PS4 during heavy load and selecting the offset PWM signal PS2 as the output PWM signal PSO during light load according to the light load signal SLL.

In one embodiment, the single-sided selection circuit 400 includes a first and gate 410 and a second and gate 420. The first and gate 410 is used for performing an and logic operation on the inverted sub-signal PS1n of the basic PWM signal PS1 and the in-phase sub-signal PS1p of the basic PWM signal PS1 to generate the in-phase sub-signal PS4p of the single-side PWM signal PS 4. The second and gate 420 is used for performing and logic operation on the inverted signal of the in-phase sub-signal PS1p of the basic PWM signal PS1 and the inverted sub-signal PS1n of the basic PWM signal PS1 to generate the inverted sub-signal PS4n of the single-side PWM signal PS 4.

Referring to fig. 4, fig. 6 and fig. 8, fig. 8 is a schematic circuit diagram of a BD type pwm circuit for class D amplifier according to another embodiment of the present invention. The BD type PWM circuit 80 is similar to the BD type PWM circuits 50 and 70, and the difference is that the output selection circuit 308 of the BD type PWM circuit 80 can select the single-side PWM signal PS4 or the basic PWM signal PS1 as the reload PWM signal PS3 according to the selection signal SEL, specifically, the output selection circuit 308 includes multiplexers 318, 328, 338 and 348, the multiplexers 318 and 328 are used for selecting the PWM reload signal PS3 or the offset PWM signal PS2 as the output PWM signal PSO according to the light load signal SLL, and the multiplexers 338 and 348 are used for selecting the single-side PWM signal PS4 or the basic PWM signal PS1 as the reload PWM signal PS3 according to the selection signal SEL.

In one embodiment, the output selection circuit 308 may further include a selection control circuit for determining the selection signal SEL according to the power supply PVDD of the driving circuit 20, the current or power level (ILD) of the load 30, a temperature Temp associated with the class D amplifier circuit, or an operating frequency Fs (e.g., by receiving the clock signal CKs), wherein the operating frequency Fs is 1/Ts.

In summary, the BD type PWM circuit (e.g., 50, 60, 70) of the present invention can adaptively transition (hopping) to switch or select the PWM signal (the heavy duty PWM signal or the offset PWM signal PS2) modulated by the modulation signals (e.g., VTR1, VTR2) having different common mode voltages according to the level of the input signal, so as to keep the duty ratio of the common mode signal PSOc of the output PWM signal PSO away from 50% during light load, thereby effectively reducing ripple current and idle current and maintaining low output signal distortion.

As can be seen from fig. 4 and 6, according to the present invention, the average voltage of the differential mode signal PSOd of the output PWM signal PSO and the switching frequency can be maintained constant.

In the foregoing embodiments, the offset Vos is greater than 0 (see fig. 4 and fig. 6), the common mode voltage can rapidly transition and shift, and the duty ratio of the common mode signal PSOc at light load can be lower than 50%. On the other hand, in other embodiments, when the offset Vos is smaller than 0 for modulation, the common mode voltage transition is performed according to the aforementioned principle, so that the duty ratio of the common mode signal PSOc at light load is higher than 50%. In light load, no matter the duty ratio of the common mode signal PSOc is higher or lower than 50%, the ripple current and the idle current can be reduced as long as the duty ratio is far from 50%.

In addition, according to the present invention, the number of offset PWM signals is not limited, and in other embodiments, a plurality of offset PWM signals may be configured to further reduce distortion.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of facilitating the understanding of the present invention by those skilled in the art, and is not intended to limit the broadest scope of the present invention. The embodiments described are not limited to single use, but may be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not all of which are intended to be within the scope of this invention, will occur to those skilled in the art and are intended to be within the scope of this invention. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims (20)

1. A BD type pulse width modulation circuit for a class D amplifier for converting a pair of input signals complementary to each other into a corresponding pair of output PWM signals, the BD type pulse width modulation circuit comprising:

a duty ratio adjusting circuit, for generating a plurality of relay PWM signals, wherein the plurality of relay PWM signals include a basic PWM signal, an offset PWM signal and a heavy duty PWM signal, each of the plurality of relay PWM signals has an in-phase sub-signal, an anti-phase sub-signal and a differential mode signal, wherein the differential mode signal is a difference between the in-phase sub-signal and the anti-phase sub-signal, the duty ratio adjusting circuit comprises:

a basic comparison circuit for generating the basic PWM signal by modulating a basic modulation signal by the pair of input signals, wherein the pair of input signals and the basic modulation signal have the same common mode level; and

an offset comparator circuit for generating the offset PWM signal by modulating an offset modulation signal by the pair of input signals, wherein the offset modulation signal and the basic modulation signal have an offset amount different from 0;

a load detection circuit for determining whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal, wherein a light load signal is enabled when the level of the pair of input signals is lower than the light load threshold; and

an output selection circuit for selecting the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, and selecting the heavy-load PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, so that the rms power of the pair of output PWM signals is less than the rms power of the basic PWM signal when the level of the pair of input signals is lower than the light-load threshold;

wherein the heavy duty PWM signal is related to the basic PWM signal.

2. The BD type PWM circuit of claim 1 wherein the load detection circuit periodically determines whether the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal have a pulse in a previous operating period according to an operating period to enable a light-load signal indicating that the level of the pair of input signals is below the light-load threshold.

3. The BD type pulse width modulation circuit according to claim 1, wherein,

the heavy load PWM signal corresponds to the basic PWM signal; or

The plurality of relay PWM signals also comprise a single-side PWM signal, and the heavy-load PWM signal is corresponding to the single-side PWM signal;

the duty ratio adjusting circuit further includes a single-side selection circuit for generating the in-phase sub-signal corresponding to the single-side PWM signal according to a positive value portion of the differential-mode signal corresponding to the basic PWM signal, and generating the inverted sub-signal corresponding to the single-side PWM signal according to a negative value portion of the differential-mode signal corresponding to the basic PWM signal.

4. The BD type PWM circuit of claim 3, wherein the heavy duty PWM signal is optionally the single-side PWM signal or the basic PWM signal.

5. The BD type PWM circuit of claim 4, wherein the pair of output PWM signals are used to control a driver stage circuit to drive two terminals of a load in a PWM manner, the heavy duty PWM signal is selectively configured as the single-sided PWM signal or the basic PWM signal according to a power supply of the driver stage circuit, a level of the load, a temperature associated with the class-D amplifier circuit, or the operating frequency, wherein the operating frequency corresponds to the operating period.

6. The BD type pulse width modulation circuit of claim 1, wherein the offset is related to the light load threshold.

7. The BD type pwm circuit of claim 1, wherein the basic modulation signal and the offset modulation signal are each configured as a triangle wave or a sawtooth wave, and wherein the basic modulation signal and the offset modulation signal are synchronized with the operation period.

8. The BD type pulse width modulation circuit of claim 7, wherein the absolute value of the offset is less than 1/2 of the peak-to-peak value of the basic modulation signal.

9. The BD type pulse width modulation circuit according to claim 1, wherein,

the basic comparison circuit includes:

a first comparator for comparing an in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and

a second comparator for comparing the basic modulation signal with an inverted input signal of the pair of input signals to generate the inverted sub-signal of the basic PWM signal;

the offset comparison circuit includes:

a third comparator for comparing the in-phase input signal and the offset modulation signal of the pair of input signals to generate the in-phase sub-signal of the offset PWM signal; and

a fourth comparator for comparing the offset modulation signal with the inverted input signal of the pair of input signals to generate the inverted sub-signal of the offset PWM signal.

10. The BD type pulse width modulation circuit of claim 2, wherein the load detection circuit comprises:

a first state circuit for triggering an in-phase pulse indication signal according to a pulse of the in-phase sub-signal of the offset PWM signal;

a second state circuit for triggering an inverted pulse indication signal according to a pulse of the inverted sub-signal of the offset PWM signal; and

the third state circuit is used for judging whether the in-phase pulse indication signal and the reverse phase pulse indication signal are enabled or not according to a frequency signal switched by the operation period so as to trigger and enable the light load signal, thereby indicating that the level of the pair of input signals is lower than the light load threshold value.

11. The BD type pulse width modulation circuit of claim 3, wherein the one-side selection circuit comprises:

a first logic gate, for performing an and logic operation on an inverted sub-signal of the basic PWM signal and the in-phase sub-signal of the basic PWM signal to generate the in-phase sub-signal of the single-side PWM signal; and

and the second logic gate is used for performing AND logic operation on the inverted signal of the in-phase sub-signal of the basic PWM signal and the inverted sub-signal of the basic PWM signal to generate the inverted sub-signal of the single-side PWM signal.

12. A BD type pulse width modulation method for a class D amplifier for converting a pair of input signals complementary to each other into a corresponding pair of output PWM signals, the BD type pulse width modulation method comprising:

s1: generating a plurality of relay PWM signals, wherein the plurality of relay PWM signals include a basic PWM signal, an offset PWM signal and a heavy duty PWM signal, each relay PWM signal has a corresponding in-phase sub-signal, an inverted sub-signal and a differential mode signal, wherein the differential mode signal is a difference between the in-phase sub-signal and the inverted sub-signal, and the generating the plurality of relay PWM signals includes:

s11: modulating a basic modulation signal with the pair of input signals to generate the basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common mode level; and

s12: modulating an offset modulation signal with the pair of input signals to generate the offset PWM signal, wherein the offset modulation signal and the basic modulation signal have an offset different from 0;

s2: judging whether the level of the pair of input signals is lower than a light load threshold value according to the offset PWM signal; and

s3: selecting the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, and selecting the heavy-load PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light-load threshold, so that the rms power of the pair of output PWM signals is less than the rms power of the basic PWM signal when the level of the pair of input signals is lower than the light-load threshold;

wherein the heavy duty PWM signal is related to the basic PWM signal.

13. The BD type pwm method of claim 12, wherein the step of determining whether the level of the pair of input signals is lower than a light-load threshold comprises: periodically judging whether the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal have a pulse in the previous operation period according to an operation period to judge that the level of the pair of input signals is lower than the light load threshold.

14. The BD type pulse width modulation method according to claim 12, wherein,

the heavy load PWM signal corresponds to the basic PWM signal; or

The plurality of relay PWM signals also comprise a single-side PWM signal, and the heavy-load PWM signal is corresponding to the single-side PWM signal;

wherein the step of generating the plurality of relay PWM signals further comprises: the in-phase sub-signal corresponding to the single-side PWM signal is generated according to a positive value part of the differential mode signal corresponding to the basic PWM signal, and the reverse-phase sub-signal corresponding to the single-side PWM signal is generated according to a negative value part of the differential mode signal corresponding to the basic PWM signal.

15. The BD type pulse width modulation method of claim 14, wherein the heavy duty PWM signal is optionally the single-sided PWM signal or the basic PWM signal.

16. The BD type PWM method of claim 15, wherein the pair of output PWM signals are used to control a driver stage circuit to drive two terminals of a load in a PWM manner, the heavy duty PWM signal is determined and selected to be the single-side PWM signal or the basic PWM signal according to a power source of the driver stage circuit, a level of the load, a temperature associated with the class D amplifier circuit, or the operating frequency, wherein the operating frequency corresponds to the operating period.

17. The BD type pulse width modulation method of claim 12, wherein the offset is related to the light load threshold.

18. The BD type pulse width modulation method of claim 12, wherein the basic modulation signal and the offset modulation signal are each configured as a triangular wave or a sawtooth wave, wherein the basic modulation signal and the offset modulation signal are synchronized with the operation period.

19. The BD type pulse width modulation method of claim 18, wherein an absolute value of the offset is smaller than 1/2 of a peak-to-peak value of the basic modulation signal.

20. The BD type pulse width modulation method according to claim 12, wherein,

the step of generating the basic PWM signal includes:

comparing an in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and

comparing the basic modulation signal with an inverted input signal of the pair of input signals to generate the inverted sub-signal of the basic PWM signal;

the step of generating the offset PWM signal includes:

comparing the in-phase input signal of the pair of input signals with the offset modulation signal to generate the in-phase sub-signal of the offset PWM signal; and

the offset modulation signal is compared with the inverted input signal of the pair of input signals to generate the inverted sub-signal of the offset PWM signal.

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