CN101527548A - Circuit and method for generating PWM control signals by class D amplifier - Google Patents
Circuit and method for generating PWM control signals by class D amplifier Download PDFInfo
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- CN101527548A CN101527548A CN200810083528A CN200810083528A CN101527548A CN 101527548 A CN101527548 A CN 101527548A CN 200810083528 A CN200810083528 A CN 200810083528A CN 200810083528 A CN200810083528 A CN 200810083528A CN 101527548 A CN101527548 A CN 101527548A
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Abstract
The invention relates to a circuit and a method for generating PWM control signals by class D amplifiers. The circuit comprises a hysteresis comparator and a pulse processing unit, and is characterized in that the hysteresis comparator generates a basic PWM signal by comparing a single-ended input signal and a carrier signal; and the pulse processing unit generates a halfwidth PWM signal by subtracting the basic PWM signal and a reference periodic signal, and the pulse width of the halfwidth PWM signal is doubled so as to generate a PWM control signal.
Description
Technical field
The present invention relates to a kind of control circuit, specifically, is the circuit that a kind of D class A amplifier A produces pwm control signal.
Background technology
Switching amplifier, be called the D class A amplifier A again, compare, have the advantage on the efficient and the interests of corresponding generation with class ab ammplifier, its operation principle is to utilize the high frequency modulating method that the input signal of analog or digital is converted to the signal of second order, uses and switches full H bridge or half H bridge switch.The handoff loss of these switches is low, so the efficient of amplifier improves.In known D class A amplifier A, great majority adopt pulse-width modulation (Pulse Width Modulation; PWM) framework, typical message PWMD class A amplifier A between 100KHz to the switching frequency work between the 500KHz, higher switching frequency can further reduce distortion, but can cause lower efficient.Because the D class A amplifier A extends from the switch type power supply structure, therefore the same with the overwhelming majority's exchange type power Management Unit have an electromagnetic interference (Electro-Magnetic Interfering; EMI) problem.
Fig. 1 is the pwm signal of known D class A amplifier A.As shown in Figure 1, one at bridging load (Bridge-Tied-Load; BTL) the D class A amplifier A in the configuration produce two anti-phase pwm signal Out+ and Out-its differential output on, so the amplitude of its differential output (Out+-Out-) is the twice (2Vdd) of the amplitude of pwm signal Out+ or Out-.Because the amplitude of this differential output is big, so the ripple on the load current is also big.This class A amplifier A always needs external choke-condenser filter to remove high frequency switching carrier, but this filter is unfavorable for the miniaturization of circuit volume.In addition, this choke-condenser filter also causes the problem of EMI, and this is because this two anti-phase pwm signal Out+ and Out-produces big EMI interference.For this reason, many people propose the D class A amplifier A that reduces EMI and do not use filter, and for example US 6,614, and 297, US 6,847,257 and US 6,970,123.
Fig. 2 is the sequential chart of known differential input D class A amplifier A.As shown in the figure, the D class A amplifier A of known differential input, differential input signal Vin+ and Vin-compare with sawtooth waveforms carrier Vref respectively, produce two pwm signal PWM+ and PWM-, the two subtracts each other generation output pwm signal OutputPWM, is used for driving the power stage of D class A amplifier A.The amplitude of this output pwm signal Output PWM is identical with the amplitude of pwm signal PWM+ and PWM-, so the ripple on the load current is less.
For differential input D class A amplifier A, input information and power output are designed among the difference of two pwm signal PWM+ and PWM-.As shown in Figure 2, the pulse duration that pwm signal PWM+ or PWM-and 50%duty cycle subtract each other generation is half of output pwm signal OutputPWM, and in other words, the pulse of output pwm signal Output PWM is to the rising edge symmetry of 50%dutycycle.Yet, under identical gain, 1/4th of the D class A amplifier A that uses its power output of D class A amplifier A of single-ended input signal to have only to use complete differential input signal.In known technology, single-ended input signal is always handled through gain stage earlier, is converted into complete differential input signal.Next must use this differential input signal to produce the pwm control signal of ternary or four attitudes, otherwise be to use two anti-phase sawtooth waveforms or triangular signal to produce the pwm control signal of ternary or four attitudes as the carrier signal.
Therefore known D class A amplifier A exist above-mentioned all inconvenience and problem.
Summary of the invention
One object of the present invention is to propose a kind of circuit that produces pwm control signal for the D class A amplifier A.
Another object of the present invention is to propose a kind of method that produces pwm control signal for the D class A amplifier A.
For achieving the above object, technical solution of the present invention is:
A kind of D class A amplifier A produces the circuit of pwm control signal, comprises a hysteresis comparator and a pulse processing unit, it is characterized in that:
Described hysteresis comparator is by comparing a single-ended input signal and a carrier signal to produce a basic pwm signal;
Described pulse processing unit produces a half-breadth pwm signal with a described basic pwm signal and a reference period signal subtraction, and the pulse duration of described half-breadth pwm signal increased doubly produces pwm control signal.
The circuit that D class A amplifier A of the present invention produces pwm control signal can also be further achieved by the following technical measures.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, wherein also comprises a pretreatment unit, is the single-ended input signal of unipolarity with described single-ended input signal preliminary treatment.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, and wherein said pretreatment unit comprises a comparator, and the accurate position of a more described single-ended input signal of described comparator and a direct current is to judge its polarity.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, and wherein said pretreatment unit more comprises:
One circuit for reversing is in order to being second polarity with described single-ended input signal from first polarity transformation;
One bypass resistance, adding described single-ended input signal in order to the part of described single-ended input signal second polarity of bypass is the part of second polarity from first polarity transformation, becomes the single-ended input signal of described unipolarity.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, and wherein said pulse processing unit comprises a subtracter, in order to described basic pwm signal and described reference period signal subtraction to produce described half-breadth pwm signal.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, and wherein said pulse processing unit comprises a pulse copied cells, in order to duplicate the pulse of described half-breadth pwm signal.
Aforesaid D class A amplifier A produces the circuit of pwm control signal, and wherein said pulse processing unit comprises a delay circuit, postpones described pwm control signal.
The present invention also provides a kind of D class A amplifier A to produce the method for pwm control signal, comprises the following steps:
(A) compare a single-ended input signal and a carrier signal, to produce a basic pwm signal;
(B) with a described basic pwm signal and a reference period signal subtraction, to produce a half-breadth pwm signal; And
(C) pulse duration with described half-breadth pwm signal increases doubly, to produce described pwm control signal.
The method that D class A amplifier A of the present invention produces pwm control signal can also be further achieved by the following technical measures.
Aforesaid D class A amplifier A produces the method for pwm control signal, wherein also comprises the following steps:
(D) be the single-ended input signal of unipolarity with described single-ended input signal preliminary treatment.
Aforesaid D class A amplifier A produces the method for pwm control signal, and wherein said step (D) comprises more described single-ended input signal and the accurate position of a direct current, to judge its polarity.
Aforesaid D class A amplifier A produces the method for pwm control signal, and wherein said step (D) more comprises the following steps:
Is second polarity with described single-ended input signal from first polarity transformation; And
It is the part of second polarity from first polarity transformation that the part of described single-ended input signal second polarity is added described single-ended input signal, becomes the single-ended input signal of described unipolarity.
Aforesaid D class A amplifier A produces the method for pwm control signal, and wherein said step (C) comprises the pulse of duplicating described half-breadth pwm signal.
Aforesaid D class A amplifier A produces the method for pwm control signal, and wherein said step (C) comprises the described pwm control signal of delay.
After adopting technique scheme, the circuit that D class A amplifier A of the present invention produces pwm control signal has the following advantages:
The input signal that the present invention uses is single-ended input, and whole signal processing path all keeps single-ended input, but its power output but can be the same big with the D class A amplifier A of the complete differential input signal of known use.
Description of drawings
Fig. 1 is the pwm signal of known D class A amplifier A;
Fig. 2 is the sequential chart of known differential input D class A amplifier A;
Fig. 3 is the calcspar of the first embodiment of the present invention;
Fig. 4 is the embodiment of the pulse processing unit of Fig. 3;
Fig. 5 is the sequential chart of Fig. 3 circuit;
Fig. 6 is the second embodiment of the present invention;
Fig. 7 is the embodiment of the pulse processing unit of Fig. 6; And
Fig. 8 is the sequential chart of Fig. 6 circuit.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof the present invention is illustrated further.
Now see also Fig. 3, Fig. 3 is the calcspar of the first embodiment of the present invention.Wherein utilize pretreatment unit that single-ended input signal Vin preliminary treatment is become negative single-ended input signal Vin-earlier, carry out single-ended signal again and handle.In pretreatment unit, described polarity judging unit 10 uses for example comparator, and more single-ended input signal Vin and one is 0 volt the accurate position of direct current for example, as single-ended input signal Vin when being positive, change into negatively via circuit for reversing 12, offer hysteresis comparator 16 again; When single-ended input signal Vin when negative, then directly offer hysteresis comparator 16 via bypass resistance 14.Hysteresis comparator 16 compares single-ended input signal Vin-of pretreated unipolarity and sawtooth waveforms carrier Vref, produce basic pwm signal, have the pwm control signal Ctrl1 of same pulse width and phase place and gate pole driver and the H bridge output power stage 20 that Ctrl2 gives the D class A amplifier A by pulse processing unit 18 from the output pwm signal Output PWM that basic pwm signal and reference period signal produce with Fig. 2 again.
See also Fig. 4 again, Fig. 4 is the embodiment of pulse processing unit 18, oscillogram with reference to Fig. 5 is described as follows: the reference period signal uses for example clock signal, it has 50%duty cycle, subtract each other generation half-breadth pwm signal with basic pwm signal through subtracter 182, promptly the PWM-50%duty cycle of Fig. 5 is duplicated its pulse by pulse copied cells 184 again, make the pulse duration multiplication, become complete output pwm signal and duplicate.Switch 186 and 188 switches according to the polarity of single-ended input signal Vin, and when single-ended input signal Vin was positive, switch 186 was shut, and switch 188 is opened, and pwm control signal Ctrl1 equals output pwm signal and duplicates, and pwm control signal Ctrl2 is 0; Otherwise when single-ended input signal Vin was negative, switch 186 was opened, switch 188 is shut, pwm control signal Ctrl1 is 0, and pwm control signal Ctrl2 equals output pwm signal and duplicates, and the voltage that is applied in the load is the difference of pwm control signal Ctrl1 and Ctrl2.
Fig. 6 is the second embodiment of the present invention, hysteresis comparator 30 more single-ended input signal Vin and sawtooth waveforms carrier Vref produce basic pwm signal, by pulse processing unit 32 basic pwm signal and 50%duty cycle are subtracted each other also copy pulse again, produce pwm control signal Ctrl1 and Ctrl2 and give gate pole driver and H bridge output power stage 34.Fig. 7 provides the embodiment of a pulse processing unit 32, and its relevant signal waveform as shown in Figure 8.Present embodiment is not done preliminary treatment to single-ended input signal Vin, the half-breadth pwm signal that Vin produces less than zero time is the same with the embodiment of Fig. 3, waveform after duplicating just and the Output PWM of Fig. 2 have same pulse width and phase place, but it is different with the phase place of the Output PWM of Fig. 2 that the half pulse duration drive signal that Vin produces greater than zero time is duplicated the back, therefore, delayed again circuit 326 postpones the N cycle, and the signal of exporting to gate pole driver and H bridge output power stage at last has correct phase place.N viewable design person's demand and determining, if Output on sequential correctly.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique under the situation that does not break away from the spirit and scope of the present invention, can also be made various conversion or variation.Therefore, all technical schemes that are equal to also should belong to category of the present invention, should be limited by each claim.
Claims (13)
1. the circuit of a D class A amplifier A generation pwm control signal comprises a hysteresis comparator and a pulse processing unit, it is characterized in that:
Described hysteresis comparator is by comparing a single-ended input signal and a carrier signal to produce a basic pwm signal;
Described pulse processing unit produces a half-breadth pwm signal with a described basic pwm signal and a reference period signal subtraction, and the pulse duration of described half-breadth pwm signal increased doubly produces pwm control signal.
2. D class A amplifier A as claimed in claim 1 produces the circuit of pwm control signal, and it is characterized in that: also comprising a pretreatment unit, is the single-ended input signal of unipolarity with described single-ended input signal preliminary treatment.
3. D class A amplifier A as claimed in claim 2 produces the circuit of pwm control signal, and it is characterized in that: described pretreatment unit comprises a comparator, and the accurate position of a more described single-ended input signal of described comparator and a direct current is to judge its polarity.
4. D class A amplifier A as claimed in claim 3 produces the circuit of pwm control signal, and it is characterized in that: described pretreatment unit more comprises:
One circuit for reversing is in order to being second polarity with described single-ended input signal from first polarity transformation;
One bypass resistance, adding described single-ended input signal in order to the part of described single-ended input signal second polarity of bypass is the part of second polarity from first polarity transformation, becomes the single-ended input signal of described unipolarity.
5. D class A amplifier A as claimed in claim 1 produces the circuit of pwm control signal, and it is characterized in that: described pulse processing unit comprises a subtracter, in order to described basic pwm signal and described reference period signal subtraction to produce described half-breadth pwm signal.
6. D class A amplifier A as claimed in claim 1 produces the circuit of pwm control signal, and it is characterized in that: described pulse processing unit comprises a pulse copied cells, in order to duplicate the pulse of described half-breadth pwm signal.
7. D class A amplifier A as claimed in claim 1 produces the circuit of pwm control signal, and it is characterized in that: described pulse processing unit comprises a delay circuit, postpones described pwm control signal.
8. the method for a D class A amplifier A generation pwm control signal is characterized in that: comprise the following steps:
(A) compare a single-ended input signal and a carrier signal, to produce a basic pwm signal;
(B) with a described basic pwm signal and a reference period signal subtraction, to produce a half-breadth pwm signal; And
(C) pulse duration with described half-breadth pwm signal increases doubly, to produce described pwm control signal.
9. method as claimed in claim 8 is characterized in that: also comprise the following steps:
(D) be the single-ended input signal of unipolarity with described single-ended input signal preliminary treatment.
10. method as claimed in claim 9 is characterized in that: described step (D) comprises more described single-ended input signal and the accurate position of a direct current, to judge its polarity.
11. method as claimed in claim 10 is characterized in that: described step (D) more comprises the following steps:
Is second polarity with described single-ended input signal from first polarity transformation; And
It is the part of second polarity from first polarity transformation that the part of described single-ended input signal second polarity is added described single-ended input signal, becomes the single-ended input signal of described unipolarity.
12. method as claimed in claim 8 is characterized in that: described step (C) comprises the pulse of duplicating described half-breadth pwm signal.
13. method as claimed in claim 8 is characterized in that: described step (C) comprises the described pwm control signal of delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810083528A CN101527548A (en) | 2008-03-05 | 2008-03-05 | Circuit and method for generating PWM control signals by class D amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810083528A CN101527548A (en) | 2008-03-05 | 2008-03-05 | Circuit and method for generating PWM control signals by class D amplifier |
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| CN101527548A true CN101527548A (en) | 2009-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810083528A Pending CN101527548A (en) | 2008-03-05 | 2008-03-05 | Circuit and method for generating PWM control signals by class D amplifier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315842A (en) * | 2011-04-22 | 2012-01-11 | 北京科诺伟业科技有限公司 | Single-pole SPWM (Sine Pulse Width Modulation) method and single-pole SPWM circuit |
| CN103607185A (en) * | 2013-11-27 | 2014-02-26 | 矽力杰半导体技术(杭州)有限公司 | Device and method for generating pulse width modulation signal |
-
2008
- 2008-03-05 CN CN200810083528A patent/CN101527548A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315842A (en) * | 2011-04-22 | 2012-01-11 | 北京科诺伟业科技有限公司 | Single-pole SPWM (Sine Pulse Width Modulation) method and single-pole SPWM circuit |
| CN103607185A (en) * | 2013-11-27 | 2014-02-26 | 矽力杰半导体技术(杭州)有限公司 | Device and method for generating pulse width modulation signal |
| CN103607185B (en) * | 2013-11-27 | 2016-03-30 | 矽力杰半导体技术(杭州)有限公司 | Produce the device and method of pulse-width signal |
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Application publication date: 20090909 |