CN115132686A - Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof - Google Patents

Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof Download PDF

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Publication number
CN115132686A
CN115132686A CN202210742901.2A CN202210742901A CN115132686A CN 115132686 A CN115132686 A CN 115132686A CN 202210742901 A CN202210742901 A CN 202210742901A CN 115132686 A CN115132686 A CN 115132686A
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Prior art keywords
metal
pad
impedance
abf
bga
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CN202210742901.2A
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杨成林
周云燕
宋阳
宋刚
曹立强
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN202210742901.2A priority Critical patent/CN115132686A/en
Publication of CN115132686A publication Critical patent/CN115132686A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a pad impedance optimization structure in an FCBGA substrate, which comprises: one or more layers of cavities which are positioned right above or right below the BGA bonding pad, wherein the cavities are metal-free blank areas which are opposite to the BGA bonding pad in one or more layers of metal wiring layers; and a plurality of metal strips extending from the metal wiring layer to the voids.

Description

Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof.
Background
With the increasing demand for high-density and high-speed SiP (system in package) integration, the high-speed signal in the SiP may face a plurality of impedance discontinuity structures, and the problem of impedance matching of the high-speed signal in the micro system is more prominent. Such as ball pads, vias, and via pads of FCBGA (flip chip ball grid array) substrates, cause impedance discontinuities in the high speed path, and these impedance discontinuities all contribute to poor transmission performance. Therefore, when the high-speed high-density system-level packaging is arranged, the influence of the impedance discontinuous structure on the transmission performance is eliminated as much as possible by using a reasonable structure, the transmission performance of high-speed signals is improved, and the stable function of the system is ensured.
At present, the main way of improving the high-speed and high-density SiP impedance discontinuity structure is to reduce the impedance variation amplitude way at the impedance discontinuity position, for example, for the impedance discontinuity structure of the via hole, the common methods for reducing the impedance discontinuity of the via hole mainly include: and adopting a diskless process, selecting a wire outlet mode, optimizing the diameter of the anti-bonding pad and the like. For the impedance discontinuous structure of the bonding pad, the adjustment of the thickness of a medium and the hollowing of the ground plane right above/below the bonding pad are mainly adopted at present, and the distributed capacitance of the bonding pad can be reduced through the above modes. But within a limited adjustment range of the thickness of the medium, the resistance discontinuous structure of the bonding pad needs to hollowing out multiple layers of power/ground planes right above/below the bonding pad. Fig. 1 shows a prior art impedance optimization structure hollowed out over a bond pad. The power/ground planes 40 of the multiple layers directly above/below the bonding pad 30 are hollowed out as shown in fig. 1.
Although the hollowing process can optimize the electrical performance of the transmission structure, for the optimized structure requiring hollowing of multiple layers of power supply/ground planes right above/below the large pad structure, the optimized structure with continuous multiple layers and large area hollowing has a serious preparation problem for the preparation process of the FCBGA substrate, which affects the reliability of the final product.
Disclosure of Invention
The invention aims to provide a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof, wherein the pad impedance optimization structure can play a supporting role while optimizing the impedance of a BGA pad, and prevents the conditions that the pressing thickness of a medium is inconsistent and gaps exist among multiple layers of ABF thin composite materials in the process of pressing the ABF thin composite materials.
In a first aspect of the present invention, to solve the problems in the prior art, the present invention provides a pad impedance optimization structure in an FCBGA substrate, including:
one or more layers of cavities which are positioned right above or right below the BGA bonding pad, wherein the cavities are metal-free blank areas which are opposite to the BGA bonding pad in one or more layers of metal wiring layers; and
a plurality of metal strips extending from the metal wiring layer to the void.
Further, the plurality of metal strips located on the same layer are connected or not connected with each other.
Further, the diameter of the hollow is 600 μm to 1000 μm.
Further, the length of the metal strip is 300-1000 μm, and the width is 30-70 μm.
Further, the pad impedance optimization structure is formed simultaneously with the metal wiring layer.
In a second aspect of the present invention, to solve the problems in the prior art, the present invention provides a method for manufacturing a pad impedance optimization structure in an FCBGA substrate, including:
laminating the second metal plate, the ABF thin composite material, the first substrate, the ABF thin composite material and the second metal plate from top to bottom in sequence, and laminating;
removing the second metal plate;
manufacturing a blind hole penetrating through the ABF thin composite material, filling metal into the blind hole to form a second conductive through hole, and forming a first metal layer on the surface of the ABF thin composite material; and
and etching the first metal layer to form a second metal wiring layer, and simultaneously forming a pad impedance optimization structure in the area opposite to the pad, wherein the pad impedance optimization structure is a cavity with a metal strip.
Further, repeating the step of laminating the ABF thin composite material for multiple times to the step of forming the pad impedance optimization structure to obtain multiple layers of cavities with metal strips.
Further, the plurality of metal strips on the same layer are connected or not connected with each other; and/or
The length of the metal strip is 300-1000 μm, and the width is 30-70 μm.
Further, the area of the hollow is 1-1.67 times that of the BGA pad.
The invention has at least the following beneficial effects: the invention discloses a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof, wherein the pad impedance optimization structure can play a supporting role while optimizing the impedance of a BGA pad, and can prevent the condition that gaps exist among a plurality of layers of ABF thin composite materials due to the inconsistent medium pressing thickness in the process of pressing the ABF thin composite materials; the pad impedance optimization structure can avoid board explosion during manufacturing of the FCBGA substrate; the pad impedance optimization structure and the metal rewiring on the surface of the thin ABF composite material are formed simultaneously, no additional process step is added, the operation is simple, and the feasibility is high.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 illustrates a prior art impedance optimization structure hollowed out over a bond pad;
FIG. 2 shows a schematic cross-sectional view of a BGA pad superstructure in accordance with the prior art;
FIG. 3 shows a schematic diagram of a BGA pad without optimized impedance, according to the prior art;
FIG. 4 shows a TDR impedance simulation of a BGA pad after impedance optimization for small area undercutting according to the prior art;
FIG. 5 shows a schematic diagram of optimizing BGA pad impedance for large area voiding according to the prior art;
FIG. 6 shows a TDR impedance simulation graph of a BGA pad after large area voiding to optimize impedance according to the prior art;
FIG. 7 is a schematic cross-sectional view of a process for fabricating a FCBGA substrate, in accordance with one embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating the separation of an optimized structure of a BGA pad, in accordance with one embodiment of the present invention;
FIG. 9 is a schematic diagram of a composite of an optimized structure of a BGA pad in accordance with one embodiment of the present invention; and
fig. 10 shows a graph of TDR impedance simulation of a BGA pad optimized by an optimization structure according to an embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
A conventional technique to optimize the impedance of the BGA pad is to void the metal directly above/below the BGA pad when fabricated on the FCBGA substrate. When the FCBGA substrate with the multilayer board is manufactured, the ABF thin composite material needs to be pressed for multiple times, and a metal wiring layer is manufactured on the surface of the ABF thin composite material. By adopting a conventional BGA (ball grid array) pad impedance optimization method, the inconsistency of the medium lamination thickness exists in the process of laminating the ABF thin composite material for many times, the uniformity of the thickness of the electroplated metal on the surface of the ABF thin composite material cannot be ensured, and gaps exist among multiple layers of ABF thin composite materials, so that the plate explosion can be caused in the subsequent heating process.
FIG. 2 shows a schematic cross-sectional view of a BGA pad superstructure in accordance with the prior art;
FIG. 3 shows a schematic diagram of a BGA pad without optimized impedance, according to the prior art; and
fig. 4 shows a graph of a TDR impedance simulation of a BGA pad after impedance optimization by small area voiding according to the prior art.
As shown in fig. 2 and 3, a second ABF thin composite material 102, a third metal wiring layer 103, a first ABF thin composite material 104, and a second metal wiring layer 105 are sequentially disposed above the BGA pad 101. Wherein the metal planes of third metal wiring layer 103 and second metal wiring layer 105 have a significant effect on the impedance of BGA pad 101. As shown in fig. 4, if the metal planes of the third metal wiring layer 103 and the second metal wiring layer 105 above the BGA pad 101 are hollowed to have a diameter of 200 μm, the TDR (time domain reflectometer) impedance value of the BGA pad 101 is at a low position, and a high-speed signal is easily reflected at a place where the impedance is not matched, so that the transmission performance of the BGA pad is not guaranteed, and it can be seen from the simulation result that the impedance value at the BGA pad is only 39.27 Ω, and the error from the impedance of the standard 50 Ω is-21.4%.
FIG. 5 shows a schematic diagram of optimizing BGA pad impedance for large area voiding in accordance with the prior art; fig. 6 shows a graph of a TDR impedance simulation of a BGA pad after optimizing impedance by hollowing out a large area according to the prior art.
As shown in fig. 5 and 6, when the metal planes of the third metal wiring layer 103 and the second metal wiring layer 105 above the BGA pad 101 are hollowed out to have a diameter of 800 μm, the TDR resistance of the BGA pad 101 can be maintained at about 50 Ω, and the impedance mismatch at this position, where high-speed signals are likely to occur, can be improved well, thereby ensuring the transmission performance. Simulation results show that the impedance value at the BGA pad can reach 48.68 omega, and the error of the impedance from the standard 50 omega is only-2.6%. However, the large-area hollowing treatment can cause a relatively serious process problem in the step of laminating the ABF thin composite materials in the manufacturing process of the FCBGA substrate, because a large-area metal layer is continuously lost, the medium has the condition of uneven laminating thickness during laminating, so that the metal layer in the subsequent electroplating process is uneven, even a cavity is generated in the laminating process between the ABF thin composite materials due to the large-area metal layer loss, and even a plate explosion phenomenon can be caused.
Therefore, there is a need to improve the impedance optimization structure with serious manufacturing problems, and to provide an optimization structure that can ensure the transmission performance of the BGA substrate to some extent while having manufacturability.
FIG. 7 is a schematic cross-sectional view of a manufacturing process for an FCBGA substrate, in accordance with one embodiment of the present invention; FIG. 8 is a schematic diagram illustrating the separation of an optimized structure of a BGA pad in accordance with one embodiment of the present invention; FIG. 9 is a schematic diagram of a composite of an optimized structure of a BGA pad in accordance with one embodiment of the present invention; fig. 10 shows a graph of TDR impedance simulation of a BGA pad optimized by an optimization structure according to an embodiment of the present invention.
As shown in fig. 7, a method for manufacturing an FCBGA substrate includes:
in step 1, a first metal plate 202 is covered on the front and back surfaces of a first substrate 201.
In step 2, a first via 203 is made by etching through the first substrate 201 and the first metal plate 202.
In step 3, a first conductive via 204 is formed by filling metal in the first via 203 by electroplating, electroless plating, deposition, or the like.
In step 4, the first metal plate 202 is etched to form a first wiring layer 205 on the front and back surfaces of the first substrate 201. A first metal routing layer 205 electrically connects the first conductive vias 204.
In step 5, the second metal plate 206, the ABF thin composite material 207, the first substrate 201, the ABF thin composite material 207, and the second metal plate 206 are sequentially stacked from top to bottom, and then are pressed. For example, a vacuum lamination process may be used.
In step 6, the second metal plate 206 is removed by a copper reduction process.
In step 7, blind vias 208 are made through the thin composite material 207 of ABF, exposing portions of the first metal routing layer 205.
In step 8, a second conductive via 209 is formed by filling metal in the blind via 208 by electroplating, electroless plating, deposition, etc., and a first metal layer 210 is formed on the surface of the first ABF thin composite material 207.
In step 9, the first metal layer 210 is etched to form a second metal wiring layer 211. The second metal wiring layer 211 is electrically connected to the first metal wiring layer 205 through the second conductive via 209.
In step 10, a solder resist layer 212 covering the second metal wiring layer 211 is fabricated by coating, deposition, or the like.
In step 11, the solder resist layer on the part of the second metal wiring layer 211 is removed, the part of the second metal wiring layer 211 is exposed as a BGA pad, and a protective layer is coated on the exposed surface of the second metal wiring layer 211. Such as gold or nickel-plated palladium-gold or an organic solder resist (OSP) coating.
And repeating the step 5 to the step 9, and carrying out ABF thin composite material stitching, blind hole manufacturing and metal wiring layer manufacturing for multiple times, so that the multiple ABF thin composite materials are laminated, and the second metal wiring layer to the Nth metal wiring layer which are interconnected are obtained.
The existing BGA bonding pad impedance optimization method is to hollows out a metal plane of a metal wiring layer which is positioned right above a BGA bonding pad, and due to continuous large-area metal loss, when an ABF thin composite material is laminated, a medium has the condition of uneven lamination thickness, so that the problem of uneven metal layer of a subsequent electroplating process is caused, and even a cavity is generated in the laminating process between the ABF thin composite materials. The invention provides a BGA impedance optimization structure which can optimize BGA impedance and avoid the problems of uneven thickness and void generation in the laminating process of ABF thin composite materials.
As shown in fig. 8 and 9, when one or more second metal wiring layers corresponding to ABF thin composite material are manufactured, a BGA pad impedance optimization structure with metal strips is manufactured at a position right above/below the subsequent BGA pad 101. The BGA pad impedance optimizing structure includes a hollow space facing the BGA pad 101, a plurality of metal bars 106 having a diameter of 600 μm to 1000 μm and extending from the third metal wiring layer 103 and the second metal wiring layer 105 to the hollow space, and the BGA pad 101 having a size of 500 μm to 800 μm. In other words, the void area is 1-1.67 times that of the BGA pad 101. The cavity is filled with a medium. The plurality of metal strips 106 located on the same layer are symmetrically distributed, and may or may not be connected to each other. Preferably, the number of metal strips 106 is even. The metal strip 106 has a length of 300 μm to 1000 μm and a width of 30 μm to 70 μm. When the BGA pad 101 has a plurality of metal wiring layers on the upper/lower part, the corresponding position of each second metal wiring layer is provided with the BGA pad impedance optimization structure with the metal strip, and the positions of the metal strips of the BGA pad impedance optimization structure with the metal strip on each layer are different and form a certain angle. The BGA bonding pad impedance optimization structure with the metal strip is formed at the same time of manufacturing the metal wiring layer, and no additional process step is added.
As shown in fig. 10, an impedance optimization structure of a BGA pad with metal strips is provided, for example, 2 layers of ABF thin composite material and 2 layers of second metal wiring layer are provided above the BGA pad, the diameter of the cavity is 800 μm, 4 metal strips are selected, the TDR impedance value of the BGA pad with BGA pad diameter of 600 μm can be maintained around 50 Ω, impedance mismatch at this position is easily improved for high-speed signals, and transmission performance is guaranteed. The simulation result shows that the impedance value at the BGA bonding pad can reach 46.42 omega, the error from the standard 50 omega impedance is only-7.2%, the optimized structure improves the problems of the conventional optimized structure in the ABF thin composite material laminating process in the FCBGA substrate preparation process, the occurrence of plate explosion can be effectively avoided, the consistency of the medium laminating thickness can be better controlled, and the uniformity of the thickness of the electroplated metal can be ensured.
The invention has at least the following beneficial effects: the invention discloses a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof, wherein the pad impedance optimization structure can play a supporting role while optimizing the impedance of a BGA pad, and can prevent the condition that gaps exist among a plurality of layers of ABF thin composite materials due to the inconsistent medium pressing thickness in the process of pressing the ABF thin composite materials; the pad impedance optimization structure can avoid board explosion during manufacturing of the FCBGA substrate; the pad impedance optimization structure and the metal rewiring on the surface of the thin ABF composite material are formed simultaneously, no additional process step is added, the operation is simple, and the feasibility is high.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (10)

1. A pad impedance optimization structure in an FCBGA substrate, comprising:
one or more layers of cavities which are positioned right above or right below the BGA bonding pad, wherein the cavities are metal-free blank areas which are opposite to the BGA bonding pad in one or more layers of metal wiring layers; and
a plurality of metal strips extending from the metal wiring layer to the void.
2. The FCBGA substrate of claim 1, wherein the plurality of metal strips in the same layer are connected or disconnected from each other.
3. The FCBGA substrate of claim 1, wherein the voids are 600-1000 μm in diameter.
4. The FCBGA substrate of claim 1, wherein the metal strip has a length of 300-1000 μm and a width of 30-70 μm.
5. The FCBGA substrate of claim 1, wherein the pad impedance optimization structure is formed simultaneously with a metal routing layer.
6. The pad impedance optimizing structure in an FCBGA substrate of claim 1, wherein the void has an area 1-1.67 times the area of the BGA pad.
7. A method of fabricating a pad impedance optimization structure in an FCBGA substrate, comprising:
laminating the second metal plate, the ABF thin composite material, the first substrate, the ABF thin composite material and the second metal plate from top to bottom in sequence, and laminating;
removing the second metal plate;
manufacturing a blind hole penetrating through the ABF thin composite material, filling metal into the blind hole to form a second conductive through hole, and forming a first metal layer on the surface of the ABF thin composite material; and
and etching the first metal layer to form a second metal wiring layer, and forming a pad impedance optimization structure in a region opposite to the pad, wherein the pad impedance optimization structure is a cavity with a metal strip.
8. The method of claim 7, wherein the step of laminating the thin ABF composite material to form the pad impedance optimization structure is repeated a plurality of times to obtain a plurality of layers of voids with metal strips.
9. The method of claim 7, wherein said plurality of metal strips in the same layer are connected or disconnected from each other; and/or
The length of the metal strip is 300-1000 μm, and the width is 30-70 μm.
10. The method of manufacturing a pad impedance optimizing structure in a FCBGA substrate of claim 7, wherein the void has an area 1-1.67 times the area of the BGA pad.
CN202210742901.2A 2022-06-28 2022-06-28 Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof Pending CN115132686A (en)

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CN202210742901.2A CN115132686A (en) 2022-06-28 2022-06-28 Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof

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CN202210742901.2A CN115132686A (en) 2022-06-28 2022-06-28 Bonding pad impedance optimization structure in FCBGA substrate and manufacturing method thereof

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