CN115132591B - Preparation method of polyimide via hole and wafer level semiconductor packaging structure - Google Patents
Preparation method of polyimide via hole and wafer level semiconductor packaging structure Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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Abstract
The invention provides a preparation method of a polyimide via hole and a wafer level semiconductor packaging structure, wherein the preparation method of the polyimide via hole comprises the following steps: s1: providing a substrate with a metal bonding pad attached to the surface; s2: forming a polyimide layer on a substrate; s3: forming a metal layer on the polyimide layer; s4: forming a preset layer on the metal layer, and forming a first pre-via hole on the preset layer; s5: etching the metal layer to form a second pre-via hole; s6: etching the polyimide layer to form a third pre-via hole; s7: and removing all the structures above the polyimide layer to form the polyimide through hole on the polyimide layer. The invention avoids the problem that residues exist at the bottom of the small-size polyimide via hole, so that the upper and lower outlines of the polyimide via hole are basically consistent, the preparation process is refined, and the yield of products is improved; in the wafer level semiconductor packaging, the smaller polyimide through hole can make the product design more complicated and more detailed, and greatly improves the chip performance.
Description
Technical Field
The invention relates to the technical field of advanced semiconductor packaging, in particular to a preparation method of a polyimide through hole and a wafer level semiconductor packaging structure.
Background
With the rapid development of electronic science and technology, the trend of miniaturization of microelectronic technology is developing, and the research on wafer level packaging materials is deepening. The early wafer level packaging material was Benzocyclobutene (BCB), but was gradually eliminated due to its low elongation at break, low tensile strength, high process cost, and the like. Polyimide (PI) is a polymer material and has excellent thermal stability, mechanical properties, chemical stability, dielectric properties, insulating properties, adhesive force and water resistance, and is widely used in the fields of aerospace, microelectronics and the like. Particularly, polyimide is one of the most important interlayer dielectric materials in advanced semiconductor packaging processes such as wafer level packaging. As shown in fig. 1 to 3, in the conventional prior art, polyimide vias are generally prepared by coating, exposing, developing and curing, and then connecting upper and lower Redistribution layers (RDLs), but the polyimide via profile varies greatly from top to bottom, the process is not precise, and residues are left at the bottom of the via. Advanced semiconductor packaging technology requires smaller sized polyimide vias to improve chip performance, and therefore process optimization and improvement are needed.
In view of the above, it is necessary to provide a method for manufacturing a polyimide via hole and a semiconductor package structure, which avoid the problem of residues at the bottom of the small-sized polyimide via hole, so that the upper and lower outlines of the polyimide via hole are substantially consistent, and the manufacturing process is fine, thereby improving the yield of products and greatly improving the performance of chips.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for manufacturing a polyimide via hole and a wafer level semiconductor package structure, which are used to avoid the problem of residues existing at the bottom of a small-sized polyimide via hole, so that the upper and lower contours of the polyimide via hole are substantially consistent, and the manufacturing process is refined, thereby improving the yield of products and greatly improving the performance of chips.
In order to achieve the above object, the present invention provides a method for preparing a polyimide via hole, the method comprising:
s1: providing a substrate with a metal bonding pad attached to the surface;
s2: forming a polyimide layer on the substrate, wherein the top of the polyimide layer is higher than the metal pad;
s3: forming a metal layer on the polyimide layer;
s4: forming a preset layer on the metal layer, and forming a first pre-via hole on the preset layer, wherein the first pre-via hole is positioned right above the metal pad, and the aperture size of the first pre-via hole is less than or equal to 2 μm;
s5: etching the metal layer to form a second pre-via hole based on the first pre-via hole;
s6: etching the polyimide layer to form a third pre-via hole based on the second pre-via hole, wherein the third pre-via hole is positioned vertically above the metal pad and is in direct contact with the metal pad;
s7: and removing all structures above the polyimide layer to form a polyimide through hole on the polyimide layer.
Optionally, the first pre-via, the second pre-via, and the third pre-via have the same aperture size.
Optionally, the step of forming the polyimide layer comprises: coating, full exposure and curing.
Optionally, in step S4, the step of forming the preset layer includes: forming a patterned preset light resistance layer on the metal layer, wherein the preset light resistance layer is positioned vertically above the metal bonding pad, and the diameter size of the preset light resistance layer is less than or equal to 2 mu m; electroplating metal on the metal layer to form the preset layer, wherein the preset layer fills gaps among the preset photoresist layers and is flush with the tops of the preset photoresist layers; and etching all the preset photoresist layer, thereby forming the first pre-via hole at the position of the preset photoresist layer. Optionally, in step S4, the preset layer is a photoresist layer, the step of forming the preset layer includes coating, exposing, and developing, and etching the preset layer to form the first pre-via hole, the first pre-via hole is located right above the metal pad, the aperture size of the first pre-via hole is less than or equal to 2 μm, and in step S5, the step of removing the preset layer is further included after the second pre-via hole is formed.
Optionally, in step S4, the material of the preset layer is polyimide, and the step of forming the preset layer includes coating, exposing, developing and curing, so that the first pre-via hole is formed on the preset layer, the first pre-via hole is located vertically above the metal pad, the aperture size of the first pre-via hole is less than or equal to 2 μm, and in step S5, the step of removing the preset layer is further included after the second pre-via hole is formed.
Optionally, the material of the metal pad is one or a combination of two or more of aluminum, copper and gold.
Optionally, the metal layer is a single-layer structure of an Al layer or a stacked-layer structure of a Ti layer and a Cu layer.
Optionally, the polyimide via is formed by dry etching the polyimide layer.
The invention also provides a preparation method of the wafer level semiconductor packaging structure, which comprises the following steps: the method for preparing a polyimide via hole as described in any of the above.
As described above, the preparation method of the polyimide via hole and the wafer level semiconductor package structure of the present invention has the following beneficial effects: the invention avoids the problem that residues exist at the bottom of the small-size polyimide via hole, so that the upper and lower outlines of the polyimide via hole are basically consistent, the preparation process is refined, and the yield of products is improved; in the wafer level semiconductor packaging, the smaller polyimide through hole can make the product design more complicated and more detailed, and greatly improves the chip performance.
Drawings
FIG. 1 shows a schematic structural diagram of a polyimide via hole prepared by a prior art coating method.
FIG. 2 is a schematic structural diagram of a polyimide via exposed by a prior art method for fabricating a via.
FIG. 3 is a schematic diagram showing the structure of a polyimide via developed and cured by a method for preparing a polyimide via according to the prior art.
FIG. 4 is a schematic flow chart of a method for preparing a polyimide via hole according to the present invention.
Fig. 5 is a schematic structural diagram of step S1 of the method for preparing a polyimide via hole according to the present invention.
Fig. 6 is a schematic structural diagram of step S2 of the method for preparing a polyimide via hole according to the present invention.
Fig. 7 is a schematic structural diagram of step S3 of the method for preparing a polyimide via hole according to the present invention.
Fig. 8 is a schematic structural diagram of step S4 of the method for preparing a polyimide via hole according to the present invention.
Fig. 9 is a schematic structural diagram of step S5 of the method for preparing a polyimide via hole according to the present invention.
Fig. 10 is a schematic structural view of step S6 of the method for preparing a polyimide via according to the present invention.
Fig. 11 is a schematic structural view of step S7 of the method for preparing a polyimide via according to the present invention.
Fig. 12 is a schematic structural diagram showing a step S4 of the method for forming a polyimide via hole according to the present invention.
Fig. 13 is a schematic structural diagram of a preset layer formed in the step S4 embodiment of the method for preparing a polyimide via hole of the present invention.
Fig. 14 is a schematic structural diagram of the step S5 of the polyimide via hole preparation method of the present invention, in which the predetermined layer where the first pre-via hole is removed is shown.
Fig. 15 is a schematic structural diagram of a first pre-via formed in a predetermined layer made of polyimide in the specific embodiment of step S4 of the method for preparing a polyimide via hole according to the present invention.
Fig. 16 is a schematic structural diagram showing the formation of a second pre-via based on the first pre-via in fig. 15.
Description of the element reference numerals
10, a substrate; 20, a metal pad; 30, a polyimide layer; 40, a metal layer; 50, presetting a photoresist layer; 60, a preset layer; 71, a first pre-via; 72, second pre-via; 73, a third pre-via; 74, polyimide vias.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one structure or feature's relationship to another structure or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between 8230 \ 8230;" between "means both end points are included.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Polyimide is one of the most important interlayer dielectric materials in the field of semiconductor packaging. As shown in fig. 1 to 3, in the method for preparing a polyimide via according to the prior art, the polyimide via is generally prepared by coating (as shown in fig. 1), exposing (as shown in fig. 2), developing and curing (as shown in fig. 3), and the upper and lower redistribution layers are connected, but the polyimide via profile prepared according to the prior art is greatly changed from top to bottom (as shown in fig. 3), especially, residues exist at the bottom of the via, so that the sizes of the upper and lower profiles of the polyimide via are not consistent, and the yield of the product is not high.
Based on the findings and through research and analysis, the inventor provides a preparation method of a polyimide via hole, so as to solve the problem that residues exist at the bottom of the polyimide via hole, enable the upper and lower outlines of the polyimide via hole to be basically consistent, and enable the preparation process to be fine, thereby improving the yield of products and greatly improving the performance of chips. The method for preparing the polyimide via hole according to the present embodiment is described in detail below with reference to the accompanying drawings.
Example one
As shown in fig. 4 to 11, the present embodiment provides a method for preparing a polyimide via, where the method for preparing a polyimide via includes the following steps:
s1: providing a substrate 10 with a metal pad 20 attached on the surface;
s2: forming a polyimide layer 30 on the substrate 10, wherein the top of the polyimide layer 30 is higher than the metal pad 20;
s3: forming a metal layer 40 on the polyimide layer 30;
s4: forming a preset layer 60 on the metal layer 40, and forming a first pre-via hole 71 on the preset layer, wherein the first pre-via hole 71 is located right above the metal pad 20, and the aperture size of the first pre-via hole 71 is less than or equal to 2 μm;
s5: etching the metal layer 40 to form a second pre-via 72 based on the first pre-via 71;
s6: etching the polyimide layer 30 to form a third pre-via 73 based on the second pre-via 72, the third pre-via 73 being vertically above the metal pad 20 and directly contacting the metal pad 20;
s7: all structures above the polyimide layer 30 are removed to form polyimide vias 74 on the polyimide layer 30.
The problem that residues exist at the bottom of the small-size polyimide via hole 74 is solved, so that the upper and lower outlines of the polyimide via hole 74 are basically consistent, the preparation process is fine, and the yield of products is improved; in the wafer level semiconductor package of the embodiment, the smaller polyimide via 74 can make the product design more complicated and fine, and greatly improve the chip performance.
Referring to fig. 4 to 16, the present embodiment will be further described with reference to the accompanying drawings.
As shown in fig. 4 and 5, as an example, step S1 is first performed to provide the substrate 10 with the metal pad 20 on the surface.
As an example, the substrate 10 is one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, and in this embodiment, a glass layer is preferably used, and the glass layer has a low cost and can reduce the difficulty of a subsequent peeling process. As an example, the material of the metal pad 20 is one or a combination of two or more of aluminum, copper and gold. The thickness of the substrate 10 and the metal pad 20 is not limited in any way, and may be set according to actual needs as long as the above requirements are met.
As shown in fig. 4 and 6, as an example, step S2 is performed to form a polyimide layer 30 on the substrate 10, wherein the top of the polyimide layer 30 is higher than the metal pad 20.
As an example, the step of forming the polyimide layer 30 includes: coating, full exposure and curing. It should be noted that the step of forming the polyimide layer 30 in this embodiment is different from the prior art, in which the polyimide via holes are usually prepared mainly through the steps of coating, exposing, developing and curing, that is, the polyimide via holes are prepared together with the polyimide layer, and the polyimide layer with the polyimide via holes is formed through patterning in the step of exposing, forming a polyimide via prototype, developing and curing. In this embodiment, the polyimide layer 30 is formed by coating polyimide on the substrate 10, exposing the polyimide to light, and curing, wherein the polyimide layer 30 is solid and does not include the polyimide via 74.
As shown in fig. 4 and 7, as an example, a metal layer 40 is formed on the polyimide layer 30 in step S3.
The metal layer 40 is, for example, a single layer structure of an Al layer or a stacked structure of a Ti layer and a Cu layer, and only the stacked structure of the Ti layer and the Cu layer is shown in fig. 7. In this embodiment, the method for forming the metal layer 40 is a sputtering process, and when the metal layer 40 is a single-layer structure of an Al layer, an Al layer is sputtered on the polyimide layer 30; when the metal layer 40 is a laminated structure of a Ti layer and a Cu layer, a Ti layer is sputtered on the polyimide layer 30, and then a Cu layer is sputtered on the polyimide layer to form a laminated metal layer Ti/Cu layer. The Al layer and the Ti/Cu layer are nanoscale metal layers, and the thicknesses of the Al layer and the Ti/Cu layer can be set according to actual needs without limitation. The metal layer 40 is formed in this step, so as to ensure that the aperture range of the etching is not changed during the subsequent small-scale longitudinal etching, and the metal layer 40 is interposed between the polyimide layer 30 and the predetermined layer 60, so as to not adhere to the polyimide layer 30 when the predetermined layer 60 is removed, and to facilitate the removal.
As shown in fig. 4 and fig. 8, as an example, step S4 is performed to form a predetermined layer 60 on the metal layer 40, and form a first pre-via 71 on the predetermined layer 60, where the first pre-via is located right above the metal pad 20, and an aperture size of the first pre-via 71 is smaller than or equal to 2 μm.
The method for forming the preset layer 60 includes one of a plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination molding, spin coating molding and electroplating molding, at this time, the preset layer 60 is made of one of epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass and electroplating metal, and the specific thickness of the preset layer 60 is set according to actual needs, and is not limited herein. The first pre-via hole 71 is located right above the metal pad 20, the position right above the metal pad 20 needs to be preset in advance when the first pre-via hole 71 is prepared, the aperture of the first pre-via hole 71 is the same as that of the finally formed polyimide via hole 74, and the aperture size is smaller than or equal to 2 μm.
As shown in fig. 4 and 9, as an example, step S5 is performed to form a second pre-via 72 on the metal layer 40 based on the first pre-via 71.
The aperture of the second pre-via hole 72 is the same as that of the first pre-via hole 71, that is, the aperture of the finally formed polyimide via hole 74, and the aperture size is less than or equal to 2 μm. The metal layer 40 is a single-layer structure of an Al layer or a laminated structure of a Ti layer and a Cu layer, and when the metal layer 40 is the single-layer structure of the Al layer, the second pre-via hole 72 may be formed by dry etching; when the metal layer 40 is a stacked structure of a Ti layer and a Cu layer, the second pre-via 72 may be formed by etching using a wet process. Dry etching includes all gas types, e.g. O 2 、N 2 、AR、CF 4 、N 2 H 2 Etc., the etching gas is selected mainly according to the substrate to be etched; the solution etched by the wet process comprises degumming liquid containing dimethyl sulfoxide, glycol, N-methyl-2-pyrrolidone and tetramethyl ammonium hydroxide. Both preparation methods can be used for forming the second pre-via 72, and only different forming methods are adopted for different metal layer 40 materials, and the specific forming method can be set according to actual needs, which is not limited herein.
As shown in fig. 4 and 10, as an example, step S6 is performed next, the polyimide layer 30 is etched to form the third pre-via 73 based on the second pre-via 72, and the third pre-via 73 is located vertically above the metal pad 20 and directly contacts the metal pad 20. For example, the first pre-via hole 71, the second pre-via hole 72, and the third pre-via hole 73 are all on the same vertical line, and all have the same aperture, and the size of the aperture is less than or equal to 2 μm. The preparation method of the polyimide via hole in the embodiment mainly aims at the small-sized polyimide via hole 74, so that the product design is more complicated and delicate, the chip performance is greatly improved, and the aperture of the polyimide via hole in the prior art is mostly larger than 2 μm.
By way of example, the method of forming the polyimide via 74 is dry etchingThe polyimide layer 30, the dry etching including all gas types, e.g., O 2 、N 2 、AR、CF 4 、N 2 H 2 And the etching gas is selected mainly according to the substrate to be etched, and can be specifically set according to actual needs without limitation. The dry etching process can reduce the generation of waste water, reduce environmental pollution and is more environment-friendly.
As shown in fig. 4 and fig. 11, as an example, step S7 is finally performed to remove all structures on the polyimide layer 30, so as to form a polyimide via 74 on the polyimide layer 30.
At this time, the structure on the polyimide layer 30 includes the metal layer 40 and the predetermined layer 60, and the predetermined layer 60 may be stripped first, or the predetermined layer 60 may be etched by a dry etching process, and then the metal layer 40 may be etched by a dry etching or wet etching process. The removing method includes, but is not limited to, the above method as long as the removing requirement can be met, and may be specifically set according to an actual need, and is not limited herein.
As shown in fig. 12 to 13, as an example, in step S4, the step of forming the preset layer 60 includes: forming a patterned preset photoresist layer 50 on the metal layer 40, where the preset photoresist layer 50 is located right above the metal pad 20, and the diameter of the preset photoresist layer 50 is less than or equal to 2 μm (as shown in fig. 12); electroplating metal on the metal layer 40 to form the predetermined layer 60, wherein the predetermined layer 60 fills the gap between the predetermined photoresist layers 50, and the predetermined layer 60 is flush with the top of the predetermined photoresist layer 50 (as shown in fig. 13); etching all the predetermined photoresist layer 50, thereby forming the first pre-via hole 71 at the position of the predetermined photoresist layer 50. It should be noted that, the position of the patterned predetermined photoresist layer 50 is also the position of the first pre-via hole 71 formed subsequently, and the patterned predetermined photoresist layer 50 should be cylindrical, and the diameter size of the cylindrical predetermined photoresist layer is completely the same as that of the first pre-via hole 71. The material of the predetermined photoresist layer 50 is one or a combination of two or more of epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the predetermined photoresist layer 50 may be etched away by dry etching. The step of forming the predetermined photoresist layer 50 includes coating, exposing, and developing to form the predetermined photoresist layer 50 having the same predetermined shape as the first pre-via hole 71. The subsequent processes and material types are the same as those in the above steps, and are described in detail, and are not repeated herein.
As shown in fig. 14, as an example, in step S4, the predetermined layer 60 is a photoresist layer, the step of forming the photoresist layer includes coating, exposing, and developing, and etching on the photoresist layer to form the first pre-via hole 71, the first pre-via hole 71 is located right above the metal pad 20, the aperture size of the first pre-via hole 71 is less than or equal to 2 μm, and in step S5, the step of removing the predetermined layer 60 is further included after forming the second pre-via hole 72.
The step of forming the photoresist layer comprises coating, exposing and developing, wherein the photoresist layer is formed firstly, and then the first pre-via hole 71 is formed on the photoresist layer by etching; based on the first pre-via hole 71, the metal layer 40 is etched to form a second pre-via hole 72, the photoresist layer is removed, the photoresist layer is made of one or a combination of more than two of epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and the photoresist layer can be etched by dry etching, so that the removal of the photoresist layer relieves the burden of preparing the polyimide via hole 74 in the step S6, and the problem that the polyimide via hole 74 is not prepared finely enough due to too many structures above the polyimide layer 30 is avoided.
As shown in fig. 15 to 16, as an example, in step S4, the material of the predetermined layer is polyimide, the step of forming the predetermined layer 60 includes coating, exposing, developing and curing, so that the first pre-via hole 71 is formed on the predetermined layer 60 (as shown in fig. 15), the first pre-via hole 71 is located right above the metal pad 20, the aperture size of the first pre-via hole 71 is less than or equal to 2 μm, and in step S5, the step of removing the predetermined layer 60 is further included after the second pre-via hole 72 is formed (as shown in fig. 16).
The step of forming the predetermined layer 60 includes coating, exposing, developing and curing, since the predetermined layer 60 is made of polyimide, and the predetermined layer 60 formed here has the first pre-via 71 formed therein, the substrate and the first pre-via 71 formed by this method will have residues at the bottom to a certain extent, so that the lower profile of the first pre-via 71 is smaller than the upper profile. It should be noted here that the second pre-via 72 is formed by etching the metal layer 40 based on the aperture of the lower profile of the first pre-via 71, the aperture of the lower profile of the first pre-via 71 is the same as the aperture of the second pre-via 72, and the pre-determined layer 60 is removed by dry etching, so that the removal of the pre-determined layer 60 reduces the burden of preparing the polyimide via 74 in step S6, and avoids the problem that the polyimide via 74 is not prepared finely due to too much structure above the polyimide layer 30.
Example two
The embodiment provides a specific embodiment of a method for preparing a polyimide via hole, which includes the following steps:
the substrate 10 with the metal pad 20 attached to the surface is provided, the substrate 10 preferably adopts a glass layer, the cost is low, the difficulty of the subsequent stripping process is reduced, and the material of the metal pad 20 is preferably copper due to cost and conductivity, and becomes a copper pad.
The polyimide layer 30 is formed on the glass layer by coating, full exposure and curing, and the polyimide layer 30 is solid at the moment when the top of the polyimide layer 30 is higher than the copper pad.
A Ti layer is sputtered on the polyimide layer 30 by a sputtering method, and then a Cu layer is sputtered on the Ti/Cu layer to form a laminated structure of Ti/Cu layers.
Forming the preset photoresist layer 50 on the Ti/Cu layer by processes of coating, exposing, developing and the like, wherein the preset photoresist layer 50 is located right above the Ti/Cu layer, the diameter of the preset photoresist layer 50 is 1.8 μm, the position of the preset photoresist layer 50 is also the position of the first pre-via hole 71 later, the shape and the height of the preset photoresist layer 50 are the same as those of the first pre-via hole 71, electroplating metal Cu on the Ti/Cu layer to form an electroplated metal Cu layer, the gap between the preset photoresist layer 50 is filled with the electroplated metal Cu layer, the top of the electroplated metal Cu layer is flush with the top of the preset photoresist layer 50, wrapping the preset photoresist layer 50, and stripping or etching the preset photoresist layer 50 to form the first pre-via hole 71 at the position of the preset photoresist layer 50, and the aperture of the first pre-via hole 71 is 1.8 μm.
And etching the Ti/Cu layer to form a second pre-via hole 72 by adopting a wet etching process based on the first pre-via hole 71, wherein the second pre-via hole 72 and the first pre-via hole 71 have the same aperture size and are both 1.8 mu m.
Based on the second pre-via hole 72, a dry etching process is adopted to etch the polyimide layer 30 to form a third pre-via hole 73, the third pre-via hole 73 is located vertically above the Cu bonding pad and directly contacts with the Cu bonding pad, and the third pre-via hole 73 and the second pre-via hole 72 are also identical in aperture size and are both 1.8 μm.
And removing the residual electroplated metal Cu layer by adopting a dry etching process, and removing the residual Ti/Cu layer by adopting a wet etching process to finally obtain the polyimide via hole 74 on the polyimide layer 30.
EXAMPLE III
The embodiment provides a specific embodiment of a method for preparing a polyimide via hole, which includes the following steps:
the difference between this embodiment and the second embodiment is that the metal layer and the subsequent steps are formed, and the previous step and the second embodiment have already been described, and are not described herein again.
An Al layer is sputtered on the polyimide layer 30 by sputtering, thereby forming a single-layer structure of the Al layer.
Forming a light resistance layer on the Al layer through the processes of coating, exposing, developing and the like, wherein the material of the light resistance layer is epoxy resin, etching the light resistance layer by adopting a dry etching process to form the first pre-via hole 71, the aperture size of the first pre-via hole 71 is 1.8 mu m, and the first pre-via hole 71 is positioned right above the Cu bonding pad vertically.
And etching the Al layer by adopting a dry etching process to form a second pre-via hole 72 based on the first pre-via hole 71, and then etching the residual photoresist layer by adopting the dry etching process. Removing the remaining photoresist layer at this time relieves the burden of preparing the polyimide via 74, and avoids the disadvantage of the polyimide via 74 being prepared with insufficient fineness due to the thick structure above the polyimide layer 30. The second pre-via hole 72 and the first pre-via hole 71 have the same aperture size, which is 1.8 μm.
And etching the polyimide layer 30 by adopting a dry etching process to form a third pre-via hole 73 based on the second pre-via hole 72, wherein the third pre-via hole 73 is positioned vertically above the Cu bonding pad and is in direct contact with the Cu bonding pad. The third pre-via hole 73 and the second pre-via hole 72 have the same aperture size, which is 1.8 μm.
Finally, the remaining Al layer is etched by using a dry etching process, and the polyimide via 74 on the polyimide layer 30 is finally obtained.
All etching processes in the embodiment adopt dry etching, so that the generation of waste water can be reduced, the environmental pollution is reduced, and the method is more environment-friendly.
Example four
The embodiment provides a specific embodiment of a method for preparing a polyimide via hole, which includes the following steps:
the difference between this embodiment and the second embodiment is the step after the metal layer is formed, and the previous step is described in the second embodiment, and is not described herein again.
The predetermined layer 60 is formed on the Ti/Cu layer through processes of coating, exposing, developing, curing and the like, the predetermined layer 60 is made of polyimide, at this time, the first pre-via hole 71 is already formed on the predetermined layer 60, residues exist at the bottom of the substrate and the first pre-via hole 71 formed by the method to a certain extent, so that the lower profile of the first pre-via hole 71 is smaller than the upper profile, the aperture size of the lower profile of the first pre-via hole 71 is 1.8 μm, and the first pre-via hole 71 is located vertically above the Cu pad.
Etching the Ti/Cu layer to form the second pre-via hole 72 by using a wet etching process based on the aperture of the lower profile of the first pre-via hole 71; and then, the residual preset layer 60 made of polyimide is etched by adopting a dry etching process, so that the burden of preparing the polyimide via hole 74 is reduced, and the problem that the polyimide via hole 74 is not prepared finely due to the fact that the structure above the polyimide layer 30 is too thick is avoided. The aperture of the second pre-via hole 72 is the same as the aperture of the lower profile of the first pre-via hole 71, and both are 1.8 μm.
And etching the polyimide layer 30 by adopting a dry etching process to form the third pre-via hole 73 based on the second pre-via hole 72, wherein the third pre-via hole 73 is positioned vertically above the Cu bonding pad and is in direct contact with the Cu bonding pad. The third pre-via hole 73 and the second pre-via hole 72 have the same aperture size, which is 1.8 μm.
And finally, etching the residual Ti/Cu layer by adopting a wet etching process to finally obtain the polyimide via hole 74 on the polyimide layer 30.
EXAMPLE five
The embodiment provides a method for manufacturing a wafer level semiconductor packaging structure, which includes the method for manufacturing a polyimide via hole described in the first embodiment.
In summary, the present invention provides a method for preparing a polyimide via hole, which includes the following steps: s1: providing a substrate with a metal bonding pad attached to the surface; s2: forming a polyimide layer on the substrate, wherein the top of the polyimide layer is higher than the metal pad; s3: forming a metal layer on the polyimide layer; s4: forming a preset layer on the metal layer, and forming a first pre-via hole on the preset layer, wherein the first pre-via hole is positioned right above the metal pad, and the aperture size of the first pre-via hole is less than or equal to 2 microns; s5: etching the metal layer to form a second pre-via hole based on the first pre-via hole; s6: etching the polyimide layer to form a third pre-via hole based on the second pre-via hole, wherein the third pre-via hole is positioned vertically above the metal pad and directly contacts with the metal pad; s7: and removing all structures above the polyimide layer to form a polyimide through hole on the polyimide layer. The invention avoids the problem that residues exist at the bottom of the small-size polyimide via hole, so that the upper and lower outlines of the polyimide via hole are basically consistent, the preparation process is refined, and the yield of products is improved; in the wafer level semiconductor packaging, the smaller polyimide through hole can make the product design more complex and delicate, and greatly improve the chip performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (9)
1. A preparation method of a polyimide via hole is characterized by comprising the following steps:
s1: providing a substrate with a metal bonding pad attached to the surface;
s2: forming a polyimide layer on the substrate, the polyimide layer having a top higher than the metal pad, the forming the polyimide layer comprising: coating, full exposure and curing;
s3: forming a metal layer on the polyimide layer;
s4: forming a preset layer on the metal layer, and forming a first pre-via hole on the preset layer, wherein the first pre-via hole is positioned vertically above the metal pad, and the aperture size of the first pre-via hole is less than or equal to 2 μm;
s5: etching the metal layer to form a second pre-via hole based on the first pre-via hole;
s6: etching the polyimide layer to form a third pre-via hole based on the second pre-via hole, wherein the third pre-via hole is positioned vertically above the metal pad and is in direct contact with the metal pad;
s7: and removing all structures above the polyimide layer to form a polyimide through hole on the polyimide layer.
2. The method of preparing a polyimide via according to claim 1, wherein: the first pre-via hole, the second pre-via hole and the third pre-via hole have the same aperture size.
3. The method of preparing a polyimide via according to claim 1, wherein: in step S4, the step of forming the preset layer includes: forming a patterned preset light resistance layer on the metal layer, wherein the preset light resistance layer is positioned right above the metal bonding pad, and the diameter size of the preset light resistance layer is less than or equal to 2 mu m; electroplating metal on the metal layer to form the preset layer, wherein the preset layer fills gaps among the preset photoresist layers and is flush with the tops of the preset photoresist layers; and etching all the preset photoresist layer, thereby forming the first pre-via hole at the position of the preset photoresist layer.
4. The method of preparing a polyimide via according to claim 1, wherein: in step S4, the preset layer is a photoresist layer, the step of forming the preset layer includes coating, exposing, and developing, and etching the preset layer to form the first pre-via hole, and in step S5, the step of removing the preset layer is further included after the second pre-via hole is formed.
5. The method of preparing a polyimide via according to claim 1, wherein: in step S4, the preset layer is made of polyimide, the step of forming the preset layer includes coating, exposing, developing and curing, so that the first pre-via hole is formed in the preset layer, and in step S5, the step of removing the preset layer is further included after the second pre-via hole is formed.
6. The method of preparing a polyimide via according to claim 1, wherein: the metal bonding pad is made of one or a combination of more than two of aluminum, copper and gold.
7. The method of preparing a polyimide via according to claim 1, wherein: the metal layer is of a single-layer structure of an Al layer or a laminated structure of a Ti layer and a Cu layer.
8. The method of preparing a polyimide via according to claim 1, wherein: the method of forming the polyimide via is dry etching the polyimide layer.
9. A preparation method of a wafer level semiconductor packaging structure is characterized by comprising the following steps: the method for preparing the polyimide via hole as claimed in any one of claims 1 to 8.
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| CN202211068622.9A CN115132591B (en) | 2022-09-02 | 2022-09-02 | Preparation method of polyimide via hole and wafer level semiconductor packaging structure |
| PCT/CN2023/097808 WO2024045732A1 (en) | 2022-09-02 | 2023-06-01 | Preparation method for polyimide via and wafer level semiconductor packaging structure |
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| CN202211068622.9A CN115132591B (en) | 2022-09-02 | 2022-09-02 | Preparation method of polyimide via hole and wafer level semiconductor packaging structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1089369A (en) * | 1992-11-18 | 1994-07-13 | 三星电子株式会社 | Adopt silylation to form the method for figure |
| CN1427458A (en) * | 2001-12-17 | 2003-07-02 | 三菱电机株式会社 | Method for mfg. semiconductor device |
| CN103035512A (en) * | 2012-11-02 | 2013-04-10 | 上海华虹Nec电子有限公司 | Production method of non-photosensitive polyimide passivation layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2137808A (en) * | 1983-04-06 | 1984-10-10 | Plessey Co Plc | Integrated circuit processing method |
| JPH0821782B2 (en) * | 1992-03-30 | 1996-03-04 | 日本碍子株式会社 | Method for forming multilayer circuit board |
| CN101566799B (en) * | 2008-04-23 | 2011-09-21 | 中国科学院微电子研究所 | Method for preparing hollowed-out polyimide evaporation shadow mask |
| CN103137469B (en) * | 2011-11-22 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | A kind of manufacture method of non-photosensitive polyimide passivation layer |
| CN111952169A (en) * | 2020-08-21 | 2020-11-17 | 北京北方华创微电子装备有限公司 | Polyimide etching method |
| CN115132591B (en) * | 2022-09-02 | 2022-11-29 | 盛合晶微半导体(江阴)有限公司 | Preparation method of polyimide via hole and wafer level semiconductor packaging structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1089369A (en) * | 1992-11-18 | 1994-07-13 | 三星电子株式会社 | Adopt silylation to form the method for figure |
| CN1427458A (en) * | 2001-12-17 | 2003-07-02 | 三菱电机株式会社 | Method for mfg. semiconductor device |
| CN103035512A (en) * | 2012-11-02 | 2013-04-10 | 上海华虹Nec电子有限公司 | Production method of non-photosensitive polyimide passivation layer |
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