CN115132245A - Addressing device of cascade front-end controller and uplink transmission power determining method - Google Patents

Addressing device of cascade front-end controller and uplink transmission power determining method Download PDF

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Publication number
CN115132245A
CN115132245A CN202110336585.4A CN202110336585A CN115132245A CN 115132245 A CN115132245 A CN 115132245A CN 202110336585 A CN202110336585 A CN 202110336585A CN 115132245 A CN115132245 A CN 115132245A
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connector
end controller
pins
cascade
kth
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王俊
王根
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Fulian Guoji Shanghai Electronics Co ltd
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Fulian Guoji Shanghai Electronics Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Programmable Controllers (AREA)

Abstract

The addressing device of the cascade front-end controller comprises: the PLC comprises a first connector, wherein the first connector comprises N cascade pins; the system comprises N front-end controllers, each front-end controller comprises a second connector and a third connector, the second connector comprises N cascade pins, and the third connector comprises N-1 cascade pins; n cascade pins of a second connector of the Nth front-end controller are connected with N cascade pins of a first connector of the PLC, and N-1 cascade pins of a third connector of the Nth front-end controller are connected with second to Nth cascade pins of the second connector; the 1 st to the Kth cascade pins of the second connector of the Kth front-end controller are connected with the 1 st to the Kth cascade pins of the third connector of the front-end controller at the upper stage; the 1 st to K-1 st cascade pins of the third connector of the Kth front-end controller are connected to the 1 st to K-1 st cascade pins of the second connector of the front-end controller of the next stage, so that unique address pins of the front-end controller are defined.

Description

Addressing device of cascade front-end controller and uplink transmission power determining method
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an addressing apparatus for a cascade front-end controller and an uplink power determination method.
Background
In the industrial control field, for the AD/DA terminal control with low delay, fast response and large data volume, plc (programmable Logic controller) often uses Ethernet or Ethernet cat to exchange data and control commands with a front-end controller. The front-end controller collects data and controls behaviors with the AD/DA terminal through protocols such as RS485/RS 232. Based on the application premise mainly based on data acquisition, the advantages of high speed and bandwidth of Ethernet or EtherCat cannot be maximized, so that a simpler and more cost-effective alternative scheme is needed.
Disclosure of Invention
In view of the above, there is a need to provide an addressing apparatus for cascaded front-end controllers, which can clarify the unique address pins of each front-end controller, and even if the positions of the front-end controllers are arbitrarily exchanged, the conflict and contradiction of CS signals of the old and new position controllers will not be caused.
An addressing apparatus of a cascade front-end controller according to an embodiment of the present invention includes:
the PLC comprises a first connector, wherein the first connector comprises N cascade pins and is used for cascading the extended front-end controller, and N > is 1;
the system comprises N front-end controllers, each front-end controller comprises a second connector and a third connector, the second connector comprises N cascade pins, and the third connector comprises N-1 cascade pins;
n cascade pins of a second connector of an Nth front-end controller are respectively connected with N cascade pins of a first connector of the PLC in a one-to-one correspondence manner, and N-1 cascade pins of a third connector of the Nth front-end controller are respectively connected with second to Nth cascade pins of the second connector in a one-to-one correspondence manner;
the 1 st to Kth cascade pins of the second connector of the Kth front-end controller are connected with the 1 st to Kth cascade pins of the third connector of the front-end controller at the upper stage; the 1 st to the K-1 st cascade pins of the third connector of the Kth front-end controller are electrically connected with the 1 st to the K-1 st cascade pins of the second connector of the front-end controller of the next stage; the 2 nd to the K-1 th cascade pins of the second connector of the Kth front-end controller are electrically connected to the 1 st to the K-1 th cascade pins of the third connector of the Kth front-end controller, wherein 1< ═ K < N.
Preferably, the first cascade pin of the second connector of each front-end controller is grounded.
Preferably, the second connector of each front-end controller further includes N detection pins, and the third connector further includes N-1 detection pins;
n detection pins of a second connector of an Nth front-end controller are respectively connected with N detection pins of a first connector of the PLC in a one-to-one correspondence manner, and N-1 detection pins of a third connector of the Nth front-end controller are respectively connected with second to Nth detection pins of the second connector in a one-to-one correspondence manner;
the 1 st to Kth detection pins of the second connector of the Kth front-end controller are connected with the 1 st to Kth detection pins of the third connector of the front-end controller at the upper stage; the 1 st to the K-1 st detection pins of the third connector of the Kth front-end controller are electrically connected with the 1 st to the K-1 st detection pins of the second connector of the front-end controller of the next stage; the 2 nd to the K-1 th detection pins of the second connector of the Kth front-end controller are electrically connected to the 1 st to the K-1 th detection pins of the third connector of the Kth front-end controller, wherein 1< ═ K < N.
Preferably, the first detection pin of the second connector of each front-end controller is grounded.
Preferably, the initial state of the cascade pin and the detection pin of the first connector of the PLC is a high level, and the initial state of the first cascade pin and the first detection pin of the second connector of each front-end controller is a low level.
Preferably, when a detection pin of the first connector of the PLC is at a low level, it represents that a front-end controller is accessed; when a detection pin of a first connector of the PLC is at a high level, no front-end controller is accessed.
Preferably, when the cascade pin of the first connector of the PLC is at a low level, it represents that the front-end controller is available; and when the cascade pin of the first connector of the PLC is in a high level, the front-end controller is not available.
Preferably, when the PLC detects that the level of the detection pin is a low level and the level of the corresponding cascade pin is a high level, it determines that the current front-end controller has a fault.
Preferably, each front-end controller further comprises a fourth connector for connecting an external analog-to-digital conversion device or a digital-to-analog conversion device.
Compared with the prior art, the addressing device of the cascade front-end controller and the uplink power determining method provided by the embodiment of the invention have the advantages that N front-end controllers are connected in a staggered manner through the second connector and the third connector to realize cascade connection, so that the unique address pins of each front-end controller are clear, and the conflict and contradiction of CS signals of new and old position controllers can not be caused even if the positions of the front-end controllers are arbitrarily exchanged.
Drawings
Fig. 1 is a block diagram of an addressing apparatus of a cascaded front-end controller according to an embodiment of the present invention.
Fig. 2 is a block diagram of an addressing apparatus of a cascaded front-end controller according to an embodiment of the present invention.
Description of the main Components
Addressing device 10 for cascaded front-end controllers
PLC 100
Front end controller 101
First connector 1001
Second connector 1011
Third connector 1012
Cascade pin CS0-CS3
Detection pins ADD0-ADD3
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic structural diagram of an addressing device 10 of a cascaded front-end controller according to an embodiment of the present invention. In this embodiment, the addressing device 10 of the cascade front-end controller includes a PLC 100 and N front-end controllers 101 to realize cascade expansion.
In this embodiment, the PLC 100 includes a first connector 1001, and the first connector 1001 includes N cascade pins for cascading the extended front-end controller, where N > 1. N front-end controllers 101, each front-end controller 101 comprises a second connector 1011 and a third connector 1012, the second connector 1011 comprises N cascade pins, and the third connector 1012 comprises N-1 cascade pins.
In this embodiment, N cascade pins of the second connector 1011 of the nth front-end controller 101 are connected to N cascade pins of the first connector 1001 of the PLC in a one-to-one correspondence, and N-1 cascade pins of the third connector 1012 of the nth front-end controller 101 are connected to second to nth cascade pins of the second connector 1011 in a one-to-one correspondence. The 1 st to kth cascade pins of the second connector 1011 of the kth front-end controller 101 are connected to the 1 st to kth cascade pins of the third connector 1012 of the front-end controller 101 at the upper stage; the 1 st to K-1 st cascade pins of the third connector 1012 of the Kth front-end controller 101 are electrically connected to the 1 st to K-1 st cascade pins of the second connector 1011 of the next-stage front-end controller 101; the 2 nd to K-1 th cascade pins of the second connector 1011 of the kth front-end controller 101 are electrically connected to the 1 st to K-1 th cascade pins of the third connector 1012 of the kth front-end controller 101, where 1< ═ K < N. The first cascade pin of the second connector 1011 of each front end controller 101 is connected to ground.
In this embodiment, the second connector 1011 of each front-end controller 101 further includes N detection pins, and the third connector 1012 further includes N-1 detection pins;
n detection pins of the second connector 1011 of the nth front-end controller 101 are connected to N detection pins of the first connector 1001 of the PLC in a one-to-one correspondence, and N-1 detection pins of the third connector 1012 of the nth front-end controller 101 are connected to second to nth detection pins of the second connector 1011 in a one-to-one correspondence. The 1 st to kth detection pins of the second connector 1011 of the kth front-end controller 101 are connected to the 1 st to kth detection pins of the third connector 1012 of the front-end controller 101 at the upper stage; the 1 st to K-1 st detection pins of the third connector 1012 of the Kth front end controller 101 are electrically connected to the 1 st to K-1 st detection pins of the second connector 1011 of the next front end controller 101; the 2 nd to K-1 th detection pins of the second connector 1011 of the kth front-end controller 101 are electrically connected to the 1 st to K-1 th detection pins of the third connector 1012 of the kth front-end controller 101, wherein 1< ═ K < N. The first detection pin of the second connector 1011 of each front-end controller 101 is grounded.
In this embodiment, the initial state of the cascade pin and the detect pin of the first connector 1001 of the PLC 100 is at a high level, and the initial state of the first cascade pin and the first detect pin of the second connector 1011 of each front-end controller is at a low level. When the detection pin of the first connector 1001 of the PLC 100 is at a low level, it represents that a front-end controller is accessed; when the pin of the detection pin of the first connector 1001 of the PLC 100 is at a high level, it means that no front-end controller is connected.
In this embodiment, when the cascade pin of the first connector 1001 of the PLC 100 is at a low level, it represents that the front-end controller is available; when the cascade pin of the first connector 1001 of the PLC 100 is high, it represents that the front-end controller is not available. When the PLC 100 detects that the level of the detection pin of the first connector 1001 is low and the level of the corresponding cascade pin is high, it determines that the current front-end controller has a fault.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the addressing device 10 of the cascaded front-end director according to the present invention. In the present embodiment, 4 front-end controllers (front-end controller 1, front-end controller 2, front-end controller 3, and front-end controller 4) are taken as an example for description, but not limited thereto, and the number of front-end controllers to be cascaded and expanded may be determined according to actual application requirements.
As shown in fig. 2, the cascade pins CS0-CS3 of the first connector 1001 of the PLC 100 are connected to the cascade pins CS0-CS3 of the second connector 1011 of the front-end controller 4 in a one-to-one correspondence, respectively. The cascade pins CS1-CS3 of the second connector 1011 of the front-end controller 4 are connected with the CS1-CS3 of the third connector 1012 in a one-to-one correspondence, and the cascade pin CS0 of the second connector 1011 of the front-end controller 4 is grounded, so that the staggered connection is realized. The cascade pins CS1-CS3 of the third connector 1012 of the front-end controller 4 are connected with the cascade pins CS0-CS2 of the second connector of the front-end controller 3 in a one-to-one correspondence, the CS1-CS2 of the second connector 1011 of the front-end controller 3 is connected with the CS1-CS2 of the third connector 1012 in a one-to-one correspondence, meanwhile, the cascade pins CS1-CS2 of the front-end controller 3 are connected with the cascade pins CS0-CS1 of the second connector 1011 of the front-end controller 2 of the next stage in a one-to-one correspondence, and so on, when the CS signal of the front-end controller 1 reaches the end of the PLC 100, the CS signal is defined at the CS3 pin of the PLC 100, so that the unique address pin of each front-end controller is defined, and collision and contradiction of CS signals of new and old position controllers are not caused even if the positions of each front-end controller are arbitrarily exchanged.
When the cascade pin of the first connector 1001 of the PLC 100 is at a low level, it represents that the front-end controller is available; when the cascade pin of the first connector 1001 of the PLC 100 is at a high level, it represents that the front-end controller is not available, and as shown in table 1, when the number of the front-end controllers is 4, the following address code table can be obtained:
TABLE 1
Figure BDA0002997932330000071
The PLC 100 can accurately and unmistakably exchange data with its intended front-end controller only by putting an address code into the SPI protocol, regardless of the replacement of the front-end controller.
The PLC 100 is connected to the detection pins of the front-end controller in a manner similar to the cascade pins, and will not be described herein again.
When the detection pin of the first connector 1001 of the PLC 100 is at a low level, it represents that a front-end controller is accessed; when the pin of the detection pin of the first connector 1001 of the PLC 100 is at a high level, it means that no front-end controller is connected. As shown in table 2, when the number of front-end controllers is 4, the following address code table can be obtained:
TABLE 2
Figure BDA0002997932330000081
From the above table, when the PLC detects that both ADD0 and CS0 pin are 0, it can clip the front-end controller 4 through 1110 and perform data exchange.
Compared with the prior art, according to the addressing device of the cascade front-end controller and the uplink power determining method provided by the embodiment of the invention, N front-end controllers are connected in a staggered manner through the second connector and the third connector to realize cascade connection, so that the unique address pins of each front-end controller are determined, and the conflict and contradiction of CS signals of new and old position controllers can not be caused even if the positions of the front-end controllers are randomly exchanged.
It will be appreciated by those skilled in the art that the above embodiments are only for illustrating the present invention and are not to be used as a limitation of the present invention, and that suitable modifications and variations of the above embodiments are within the scope of the present invention as claimed in the appended claims, as long as they fall within the true spirit of the present invention.

Claims (9)

1. An addressing mechanism for a cascaded front-end director, comprising:
the PLC comprises a first connector, wherein the first connector comprises N cascade pins and is used for cascading the extended front-end controller, and N > is 1;
the system comprises N front-end controllers, each front-end controller comprises a second connector and a third connector, the second connector comprises N cascade pins, and the third connector comprises N-1 cascade pins;
n cascade pins of a second connector of an Nth front-end controller are respectively connected with N cascade pins of a first connector of the PLC in a one-to-one correspondence manner, and N-1 cascade pins of a third connector of the Nth front-end controller are respectively connected with second to Nth cascade pins of the second connector in a one-to-one correspondence manner;
the 1 st to Kth cascade pins of the second connector of the Kth front-end controller are connected with the 1 st to Kth cascade pins of the third connector of the front-end controller at the upper stage; the 1 st to the K-1 st cascade pins of the third connector of the Kth front-end controller are electrically connected to the 1 st to the K-1 st cascade pins of the second connector of the front-end controller of the next stage; the 2 nd to the K-1 th cascade pins of the second connector of the Kth front-end controller are electrically connected with the 1 st to the K-1 st cascade pins of the third connector of the Kth front-end controller, wherein 1< K < N.
2. The addressing mechanism for a cascaded front-end controller as recited in claim 1, wherein:
the first cascade pin of the second connector of each front-end controller is grounded.
3. The addressing mechanism for cascaded front-end directors of claim 2, wherein said second connector of each front-end director further comprises N sense pins, and said third connector further comprises N-1 sense pins;
n detection pins of a second connector of the Nth front-end controller are respectively connected with N detection pins of a first connector of the PLC in a one-to-one correspondence manner, and N-1 detection pins of a third connector of the Nth front-end controller are respectively connected with second to Nth detection pins of the second connector in a one-to-one correspondence manner;
the 1 st to Kth detection pins of the second connector of the Kth front-end controller are connected with the 1 st to Kth detection pins of the third connector of the front-end controller at the upper stage; the 1 st to the K-1 st detection pins of the third connector of the Kth front-end controller are electrically connected with the 1 st to the K-1 st detection pins of the second connector of the front-end controller of the next stage; the 2 nd to the K-1 th detection pins of the second connector of the Kth front-end controller are electrically connected to the 1 st to the K-1 th detection pins of the third connector of the Kth front-end controller, wherein 1< ═ K < N.
4. The addressing mechanism for a cascaded front-end director of claim 3, wherein:
the first detection pin of the second connector of each front-end controller is grounded.
5. The addressing mechanism for a cascaded front-end director of claim 4, wherein:
the initial state of the cascade pin and the detection pin of the first connector of the PLC is high level, and the initial state of the first cascade pin and the first detection pin of the second connector of each front-end controller is low level.
6. The addressing mechanism of claim 5, wherein the detection pin of the first connector of the PLC is low, indicating that the front-end controller is connected; when a detection pin of a first connector of the PLC is at a high level, no front-end controller is accessed.
7. The apparatus as claimed in claim 6, wherein the cascade pin of the first connector of the PLC is low, indicating that the front-end controller is available; and when the cascade pin of the first connector of the PLC is in a high level, the front-end controller is not available.
8. The addressing mechanism as recited in claim 7, wherein when the PLC detects that the level of the detection pin is low and the level of the corresponding cascade pin is high, it determines that the current front-end controller is faulty.
9. The addressing mechanism for cascaded front-end directors of any one of claims 1-8, wherein each front-end director further comprises a fourth connector for connecting an external analog-to-digital conversion mechanism or digital-to-analog conversion mechanism.
CN202110336585.4A 2021-03-29 2021-03-29 Addressing device of cascade front-end controller and uplink transmission power determining method Pending CN115132245A (en)

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