CN115118137A - Pulse distribution device and method - Google Patents

Pulse distribution device and method Download PDF

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Publication number
CN115118137A
CN115118137A CN202210747919.1A CN202210747919A CN115118137A CN 115118137 A CN115118137 A CN 115118137A CN 202210747919 A CN202210747919 A CN 202210747919A CN 115118137 A CN115118137 A CN 115118137A
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China
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signal
target
pwm pulse
pulse signal
pulse
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CN202210747919.1A
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Chinese (zh)
Inventor
都日苏拉
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Beijing Runke General Technology Co Ltd
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Beijing Runke General Technology Co Ltd
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Priority to CN202210747919.1A priority Critical patent/CN115118137A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The embodiment of the invention discloses a pulse distribution device and a method, wherein the pulse distribution device comprises a pulse distribution module, a pulse distribution module and a pulse distribution module, wherein the pulse distribution module is used for distributing a path of PWM pulse signals which have the same phase and period as the pulse synchronization signals and are output simultaneously to target channels in N channels when the target edge state of the pulse synchronization signals is detected; the direct connection prevention module is used for obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronizing signal are output by the PWM pulse signal sending source in response to the enabling signal. The reliability of the PWM control is improved.

Description

Pulse distribution device and method
Technical Field
The present invention relates to the field of control technologies, and in particular, to a pulse distribution apparatus and method.
Background
In some control scenarios, a load (such as a motor, etc.) is PWM (Pulse Width Modulation) controlled by a multiphase bridge, where the multiphase bridge is formed by connecting multiple bridge arms in parallel, each bridge arm is formed by connecting two power transistors in series, and two power transistors in each bridge arm form an upper tube and a lower tube of the bridge arm. In a specific application scene, one half of bridge arms of a multi-phase bridge are connected with an input end of a load, the other half of bridge arms of the multi-phase bridge are connected with an output end of the load, an upper power tube of one bridge arm connected with the input end of the load and a lower power tube of the other bridge arm connected with the output end of the load form a group of power tubes, therefore, the load can be connected with a plurality of groups of power tubes, and the load is controlled through the multi-phase bridge in a mode that PWM pulse signals are sequentially sent to the groups of power tubes connected with the load in a time-sharing mode, so that only one group of power tubes are conducted at the same time, and the control of the load is realized.
In the existing bridge arm control, a Micro Controller Unit (MCU) sequentially sends PWM pulse signals to power tube groups corresponding to pins through the pins to implement PWM control, and because the pulse synchronization of the pins of the MCU is poor, the power tubes cannot be guaranteed to be turned on or turned off at the same time, which is poor in reliability.
Disclosure of Invention
The invention aims to provide a pulse distribution device and a pulse distribution method so as to improve the reliability of PWM control. The technical scheme is as follows:
a pulse distribution device comprising:
the pulse distribution module is used for distributing a path of PWM pulse signals which have the same phase and period with the pulse synchronization signals and are output simultaneously to a target channel in N channels when the target edge state of the pulse synchronization signals is detected; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and the direct connection prevention module is used for acquiring the reverse phase signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the reverse phase signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
The above apparatus, optionally, the pulse allocation module includes:
the edge detection submodule is used for carrying out target edge state detection on the pulse synchronization signal;
and the channel distribution submodule is used for conducting a target channel in the N channels of the controllable switch according to a preset control sequence when the edge detection submodule detects the target edge state of the pulse synchronization signal so as to distribute the PWM pulse signal to the target channel.
The above apparatus, optionally, the pulse distribution module further includes:
a channel configuration submodule, configured to determine, in the controllable switch, a target number of available channels and a control order of the target number of available channels when the target number is obtained;
the first channel belongs to the target number of available channels.
The above apparatus, optionally, the channel configuration submodule includes: the dial switch and the first configuration unit; wherein,
the first configuration unit is used for determining a binary code through the state of each key of the dial switch;
and the decimal number corresponding to the binary code is the target number.
The above apparatus, optionally, the channel configuration submodule includes: the field programmable gate array chip and the second configuration unit; wherein,
the second configuration unit is used for determining a binary code through the level of each target pin of the field programmable gate array chip; the level of the target pin is related to the position of a target resistor in an external circuit of the target pin;
and the decimal number corresponding to the binary code is the target number.
The above apparatus, optionally, the anti-shoot-through module includes:
the negation submodule is used for negating the path of PWM pulse signal to obtain an inverted signal of the path of PWM pulse signal;
the output submodule is used for judging whether an inverted signal of the PWM pulse signal is in a high level or not; if the judgment result is negative, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverted signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
The above apparatus, optionally, further comprises:
the interference filtering module is used for respectively carrying out low-pass filtering processing on the pulse synchronization signal and the one path of PWM pulse signal;
the pulse distribution module is specifically configured to, when a target edge state of the pulse synchronization signal after the low-pass filtering is detected, distribute the PWM pulse signal after the low-pass filtering to a target channel of the N channels.
Optionally, in the apparatus, the target edge state is a rising edge; alternatively, the target edge state is a falling edge.
Optionally, the device may only allocate the one path of PWM pulse signal to one of the N channels at the same time.
A method of pulse allocation comprising:
when the target edge state of the pulse synchronization signal is detected, distributing a path of PWM pulse signal which has the same phase and period with the pulse synchronization signal and is output simultaneously to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
According to the scheme, the pulse distribution device comprises a pulse distribution module, a pulse distribution module and a pulse distribution module, wherein the pulse distribution module is used for distributing one path of PWM pulse signals which have the same phase and period as the pulse synchronization signals and are output simultaneously to target channels in N channels when the target edge state of the pulse synchronization signals is detected; the direct connection prevention module is used for obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the PWM pulse signal and the pulse synchronizing signal are output by the PWM pulse signal sending source in response to the enabling signal. In the invention, each pin of the MCU does not output a PWM pulse signal respectively, but only the PWM pulse signal transmitting source outputs one path of PWM pulse signal, and the same PWM pulse signal is triggered by the pulse synchronization signal to be distributed to different power tube groups, thereby improving the pulse synchronization of the PWM pulse signals received by different power tube groups and further improving the reliability of PWM control.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is an exemplary diagram of a multiphase bridge provided by an embodiment of the present invention;
FIG. 2 is a diagram illustrating an exemplary structure of a pulse distribution apparatus according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an example of a pulse synchronization signal and a PWM pulse signal having the same phase and period according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pulse allocation module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a pulse allocation module according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a channel configuration submodule according to an embodiment of the present invention;
fig. 7 is another schematic structural diagram of a channel configuration submodule according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a direct connection preventing module according to an embodiment of the present invention;
fig. 9 is another schematic structural diagram of a pulse distribution apparatus according to an embodiment of the present invention;
FIG. 10 is a timing diagram illustrating sequential output of PWM pulse signals to four groups of power transistors in a multiphase bridge, in accordance with embodiments of the present invention;
FIG. 11 is a flow chart of an implementation of a pulse allocation method according to an embodiment of the present invention;
fig. 12 is a block diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated herein.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, an exemplary diagram of a multiphase bridge (also referred to as an inverter bridge, inverter, etc.) according to an embodiment of the present invention is shown. In the case of the example shown in the figure,
the power tubes in the same column form a bridge arm, and it is obvious that the multiphase bridge shown in fig. 1 has 6 bridge arms, for convenience of description and distinction, the bridge arms are sequentially numbered from left to right as 1 to 6, for example, the power tube T11 and the power tube T21 form a bridge arm No. 1, where the power tube T11 is an upper tube of the bridge arm No. 1, the power tube T21 is a lower tube of the bridge arm No. 1, and for example, the power tube T13 and the power tube T23 form a bridge arm No. 3, where the power tube T13 is an upper tube of the bridge arm No. 3, and the power tube T23 is a lower tube of the bridge arm No. 3, and so on, the upper tube and the lower tube of each bridge arm can be determined.
Based on the multiphase bridge shown in fig. 1, when a load (such as a motor) needs to be controlled, only the upper tube of one bridge arm and the lower tube of the other bridge arm can be in an on state at the same time, and the other power tubes are in an off state. For example, when the power transistor T11 and the power transistor T24 are simultaneously turned on, the other power transistors are in an off state, when the power transistor T12 and the power transistor T25 are simultaneously turned on, the other power transistors are in an off state, and when the power transistor T13 and the power transistor T26 are simultaneously turned on, the other power transistors are in an off state.
Referring to fig. 2, an exemplary diagram of a pulse distribution apparatus according to an embodiment of the present invention includes: a pulse distribution module 201 and a straight-through prevention module 202; wherein,
the pulse distribution module 201 is configured to, when a target edge state of the pulse synchronization signal is detected, distribute one path of PWM pulse signal, which has the same phase and period as the pulse synchronization signal and is output simultaneously, to a target channel of the N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is an integer greater than 1; the PWM pulse signal and the pulse synchronizing signal are output by a PWM pulse signal sending source in response to an enabling signal; and when the target edge state of the pulse synchronization signal is detected at different times, distributing the one-path PWM pulse signal to different channels of the N channels.
In the embodiment of the present invention, the PWM pulse signal transmission source generates not only the PWM pulse signal but also a pulse synchronization signal having the same phase and period as the PWM pulse signal, and the PWM pulse signal transmission source simultaneously outputs the PWM pulse signal and the pulse synchronization signal. The PWM pulse signal only needs to generate one path, and a plurality of paths of PWM pulse signals do not need to be generated.
In the embodiment of the present invention, the PWM pulse signal transmission source may output PWM pulse signals with various duty ratios, and the specific output duty ratio of the PWM pulse signal is determined according to the actual application scenario, which is not described in detail herein. Whether the PWM pulse signal transmission source outputs the PWM pulse signal and the pulse synchronization signal may be controlled by the upper computer, that is, the upper computer may transmit an enable signal to the PWM pulse signal transmission source to trigger the PWM pulse signal transmission source to output the PWM pulse signal and the pulse synchronization signal, and further, the upper computer may transmit a stop signal to the PWM pulse signal transmission source to trigger the PWM pulse signal transmission source to stop outputting the PWM pulse signal and the pulse synchronization signal. The upper computer may transmit an enable signal or a stop signal to the PWM pulse signal transmission source in response to a user operation.
As shown in fig. 3, an exemplary diagram of a pulse synchronizing signal and a PWM pulse signal having the same phase and period is provided for the embodiment of the present invention, in which the duty ratio of the PWM pulse signal output by the PWM pulse signal transmission source is varied. However, the PWM pulse signal and the pulse synchronization signal have the same phase and period and are output simultaneously regardless of the variation. Of course, the duty ratio of the PWM pulse signal output by the PWM pulse signal transmission source may be constant. The duty ratio of the PWM pulse signal may be any duty ratio in the range of 0% to% 100.
In fig. 3, the duty ratio of the pulse synchronization signal is 50%, and in the present invention, the duty ratio of the pulse synchronization signal may also be other values, which is not limited in the present invention.
In the embodiment of the present invention, N channels are configured in the pulse allocating module 201, and when detecting a target edge state of the pulse synchronization signal output by the pulse allocating module 201, the pulse allocating module 201 allocates one channel of the PWM pulse signal, which has the same phase and period as the pulse synchronization signal and is output simultaneously, to one channel (for convenience of description and distinction, it is referred to as a target channel) of the N channels. When the target edge state of the pulse synchronization signal is detected at different times, the pulse allocation module 201 allocates the one path of PWM pulse signal to different channels of the N channels. Different channels of the N channels correspond to different groups of power tubes of the N groups of power tubes connected with the load in the multiphase bridge, namely one channel of the N channels corresponds to one group of power tubes of the N groups of power tubes. And only distributing the one path of PWM pulse signal to one channel of the N channels at the same time.
Each group of N groups of power tubes comprises an upper tube of a first bridge arm and a lower tube of a second bridge arm; the first bridge arm is different from the second bridge arm, the first bridge arm is connected with a first end of a load, and the second bridge arm is connected with a second end of the load; the first end and the second end of the load are both connected with at least two bridge arms, and the power tubes of different groups of power tubes are different.
Taking the multiphase bridge shown in fig. 1 as an example, there may be multiple power tube grouping methods, but regardless of the grouping manner, it is to be ensured that one power tube in each group of power tubes belongs to the bridge arm (for convenience of description and distinction, it is denoted as a first bridge arm) connected to the first end of the load, and the other power tube belongs to the bridge arm (for convenience of description and distinction, it is denoted as a second bridge arm) connected to the second end of the load, and the first bridge arm and the second bridge arm are different.
For example, power transistors T11 and T24 may be grouped together, power transistors T12 and T25 may be grouped together, and power transistors T13 and T26 may be grouped together.
For another example, power transistors T11 and T25 may be grouped together, power transistors T12 and T26 may be grouped together, and power transistors T13 and T24 may be grouped together.
For another example, power transistors T11 and T26 may be grouped together, power transistors T12 and T25 may be grouped together, and power transistors T13 and T24 may be grouped together.
In the above grouping manner, only the grouping case of half of the power transistors (for convenience of description and distinction, they are referred to as the first part of power transistors) is described, and the other half of the power transistors (for convenience of description and distinction, they are referred to as the first part of power transistors) may also be grouped according to the same principle.
For example, power transistors T14 and T21 may be grouped together, power transistors T15 and T22 may be grouped together, and power transistors T16 and T23 may be grouped together.
For another example, power transistors T15 and T21 may be grouped together, power transistors T16 and T22 may be grouped together, and power transistors T14 and T23 may be grouped together.
For another example, power transistors T16 and T21 may be grouped together, power transistors T15 and T22 may be grouped together, and power transistors T14 and T23 may be grouped together.
The first part of power tubes are used for controlling current to flow from the first end of the load to the second end of the load, and the second part of power tubes are used for controlling current to flow from the second end of the load to the first end of the load. Based on this, when the load current is required to flow from the first end of the load to the second end of the load, only a part of the power tubes of the multiphase bridge can be controlled, and when the load current is required to flow from the second end of the load to the first end of the load, only a second part of the power tubes of the multiphase bridge can be controlled.
As an example, the target edge state may be a rising edge.
As an example, the above-described target edge state may be a falling edge.
The anti-straight-through module 202 is configured to obtain an inverted signal of the one path of PWM pulse signal, transmit the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmit the inverted signal of the one path of PWM pulse signal to power tubes belonging to the same bridge arm as each power tube in the group of power tubes.
In a multiphase bridge, the phenomenon that two power tubes located in the same bridge arm are simultaneously conducted is called through, and the through can burn out the power tubes generating the through phenomenon, so that the two power tubes of the same bridge arm need to be prevented from being simultaneously conducted. Based on this, the present invention provides the straight-through prevention module 202, the straight-through prevention module 202 obtains the inverse signal of the one path of PWM pulse signal, and transmits the PWM pulse signal output by the target channel (i.e. the one path of PWM pulse signal) to a group of power tubes corresponding to the target channel, and at the same time transmits the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm in the group of power tubes, thereby ensuring that the straight-through problem does not occur in the multi-phase bridge.
Also taking the multiphase bridge of fig. 1 as an example, three sets of power tubes are provided in this example, and assuming that the power tubes T11 and T24 are a first set of power tubes, the power tubes T12 and T25 are a second set of power tubes, and the power tubes T13 and T26 are a third set of power tubes. The first group of power tubes corresponds to a first channel in the pulse allocation module 201, the second group of power tubes corresponds to a second channel in the pulse allocation module 201, and the third group of power tubes corresponds to a third channel in the pulse allocation module 201.
When the load is controlled based on the multiphase bridge, the three groups of power tube groups are sequentially switched on, for example, when the edge state of the pulse synchronization signal first appears in a target edge state, the pulse distribution module 201 distributes a PWM pulse signal to a first channel, so that the pass-through prevention module 202 transmits the PWM pulse signal to the power tubes T11 and T24, and transmits an inverted signal of the PWM pulse signal to the power tubes T21 and T14, so that only the first group of power tubes is switched on, and other power tubes are not switched on; when the edge state of the pulse synchronization signal occurs for the second time, the pulse allocating module 201 does not allocate the PWM pulse signal to the first channel (i.e. does not allocate the PWM pulse signal to the power transistors T11 and T24), but allocates the PWM pulse signal to the second channel, so that the direct connection preventing module 202 transmits the PWM pulse signal to the power transistors T12 and T25, and transmits the inverted signal of the PWM pulse signal to the power transistors T22 and T15, so that only the second group of power transistors is turned on, and the other power transistors are not turned on; when the edge state of the pulse synchronization signal occurs the target edge state for the third time, the pulse allocation module 201 does not allocate the PWM pulse signal to the second channel (i.e., does not allocate the PWM pulse signal to the power tubes T12 and T25), but allocates the PWM pulse signal to the third channel, so that the anti-pass module 202 transmits the PWM pulse signal to the power tubes T13 and T26, and transmits the inverted signal of the PWM pulse signal to the power tubes T23 and T16, so that only the third group of power tubes is turned on, and the other power tubes are not turned on; when the edge state of the pulse synchronization signal occurs in the target edge state for the fourth time, the pulse allocation module 201 no longer allocates the PWM pulse signal to the third channel (i.e., no longer allocates the PWM pulse signal to the power transistors T13 and T26), but allocates the PWM pulse signal to the first channel, so that the anti-pass module 202 transmits the PWM pulse signal to the power transistors T11 and T24, and transmits the inverted signal of the PWM pulse signal to the power transistors T21 and T14, so that only the first group of power transistors are turned on, and the other power transistors are turned off, and so on, until the PWM pulse signal transmission source no longer outputs the PWM pulse signal.
In fig. 2, a PWM pulse signal × 1 represents one path of PWM pulse signal; the PWM pulse signal × N represents N PWM pulse signals, and since the pulse allocation module 201 only selects one channel at a time, the pulse allocation module 201 outputs N PWM pulse signals in sequence in a time-sharing manner, instead of outputting N PWM pulse signals at the same time, and similarly, the anti-pass module 202 also outputs N PWM pulse signals in sequence in a time-sharing manner, instead of outputting N PWM pulse signals at the same time.
According to the pulse distribution device provided by the embodiment of the invention, each pin of the MCU does not output a PWM pulse signal, but only one path of PWM pulse signal is output by the PWM pulse signal sending source, and the same PWM pulse signal is triggered by the pulse synchronization signal to be distributed to different power tube groups, so that the pulse synchronization of the PWM pulse signals received by different power tube groups is improved, and the reliability of PWM control is further improved.
In an alternative embodiment, a schematic structural diagram of the pulse allocation module 201 is shown in fig. 4, and may include:
an edge detection submodule 401 and a channel allocation submodule 402; wherein,
the edge detection sub-module 401 is used to perform target edge state detection on the pulse synchronization signal.
The pulse distribution device of the present invention can be realized by a Field Programmable Gate Array (FPGA). The pulse width resolution of the pulse synchronization signal of the FPGA is related to the working main frequency of the FGPA, and specifically, the pulse width resolution of the pulse synchronization signal of the FPGA is the inverse of the working main frequency of the FGPA, so the pulse width of the pulse synchronization signal can be set to be an integer multiple of the inverse of the working main frequency of the FGPA. For example, assuming that the main frequency of operation of the FGPA is 50MHz, the pulse width of the pulse synchronization signal may be 20ns, or 40ns, or 60ns, etc. The FPGA can realize the identification of the pulse width in a counting mode, and the pulse width of the pulse synchronization signal is set to be integral multiple of the reciprocal of the working main frequency of the FGPA, so that one period of the pulse synchronization signal is integral multiple of the reciprocal of the working main frequency of the FGPA, the recounting can be started when one target edge state of the pulse synchronization signal is detected, and when the counting number reaches a preset value (the ratio of one period of the pulse synchronization signal to the working main frequency of the FGPA), a new target edge state is considered to be detected.
The channel allocation submodule 402 is configured to, when the edge detection submodule 401 detects a target edge state of the pulse synchronization signal, turn on a target channel of the N channels of the controllable switch according to a preset control sequence, so as to allocate the one path of PWM pulse signal to the target channel.
In the embodiment of the present invention, a controllable switch is disposed in the channel allocation sub-module 402, and the controllable switch has M selectable channels, where M is an integer greater than or equal to N. The controllable switch may be a single pole, multiple throw switch, so that only one channel can be switched on at a time.
The movable end of the controllable switch is an input end, namely an input end of a PWM pulse signal, a plurality of immovable ends of the controllable switch form a plurality of output ends, the control end of each group of power tubes of the multiphase bridge is correspondingly connected with one immovable end of the controllable switch, different groups of power tubes are connected with different immovable ends, and the movable end of the controllable switch and any one of the immovable ends form a conducting channel when being connected.
The control end of each group of power transistors is the control end of each power transistor in the group of power transistors, such as the multiphase bridge shown in fig. 1, and the control end of each power transistor is a Gate (Gate) of the power transistor.
Since the power tube groups and the channels of the controllable switches are in one-to-one correspondence, the order in which the PWM pulse signals are assigned to the channels corresponds to the order in which the PWM pulse signals are assigned to the power tube groups.
In an alternative embodiment, another structural schematic diagram of the pulse allocation module 201 is shown in fig. 5, and may further include:
a channel configuration submodule 501, configured to determine, in the controllable switch, available channels of the target number and a control sequence of the available channels of the target number when the target number is obtained; the first channel belongs to the target number of available channels.
The target number may be input by a user operating the pulse allocation module 201, that is, the pulse allocation apparatus provided in the present application may perform channel configurations of different numbers, so that the pulse allocation apparatus may be suitable for controlling multi-phase bridges of multiple scales (corresponding to different values of N), thereby improving the application range of the pulse allocation apparatus.
In an alternative embodiment, a schematic structural diagram of the channel configuration sub-module 501 is shown in fig. 6, and may include: a dial switch 601 and a first configuration unit 602; wherein,
the first configuration unit 602 is used for determining a binary code by the state of each key of the dial switch 601, and the decimal number corresponding to the binary code is the target number.
Each key of dial switch 601 can realize the selection of 0 and 1 of binary code, and if dial switch 601 is provided with K keys, the selection of K binary codes can be realized, and at most 2 binary codes can be supported K The configuration of the individual channels. For example, assuming that K is 4, the binary code obtained by the dial switch 601 is 0110, and the decimal number corresponding to the binary code 0110 is 6, the target number may be determined to be 6.
The first configuration unit 602 may further be configured to: a target number of available channels is determined in the controllable switch, and a control sequence for the target number of available channels is determined.
The control sequence of the target number of available channels may be preset, for example, assuming that each channel in the controllable switch has a number, the number is selected in the descending order, or the number is selected in the descending order.
In an alternative embodiment, another schematic structural diagram of the channel configuration sub-module 501 is shown in fig. 7, and may include: a field programmable gate array FPGA chip 701 and a second configuration unit 702; wherein,
the second configuration unit 702 is configured to determine a binary code according to a level of each target pin of the fpga chip 701, where a decimal number corresponding to the binary code is the target number, and the level of the target pin is related to a position of a target resistor in an external circuit of the target pin.
As an example, each target pin of the fpga chip 701 may have two lines connected in parallel, one of the two lines (for convenience of description and distinction, referred to as a first line) may enable the target pin to be connected to a preset power supply (e.g., a 3.3v power supply) through a 0 ohm resistor, the other line (for convenience of description and distinction, referred to as a second line) may enable the target pin to be grounded through a 0 ohm resistor, and the resistors on the two lines are pluggable into the corresponding lines. When the 0 ohm resistor is connected to the first line of the target pin A and is not connected to the second line of the target pin A, the field programmable gate array chip 701 detects the binary code 1 of the target pin A, when the 0 ohm resistor is connected to the second line of the target pin A and is not connected to the first line of the target pin A, the field programmable gate array chip 701 detects the binary code 0 of the target pin A, and if the field programmable gate array chip 701 comprises K target pins, the K target pins can realize the selection of the K binary codes and can support 2 at most K The configuration of the individual channels. K0 ohm resistors may be configured for K target pins, i.e., one 0 ohm resistor is inserted for each target pin. A user may select which line of each target pin the resistor is to be inserted into according to actual needs, for example, if the user wants to configure 4 channels and the corresponding binary code is 0100, it is necessary to connect the resistor of 0 ohm to the second line at the target pin corresponding to the highest bit and connect the resistor of the second line to the target pin corresponding to the next highest bitAnd at the pin, connecting a 0 ohm resistor into the first line, connecting a 0 ohm resistor into the second line at the target pin corresponding to the third high position, and connecting a 0 ohm resistor into the second line at the target pin corresponding to the lowest position.
The second configuration unit 702 may further be configured to: a target number of available channels is determined in the controllable switch, and a control sequence for the target number of available channels is determined.
The control sequence of the target number of available channels may be preset, for example, assuming that each channel in the controllable switch has a number, the number is selected in the descending order, or the number is selected in the descending order.
In an alternative embodiment, a schematic structural diagram of the above-mentioned anti-shoot-through module 202 is shown in fig. 8, and may include: an inverting sub-module 801 and an output sub-module 802; wherein,
the negation submodule 801 is configured to negate the one path of PWM pulse signal to obtain an inverted signal of the one path of PWM pulse signal.
As an example, the negation sub-module 801 may be implemented by an inverter.
The output sub-module 802 is used for determining whether an inverted signal of the PWM pulse signal is at a high level; if the judgment result is negative, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the reverse phase signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
In order to further ensure that the power tubes belonging to the same bridge arm as the power tubes in the group of power tube groups are in an off state, the invention firstly judges whether the reverse phase signal of the PWM pulse signal is in a high level, and outputs the reverse phase signal of the PWM pulse signal to the power tubes belonging to the same bridge arm in the group of power tube groups under the condition that the reverse phase signal is not in the high level, thereby ensuring that the power tubes belonging to the same bridge arm are not in an on state at the same time.
Furthermore, if the inverse signal of the PWM pulse signal is at a high level, the control terminals of the power transistors belonging to the same bridge arm as the power transistors in the group of power transistors are forcibly changed to a low level, thereby avoiding the shoot-through problem.
In an alternative embodiment, another schematic structural diagram of the pulse distribution apparatus provided in the embodiment of the present application is shown in fig. 9, and may further include:
and an interference filtering module 901, configured to perform low-pass filtering processing on the pulse synchronization signal and the one path of PWM pulse signal respectively.
In order to avoid interference signals such as false pulses, burrs and the like of the PWM pulse signals and the pulse synchronization signals generated by the PWM pulse signal sending source, the invention also carries out low-pass filtering processing on the PWM pulse signals and the pulse synchronization signals generated by the PWM pulse signal sending source so as to filter the interference signals such as the false pulses, the burrs and the like, avoid the false operation of channel allocation caused by the interference signals and prevent the interference signals from being transmitted to a later stage.
Accordingly, the pulse allocating module 201 is specifically configured to, when a target edge state of the pulse synchronization signal after the low-pass filtering is detected, allocate the PWM pulse signal after the low-pass filtering to a target channel of the N channels.
As shown in fig. 10, a timing diagram for sequentially outputting PWM pulse signals to four groups of power transistors in a multiphase bridge is provided according to an embodiment of the present invention.
The "clock synchronization" and "PWM input" indicate a pulse synchronization signal and a PWM pulse signal output by a PWM pulse signal transmission source. "PWM output 1" is a PWM pulse signal assigned to a first group of the four groups of power tubes, "PWM output 2" is a PWM pulse signal assigned to a second group of the four groups of power tubes, "PWM output 3" is a PWM pulse signal assigned to a third group of the four groups of power tubes, and "PWM output 4" is a PWM pulse signal assigned to a fourth group of the four groups of power tubes.
Corresponding to the apparatus embodiment, an embodiment of the present invention further provides a pulse allocation method, and an implementation flowchart of the pulse allocation method provided in the embodiment of the present invention is shown in fig. 11, and may include:
step S1101: when a target edge state of a pulse synchronization signal is detected, distributing a path of PWM pulse signal which has the same phase and period as the pulse synchronization signal and is output simultaneously to a target channel of N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
step S1102: and obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
According to the pulse distribution method provided by the embodiment of the invention, each pin of the MCU does not output a PWM pulse signal, but only one path of PWM pulse signal is output, and the same PWM pulse signal is triggered by the pulse synchronization signal to be distributed to different power tube groups, so that the pulse synchronism of the PWM pulse signals received by different groups of power tubes is improved, and the reliability of PWM control is further improved.
In an optional embodiment, the pulse allocation method may further include: carrying out target edge state detection on the pulse synchronization signal;
one implementation manner of distributing the one-path PWM pulse signal, which has the same phase and period as the pulse synchronization signal and is output at the same time, to a target channel of the N channels may be as follows:
and when the target edge state of the pulse synchronization signal is detected, conducting a target channel in the N channels of the controllable switch according to a preset control sequence so as to distribute the PWM pulse signal to the target channel.
In an optional embodiment, the pulse allocation method may further include: when a target number is obtained, determining the available channels of the target number and the control sequence of the available channels of the target number in the controllable switch;
the first channel belongs to the target number of available channels.
In an optional embodiment, one implementation manner of obtaining the number of targets includes: determining a binary code through the state of each key of the dial switch;
the decimal number corresponding to the binary code is the target number.
In an optional embodiment, one implementation manner of obtaining the number of targets includes: determining a binary code through the level of each target pin of the field programmable gate array chip; the level of the target pin is related to the position of a target resistor in an external circuit of the target pin.
And the decimal number corresponding to the binary code is the target number.
In an optional embodiment, step S1102 may specifically include:
negating the one path of PWM pulse signal to obtain an inverted signal of the one path of PWM pulse signal;
judging whether the inverted signal of the PWM pulse signal is at a high level; if the judgment result is negative, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the inverted signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
In an optional embodiment, the pulse allocation method may further include:
respectively carrying out low-pass filtering processing on the pulse synchronization signal and the one-path PWM pulse signal;
when the target edge state of the pulse synchronization signal is detected, allocating one path of PWM pulse signal, which has the same phase and period as the pulse synchronization signal and is output at the same time, to a target channel of the N channels, includes:
and when the target edge state of the pulse synchronization signal after the low-pass filtering processing is detected, distributing the PWM pulse signal after the low-pass filtering processing to a target channel in the N channels.
The pulse distribution device and the pulse distribution method provided by the embodiment of the invention can be applied to electronic equipment. Alternatively, fig. 12 shows a block diagram of a hardware structure of the electronic device, and referring to fig. 12, the hardware structure of the electronic device may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;
in the embodiment of the present invention, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete mutual communication through the communication bus 4;
the processor 1 may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits configured to implement embodiments of the present invention, etc.;
the memory 3 may include a high-speed RAM memory, and may further include a non-volatile memory (non-volatile memory) or the like, such as at least one disk memory;
wherein the memory stores a program and the processor can call the program stored in the memory, the program for:
when the target edge state of the pulse synchronization signal is detected, distributing a path of PWM pulse signal which has the same phase and period with the pulse synchronization signal and is output simultaneously to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
Alternatively, the detailed function and the extended function of the program may be as described above.
An embodiment of the present invention further provides a storage medium, where the storage medium may store a program suitable for being executed by a processor, where the program is configured to:
when the target edge state of the pulse synchronization signal is detected, distributing a path of PWM pulse signal which has the same phase and period with the pulse synchronization signal and is output simultaneously to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and obtaining the inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
Alternatively, the detailed function and the extended function of the program may be as described above.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided by the present invention, it should be understood that the disclosed system (if any), apparatus and method may be implemented in other ways. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
It should be understood that the embodiments of the present invention can be combined with each other from the drawings, the embodiments and the features to solve the above technical problems.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A pulse distribution apparatus, comprising:
the pulse distribution module is used for distributing a path of PWM pulse signals which have the same phase and period with the pulse synchronization signals and are output simultaneously to a target channel in N channels when the target edge state of the pulse synchronization signals is detected; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and the direct connection prevention module is used for acquiring the reverse phase signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the reverse phase signal of the one path of PWM pulse signal to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
2. The apparatus of claim 1, wherein the pulse allocation module comprises:
the edge detection submodule is used for carrying out target edge state detection on the pulse synchronization signal;
and the channel distribution submodule is used for conducting a target channel in the N channels of the controllable switch according to a preset control sequence when the edge detection submodule detects the target edge state of the pulse synchronization signal so as to distribute the PWM pulse signal to the target channel.
3. The apparatus of claim 2, wherein the pulse allocation module further comprises:
a channel configuration submodule, configured to determine, in the controllable switch, a target number of available channels and a control order of the target number of available channels when the target number is obtained;
the first channel belongs to the target number of available channels.
4. The apparatus of claim 3, wherein the channel configuration submodule comprises: the dial switch and the first configuration unit; wherein,
the first configuration unit is used for determining a binary code through the state of each key of the dial switch;
and the decimal number corresponding to the binary code is the target number.
5. The apparatus of claim 3, wherein the channel configuration submodule comprises: the field programmable gate array chip and the second configuration unit; wherein,
the second configuration unit is used for determining a binary code through the level of each target pin of the field programmable gate array chip; the level of the target pin is related to the position of a target resistor in an external circuit of the target pin;
and the decimal number corresponding to the binary code is the target number.
6. The apparatus of claim 1, wherein the anti-shoot-through module comprises:
the negation submodule is used for negating the path of PWM pulse signal to obtain an inverted signal of the path of PWM pulse signal;
the output submodule is used for judging whether an inverted signal of the PWM pulse signal is at a high level or not; if the judgment result is negative, the PWM pulse signal output by the target channel is transmitted to a group of power tubes corresponding to the target channel, and the reverse phase signal of the PWM pulse signal is transmitted to the power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
7. The apparatus of claim 1, further comprising:
the interference filtering module is used for respectively carrying out low-pass filtering processing on the pulse synchronization signal and the one path of PWM pulse signal;
the pulse distribution module is specifically configured to, when a target edge state of the pulse synchronization signal after the low-pass filtering is detected, distribute the PWM pulse signal after the low-pass filtering to a target channel of the N channels.
8. The apparatus of claim 1, wherein the target edge state is a rising edge; alternatively, the target edge state is a falling edge.
9. The apparatus of claim 1, wherein the one PWM pulse signal is assigned to only one of the N channels at a time.
10. A method of pulse allocation, comprising:
when the target edge state of the pulse synchronization signal is detected, distributing a path of PWM pulse signal which has the same phase and period with the pulse synchronization signal and is output simultaneously to a target channel in N channels; different channels in the N channels correspond to different groups of power tubes in the N groups of power tubes connected with the load in the multiphase bridge; wherein N is greater than 1; the one path of PWM pulse signal and the pulse synchronization signal are output by a PWM pulse signal sending source in response to an enabling signal; when the target edge state of the pulse synchronization signal is detected at different times, the PWM pulse signal is distributed to different channels of the N channels;
and obtaining an inverse signal of the one path of PWM pulse signal, transmitting the PWM pulse signal output by the target channel to a group of power tubes corresponding to the target channel, and transmitting the inverse signal of the one path of PWM pulse signal to power tubes belonging to the same bridge arm with each power tube in the group of power tubes.
CN202210747919.1A 2022-06-29 2022-06-29 Pulse distribution device and method Pending CN115118137A (en)

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