CN115117084A - Semiconductor memory device with a plurality of memory cells - Google Patents

Semiconductor memory device with a plurality of memory cells Download PDF

Info

Publication number
CN115117084A
CN115117084A CN202111001643.4A CN202111001643A CN115117084A CN 115117084 A CN115117084 A CN 115117084A CN 202111001643 A CN202111001643 A CN 202111001643A CN 115117084 A CN115117084 A CN 115117084A
Authority
CN
China
Prior art keywords
insulator
semiconductor
conductor
memory cell
charge trapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111001643.4A
Other languages
Chinese (zh)
Inventor
松尾浩司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of CN115117084A publication Critical patent/CN115117084A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device capable of improving reliability, comprising: a1 st semiconductor (32) extending in a1 st direction (X direction) parallel to the substrate (30); a1 st conductor (41) extending in a2 nd direction (Z direction) perpendicular to the substrate; a1 st charge accumulation layer (44) provided so as to surround the outer periphery of the 1 st conductor; a1 st insulator (42) provided between the 1 st conductor and the 1 st charge trapping layer so as to surround the 1 st conductor; a2 nd insulator (45) provided between the 1 st charge trapping layer and the 1 st semiconductor so as to surround the 1 st charge trapping layer; and a1 st Memory Cell (MC). A part of the outer periphery of the 2 nd insulator is in contact with the 1 st semiconductor. The 1 st memory cell includes a1 st conductor, a1 st semiconductor, a portion of a1 st charge trapping layer provided between the 1 st conductor and the 1 st semiconductor, a portion of a1 st insulator, and a portion of a2 nd insulator.

Description

Semiconductor memory device with a plurality of memory cells
Related application
This application claims priority based on Japanese patent application No. 2021-048655 (application date: 2021, 3/23). The present application includes the entire contents of the base application by reference to the base application.
Technical Field
Embodiments of the present invention relate to a semiconductor memory device.
Background
As a semiconductor memory device, a NAND type flash memory is known.
Disclosure of Invention
The invention provides a semiconductor memory device capable of improving reliability.
A semiconductor memory device according to an embodiment includes: a1 st semiconductor extending in a1 st direction parallel to the substrate; a1 st conductor extending in a2 nd direction perpendicular to the substrate; a1 st charge trapping layer provided so as to surround the outer periphery of the 1 st conductor; a1 st insulator provided between the 1 st conductor and the 1 st charge trapping layer so as to surround the 1 st conductor; a2 nd insulator provided between the 1 st charge trapping layer and the 1 st semiconductor so as to surround the 1 st charge trapping layer; and a1 st storage unit. A part of the outer periphery of the 2 nd insulator is in contact with the 1 st semiconductor. The 1 st memory cell includes a1 st conductor, a1 st semiconductor, a portion of a1 st charge trapping layer provided between the 1 st conductor and the 1 st semiconductor, a portion of a1 st insulator, and a portion of a2 nd insulator.
Drawings
Fig. 1 is a block diagram of a semiconductor memory device according to an embodiment.
Fig. 2 is a circuit diagram of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 3 is a perspective view of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 4 is a plan view of the semiconductor 32 in the uppermost layer in the memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 5 is a plan view of the uppermost insulator 33 in the memory cell array of the semiconductor memory device according to the embodiment.
Fig. 6 is a sectional view taken along line a 1-a 2 of fig. 4 and 5.
Fig. 7 is a sectional view taken along line B1-B2 of fig. 4 and 5.
Fig. 8 is a sectional view taken along line C1-C2 of fig. 4 and 5.
Fig. 9 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 10 is a sectional view taken along line a 1-a 2 of fig. 9.
Fig. 11 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 12 is a sectional view taken along line a 1-a 2 of fig. 11.
Fig. 13 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 14 is a sectional view taken along line a 1-a 2 of fig. 13.
Fig. 15 is a sectional view taken along line C1-C2 of fig. 13.
Fig. 16 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 17 is a sectional view taken along line a 1-a 2 of fig. 16.
Fig. 18 is a sectional view taken along line C1-C2 of fig. 16.
Fig. 19 is a top view taken along line D1-D2 of fig. 17 and 18.
Fig. 20 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 21 is a sectional view taken along line C1-C2 of fig. 20.
FIG. 22 is a top view taken along line D1-D2 of FIG. 21.
Fig. 23 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 24 is a sectional view taken along line C1-C2 of fig. 23.
FIG. 25 is a top view taken along line D1-D2 of FIG. 24.
Fig. 26 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 27 is a sectional view taken along line C1-C2 of fig. 26.
Fig. 28 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 29 is a sectional view taken along line a 1-a 2 of fig. 28.
FIG. 30 is a top view taken along line D1-D2 of FIG. 29.
Fig. 31 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 32 is a sectional view taken along line a 1-a 2 of fig. 31.
FIG. 33 is a top view taken along line D1-D2 of FIG. 32.
Fig. 34 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
Fig. 35 is a sectional view taken along line a 1-a 2 of fig. 34.
FIG. 36 is a top view taken along line D1-D2 of FIG. 35.
Fig. 37 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 38 is a sectional view taken along line a 1-a 2 of fig. 37.
FIG. 39 is a top view taken along line D1-D2 of FIG. 38.
Fig. 40 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 41 is a sectional view taken along line a 1-a 2 of fig. 40.
FIG. 42 is a top view taken along line D1-D2 of FIG. 41.
Fig. 43 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
Fig. 44 is a sectional view taken along line a 1-a 2 of fig. 43.
FIG. 45 is a top view taken along line D1-D2 of FIG. 44.
Fig. 46 is a plan view showing a manufacturing process of a memory cell array provided in the semiconductor memory device according to the embodiment.
FIG. 47 is a cross-sectional view taken along line A1-A2 of FIG. 46.
FIG. 48 is a top view taken along line D1-D2 of FIG. 47.
Fig. 49 is a plan view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to the embodiment.
FIG. 50 is a cross-sectional view taken along line A1-A2 of FIG. 49.
FIG. 51 is a top view taken along line D1-D2 of FIG. 50.
Fig. 52 is a plan view showing a memory cell transistor in a memory cell array provided in the semiconductor memory device according to the embodiment.
Detailed Description
Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals are given to components having substantially the same functions and configurations, and the description will be repeated only when necessary. The embodiments described below are intended to exemplify apparatuses and methods for embodying the technical ideas of the embodiments, and the technical ideas of the embodiments are not intended to specify the materials, shapes, structures, arrangements, and the like of the constituent members in the following embodiments. The technical idea of the embodiments can be variously modified within the scope of the claims.
The semiconductor memory device according to the embodiment will be described. Hereinafter, a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked above a semiconductor substrate will be described as an example of a semiconductor memory device.
1 Structure
1.1 Overall Structure of semiconductor memory device
First, an example of the overall configuration of the semiconductor memory device will be described with reference to fig. 1. Fig. 1 is an example of a block diagram showing a basic overall configuration of a semiconductor memory device.
As shown in fig. 1, the semiconductor memory device 1 includes a memory core (memory core) section 10 and a peripheral circuit section 20.
The memory core section 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.
The memory cell array 11 includes a plurality of blocks BLK (BLK 0 to BLK3 in the example of fig. 1) including a plurality of nonvolatile memory cell transistors (hereinafter also referred to as "memory cells") corresponding to rows and columns. Each block BLK includes a plurality of string units SU. In the example of fig. 1, the block BLK includes 5 string units SU0 to SU 4. Also, each string unit SU includes a plurality of NAND strings NS. The number of blocks BLK in the memory cell array 11 and the number of string units SU in the blocks BLK are arbitrary. The details of the memory cell array 11 will be described later.
The row decoder 12 decodes a row address received from an external controller not shown. And, the row decoder 12 selects the row direction of the memory cell array 11 based on the decoding result. More specifically, the row decoder 12 applies a voltage to various wirings (word lines and selection gate lines) for selecting a row direction.
The sense amplifier 13 reads data from the memory cell transistors of a certain block BLK at the time of reading data. In addition, the sense amplifier 13 applies a voltage corresponding to the write data to the memory cell array 11 at the time of writing data.
The peripheral circuit unit 20 includes a sequencer 21 and a voltage generation circuit 22.
The sequencer 21 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generation circuit 22, the row decoder 12, the sense amplifier 13, and the like during the write operation, the read operation, and the erase operation.
The voltage generation circuit 22 generates voltages necessary for a write operation, a read operation, and an erase operation, and supplies the voltages to the row decoder 12, the sense amplifier 13, and the like.
1.2 Circuit Structure of memory cell array
Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to fig. 2. Fig. 2 is a circuit diagram of the memory cell array 11. The example of fig. 2 shows circuit diagrams of the string units SU0 to SU 2. In this embodiment mode, a plurality of NAND strings NS in the string unit SU are stacked over a semiconductor substrate. The example of fig. 2 shows a circuit configuration of a plurality of stacked NAND strings NS in a string unit SU in a three-dimensional manner.
As shown in fig. 2, the NAND string NS includes selection transistors ST1 and ST2, respectively, and a plurality of memory cell transistors MC (8 memory cell transistors MC0 to MC7 in the example of fig. 2).
The memory cell transistor MC includes a control gate and a charge accumulation layer, and retains data in a nonvolatile manner. The memory cell transistor MC may be a MONOS (Metal-Oxide-Silicon) type in which an insulator is used for the charge accumulation layer, or a fg (floating gate) type in which a conductor is used for the charge accumulation layer. Hereinafter, a case where the memory cell transistor MC is of the FG type will be described. The number of memory cell transistors MC included in 1 NAND string NS may be 16, 32, 48, 64, 96, 128, or the like, and the number thereof is not limited.
The memory cell transistors MC0 to MC7 included in the NAND string NS have their current paths connected in series. The drain of the memory cell transistor MC0 is connected to the source of the select transistor ST 1. The source of the memory cell transistor MC7 is connected to the drain of the select transistor ST 2. The number of the selection transistors ST1 and ST2 included in the NAND string NS is arbitrary, and each of them may be 1 or more.
The gates of the plurality of memory cell transistors MC stacked in each string unit SU are commonly connected to 1 word line WL. More specifically, for example, the gates of a plurality of memory cell transistors MC0 stacked in the string units SU0 to SU2 are commonly connected to the word line WL 0. Similarly, the gates of the plurality of memory cell transistors MC1 to MC7 stacked in the string units SU0 to SU2 are connected to the word lines WL1 to WL7, respectively.
In each string unit SU, the gates of the plurality of stacked select transistors ST1 are commonly connected to 1 select gate line SGD. For example, the select transistors ST1 in the string units SU0 are connected to the select gate lines SGD0, respectively. The select transistors ST1 in the string unit SU1 are connected to the select gate lines SGD1, respectively. The select transistors ST1 in the string unit SU2 are connected to the select gate lines SGD2, respectively.
The drains of the plurality of selection transistors ST1 in the string unit SU are connected to different bit lines BL, respectively. The drains of the selection transistors ST1 provided in the same layer of each string unit SU are commonly connected to 1 bit line BL. More specifically, for example, the drain of the select transistor ST1 corresponding to the NAND string NS disposed at the lowermost layer of each string unit SU is connected to the bit line BL 0. The drain of the selection transistor ST1 corresponding to the NAND string NS arranged in the nth layer (n is an integer of 1 or more) of each string unit SU is connected to the bit line BLn.
In each string unit SU, the gates of the plurality of stacked selection transistors ST2 are commonly connected to 1 selection gate line SGS. For example, the select transistors ST2 in the string units SU0 are respectively connected to the select gate lines SGS 0. The select transistors ST2 in the string unit SU1 are connected to the select gate lines SGS1, respectively. The select transistors ST2 in the string unit SU2 are connected to the select gate lines SGS2, respectively. The gates of the plurality of selection transistors ST2 of each string unit SU may be commonly connected to 1 selection gate line SGS.
The sources of the plurality of selection transistors ST2 in each string unit SU are commonly connected to 1 source line SL.
In the write operation and the read operation, a plurality of memory cell transistors MC connected to 1 word line WL in the string unit SU are selected together. In other words, the stacked memory cell transistors MC in the string unit SU are selected together.
1.3 Structure of memory cell array
Next, an example of the structure of the memory cell array 11 will be described with reference to fig. 3. Fig. 3 is a perspective view showing a part of the memory cell array 11. In the example of fig. 3, a portion corresponding to the semiconductor 32 is hatched with diagonal lines in order to clarify the structure of the semiconductor 32. In the following description, a direction substantially parallel to the semiconductor substrate is referred to as an X direction. A direction substantially parallel to the semiconductor substrate and intersecting the X direction is expressed as a Y direction. Further, a direction substantially perpendicular to the semiconductor substrate is expressed as a Z direction.
As shown in fig. 3, an insulator 31 is provided on the semiconductor substrate 30. Insulator 31 is, for example, silicon oxide (SiO) 2 ). Further, the memory cell array 11 is provided on the insulator 31. The memory cell array 11 includes, for example, a plurality of semiconductors 32, a plurality of insulators 33 to 35, a plurality of semiconductors 36, and a plurality of electrode pillars CGP.
A plurality of semiconductors 32 are separated in the Z directionAnd opening and laminating. More specifically, the plurality of semiconductors 32 are stacked on the insulator 31 with the insulator 33 interposed therebetween. For example, polysilicon is used for the semiconductor 32. SiO is used for example in the insulator 33 2 。
Semiconductor 32 includes ST1 connection portion SC extending in the Y direction, and a plurality of active region portions AA having one end connected to ST1 connection portion SC and extending in the X direction. The ST1 connection portion SC is connected to the semiconductor 36 functioning as a current path of the selection transistor ST 1. The active region portion AA functions as an active region of the plurality of memory cell transistors MC forming a channel layer. 1 active area portion AA corresponds to 1 NAND string NS. An insulator 34 is provided between the active region portions AA adjacent in the Y direction. SiO is used for example in the insulator 34 2 。
The plurality of semiconductors 36 are stacked on the insulator 31 with the insulator 33 interposed therebetween. Semiconductor 36 is provided in the same layer as semiconductor 32. The semiconductor 36 is in contact with one side surface of the semiconductor 32 in the X direction toward the ST1 connection portion SC. An n-type semiconductor is used as the semiconductor 36. For example, polycrystalline silicon (n-type semiconductor) doped with an impurity such as phosphorus is used for the semiconductor 36.
The insulators 35 are arranged in a row in the Y direction. The insulator 35 has, for example, a cylindrical shape extending in the Z direction. The insulator 35 has side surfaces contacting the stacked semiconductors 36 and the insulator 33, and a bottom surface extending into the insulator 31. In other words, the semiconductor 36 is provided in the same layer as the semiconductor 32 so as to surround the outer peripheries of the plurality of insulators 35.
The electrode column CGP extends in the Z-direction with a bottom surface reaching into the insulator 31. The electrode pillars CGP function as gate electrodes of a plurality of memory cell transistors MC stacked in the Z direction. A word line WL, not shown, is provided above the electrode bar CGP and electrically connected to the electrode bar CGP. The details of the structure of the electrode column CGP will be described later.
Between the plurality of electrode pillars CGP arranged in two rows alternately in the X direction, active region portions AA extending in the X direction are arranged. On the other hand, an insulator 34 is provided between the plurality of electrode pillars CGP arranged in two rows along the X direction so as to face each other in the Y direction. In other words, the plurality of electrode pillars CGP arranged in two rows along the X direction so as to face each other in the Y direction are arranged to be staggered in the Y direction with the active region part AA interposed therebetween. In the same layer as the active region part AA, on the outer periphery of the electrode pillar CGP, a barrier insulating film, a charge accumulation layer, and a tunnel insulating film of the memory cell transistor MC are provided. At the position where the electrode pillar CGP crosses the active area portion AA, 1 memory cell transistor MC is disposed. A plurality of memory cell transistors MC arranged alternately along the X direction are connected to 1 active region part AA. That is, a plurality of memory cell transistors MC connected to 1 active area part AA correspond to 1 NAND string NS.
1.4 Top-down Structure of memory cell array
Next, an example of a planar structure of the memory cell array 11 will be described with reference to fig. 4 and 5. Fig. 4 is a top view of the uppermost semiconductor 32. Fig. 5 is a plan view of the uppermost insulator 33.
As shown in fig. 4 and 5, the electrode column CGP has a cylindrical shape and includes an insulator 40, a conductor 41, and an insulator 42. In addition, the shape in the XY plane of the electrode column CGP is not limited to a circle. For example, the shape in the XY plane of the electrode column CGP may also be a rectangular shape. The insulator 40 has, for example, a cylindrical shape. SiO is used for example in the insulator 40 2 . Alternatively, the insulator 40 may be discarded. That is, the conductor 41 may have a cylindrical shape or a cylindrical shape. In the YX plane, a cylindrical conductor 41 surrounding the insulator 40 is provided. The conductor 41 functions as a gate electrode of the memory cell transistor MC. A conductive material is used in the conductive body 41. The conductive material may be, for example, a metal material or a semiconductor material to which impurities are added. As the conductive material, for example, a stacked structure including tungsten (W) and titanium nitride (TiN) is used. Further, a cylindrical insulator 42 is provided so as to surround the conductor 41. The insulator 42 functions as a barrier insulating film of the memory cell transistor MC. An insulating material is used in the insulator 42. The insulating material is, for example, a high dielectric constant material such as an oxide or nitride of aluminum (Al), hafnium (Hf), Ti, zirconium (Zr), lanthanum (La), or the likeSeveral films, or SiO 2 And a high-voltage-resistant film such as silicon oxynitride (SiON), or a mixture or a laminated film thereof. Hereinafter, SiO is used for the insulator 42 2 The case of (c) will be explained.
As shown in fig. 4, a cylindrical insulator 43, a charge accumulation layer 44, and an insulator 45 are provided in this order in the same layer as the semiconductor 32 so as to surround the outer periphery of the electrode pillar CGP. The insulator 43 is provided so as to surround the insulator 42, and functions as a barrier insulating film of the memory cell transistor MC in alignment with the insulator 42. SiO is used for example in the insulator 43 2 . The charge trapping layer 44 is provided so as to surround the insulator 43. In the case of the FG-type memory cell transistor MC, for example, polysilicon is used for the charge trapping layer 44. The insulator 45 is provided so as to surround the charge trapping layer 44, and functions as a tunnel insulating film of the memory cell transistor MC. SiO, for example, is used in the insulator 45 2 。
Between the plurality of electrode pillars CGP arranged in two columns alternately in the X direction, 1 active region portion AA is provided. The active region AA is in contact with a portion of the insulator 45 provided on the outer periphery of each electrode pillar CGP. For example, the electrode posts CGP1 and CGP2 are disposed adjacent to each other in the X direction, and the electrode post CGP3 is disposed between the electrode posts CGP1 and CGP2 in the X direction and at a position different from the electrode posts CGP1 and CGP2 in the Y direction. An active region AA is provided between the electrode pillars CGP1 and CGP3 and between the electrode pillars CGP2 and CGP 3. For example, in the electrode pillars CGP1 and CGP3, between the cylindrical charge accumulation layers 44 provided on the outer peripheries thereof, there is a region having a 3-layer structure of the insulator 45 corresponding to the electrode pillar CGP1, the semiconductor 32 (active region AA), and the insulator 45 corresponding to the electrode pillar CGP3 in the XY plane. The active region portion AA extends in a meandering manner in the X direction, for example, between a plurality of electrode pillars CGP. In other words, the active area portion AA has a wave-shaped shape extending along the X direction.
In the outer periphery of the insulator 45, the other portion not in contact with the active area portion AA is in contact with the insulator 34. Between the plurality of electrode pillars CGP arranged in two rows along the Y direction in such a manner as to face each other in the X direction, the insulator 34 is provided and the source region portion AA is not provided. For example, the electrode column CGP4 and the electrode column CGP5 are disposed adjacent to each other in the X direction. The electrode posts CGP1 and CGP4 are disposed adjacent to each other in the Y direction, and the electrode posts CGP2 and CGP5 are disposed adjacent to each other in the Y direction. Further, an insulator 34 is provided in a region where the electrode posts CGP1, CGP2, CGP4, and CGP5 face each other. The side surface of the insulator 34 contacts the semiconductor 32, and the surface contacting the semiconductor 32 is curved. More specifically, for example, the insulator 34 has a shape in which a plurality of circular regions extending concentrically from a plurality of holes RH provided along the X direction are connected in the X direction.
The region including the electrode pillar CGP, the active region portion AA in contact with the insulator 45, and the insulator 43, the charge accumulation layer 44, and a part of the insulator 45 provided between the electrode pillar CGP and the active region portion AA functions as the memory cell transistor MC.
The plurality of insulators 35 having a cylindrical shape, for example, are arranged in 1 row in the Y direction, for example. A semiconductor 36 is provided so as to surround the outer peripheries of the insulators 35, and the semiconductor 36 has a shape in which a plurality of cylinders are connected in the Y direction. One side surface of the semiconductor 36 in the X direction meets the side surface of the ST1 connection portion SC of the semiconductor 32.
As shown in fig. 5, a plurality of holes RH arranged in a row along the X direction are provided between a plurality of electrode pillars CGP arranged in two rows along the Y direction so as to face each other in the X direction, such that the plurality of holes RH and the plurality of electrode pillars CGP are arranged alternately. The hole RH is filled with an insulator 34. In this embodiment, in the manufacturing process of the memory cell array 11, a replacement method is employed in which after a portion corresponding to the semiconductor 32 is formed with a sacrificial film, the sacrificial film is replaced with the semiconductor 32 and the insulator 34. The hole RH was used for the replacement. The manufacturing process of the memory cell array 11 will be described later.
1.5 Cross-sectional Structure of memory cell array
Next, a cross-sectional structure of the memory cell array 11 will be described with reference to fig. 6 to 8. Fig. 6 is a sectional view taken along line a 1-a 2 of fig. 4 and 5. Fig. 7 is a sectional view taken along line B1-B2 of fig. 4 and 5. Fig. 8 is a sectional view taken along line C1-C2 of fig. 4 and 5.
As shown in fig. 6, an insulator 31 is provided on the semiconductor substrate 30. For example, the insulating body 31 may be provided thereinIs provided withA transistor (not shown) and a plurality of wiring layers (not shown) formed on the semiconductor substrate 30.
In a part of the region on the insulator 31, for example, 5 layers of semiconductors 32 (active region part AA) are provided with an insulator 33 interposed therebetween. In other words, for example, 5 layers of active region portions AA and 5 layers of insulators 33 are alternately arranged on the insulator 31. The number of stacked layers of the semiconductor 32 (active region AA) and the insulator 33 is arbitrary. In the example of fig. 6, the Y-direction width of the semiconductor 32 becomes shorter from the lower layer toward the upper layer. More specifically, for example, in the active region AA of the 5-layer semiconductor 32, if the width of the active region AA in the Y direction is CW1 to CW5 in order from the lower layer, there is a relationship of CW1> CW2> CW3> CW4> CW 5. The structure of the active area AA is not limited thereto. For example, the width of the active region AA of the semiconductor 32 stacked apart from each other in the Y direction may be the same or may be longer from the lower layer toward the upper layer.
Insulators 50 and 51 are provided on the uppermost insulator 33. For the insulators 50 and 51, SiO, for example, is used 2 . On the insulator 51, an insulator 34 is provided.
The 5-layer insulator 33 and the insulators 50 and 51 each have an opening portion formed when the hole RH is processed in the manufacturing process of the memory cell array 11. An insulator 34 is provided in the same layer of the 5-layer semiconductor 32. The insulator 34 is connected to the insulator 34 on the insulator 51 through the 5-layer insulator 33 and the opening portions of the insulators 50 and 51. In addition, the insulator 34 on the insulator 51 may also be removed.
An electrode pillar CGP is provided to penetrate the insulator 50, the 5-layer insulator 33, and the 5-layer semiconductor 32 (and the insulator 34) and to reach the insulator 31 at the bottom surface. Inside the electrode pillar CGP, for example, an insulator 40 having a substantially cylindrical shape, a conductor 41 in contact with the side surface and the bottom surface of the insulator 40, and an insulator 42 in contact with the side surface and the bottom surface of the conductor 41 are provided. The bottom surface of the insulator 42 and its vicinity are in contact with the insulator 31. In addition, the insulator 40 may have a void formed in the center. In the example of fig. 6, the electrode column CGP has a conical shape. In the same layer as the semiconductor 32, the side surfaces of the electrode pillars CGP are bent to protrude outward. However, the shape of the electrode column CGP is not limited to these. The electrode column CGP may not be tapered, and the side surfaces may not be curved.
In the same layer as the semiconductor 32, an insulator 43, a charge accumulation layer 44, and an insulator 45 are provided in this order toward the outside on the outer periphery of the electrode pillar CGP. In other words, the insulator 43 is provided between the insulator 42 and the semiconductor 32. A charge trapping layer 44 is provided between the semiconductor 32 and the insulator 43. An insulator 45 is provided between the semiconductor 32 and the charge trapping layer 44. For example, if the diameters of the 5-layer cylindrical charge trapping layer 44 are set to FR1 to FR5 in this order from the lower layer, FR1< FR2< FR3< FR4< FR5 is concerned. A region including the conductor 41, the semiconductor 32, and parts of the insulators 42 and 43, a part of the charge trapping layer 44, and a part of the insulator 45 provided between the conductor 41 and the semiconductor 32 functions as a memory cell transistor MC.
The electrode column CGP is provided with a conductor 52 penetrating the insulator 51 and the insulator 34. The conductor 52 functions as a contact plug electrically connected to the word line WL provided above and not shown. The conductive body 52 is composed of a conductive material.
As shown in fig. 7, holes RH (opening portions of the insulators 33, 50, and 51 corresponding to the holes RH) are provided in line in the X direction. An insulator 34 is provided at the opening of the insulators 33, 50, and 51 corresponding to the hole RH. In other words, in the region where the hole RH is formed, a column of the insulator 34 is provided which connects the insulators 34 formed in the plurality of layers in the Z direction. One side surface of the semiconductor 32 in the X direction toward the ST1 connection portion SC is in contact with the insulator 34, and the other side surface facing thereto is in contact with the semiconductor 36. The insulator 35 penetrates the 5-layer insulator 33, and the bottom surface reaches the insulator 31. The semiconductor 36 is provided in the same layer as the semiconductor 32 so as to surround the insulator 35. The insulator 33 and the semiconductor 36 are connected to the side surface of the insulator 35.
As shown in fig. 8, a plurality of insulators 35 are arranged in the Y direction. Further, in the same layer as the semiconductor 32, a semiconductor 36 is provided between the insulators 35.
Method for manufacturing 2 memory cell array
Next, a method for manufacturing the memory cell array 11 will be described with reference to fig. 9 to 51. Fig. 9 to 51 show the manufacturing process of the memory cell array 11. Hereinafter, a case will be described where a replacement method is used in which a structure corresponding to the semiconductor 32 is formed using a sacrificial film, and then the sacrificial film is removed and replaced with the semiconductor 32, as a method for forming the semiconductor 32.
As shown in fig. 9 and 10, an insulator 31 is formed on the semiconductor substrate 30. In this state, on the insulator 31, 5 sacrificial films 55 corresponding to the semiconductor 32 and 5 insulators 33 are alternately stacked. The sacrificial film 55 is used for replacement of the semiconductor 32. The sacrificial film 55 is made of a material that can sufficiently obtain a selectivity ratio with respect to the insulator 33 by wet etching. Hereinafter, a case where silicon nitride (SiN) is used for the sacrificial film 55 will be described.
Next, a plurality of holes CH, RH, and DH are formed to penetrate the 5-layer sacrificial film 55 and the 5-layer insulator 33 and reach the insulator 31 from the bottom surface. The holes CH are used for the formation of the electrode columns CGP. The hole RH is used for replacement of the sacrificial film 55. A hole DH is used for the formation of the insulator 35. The diameters of the holes CH, RH, and DH may be the same or different. The shapes of the holes CH, RH, and DH in the XY plane are not limited to circular (perfect circular) shapes. Each hole may be elliptical or rectangular. The cross-sectional shapes of the holes CH, RH, and DH are not limited to the tapered shapes. The cross-sectional shape of each hole may be a straight shape with the side surface along the Z direction, or a bow (bowing) shape.
As shown in fig. 11 and 12, the holes CH, RH, and DH are filled with the sacrificial film 56, and the sacrificial film 56 on the insulator 33 of the uppermost layer is removed. The sacrificial film 56 is used to temporarily fill the holes CH, RH, and DH in the manufacturing process of the memory cell array 11. For example, a material that can sufficiently obtain a selectivity ratio with respect to wet etching of the insulator 33 and the sacrificial film 55 is used for the sacrificial film 56.The sacrificial film 56 may be, for example, a material containing carbon, or may be a thin film of SiO 2 And a stacked structure of polysilicon. Hereinafter, a case where the sacrificial film 56 is a carbon film will be described.
As shown in fig. 13 to 15, the insulator 50 is formed on the insulator 33 of the uppermost layer and the sacrificial film 56 formed in the holes CH, RH, and DH.
Next, the insulator 50 on the hole DH is processed (opened), and the sacrificial film 56 in the hole DH is exposed. In the example of fig. 13 and 15, the opening diameter of the insulator 50 is smaller than the diameter of the hole DH in the upper surface of the insulator 33 of the uppermost layer. The diameter of the opening in the insulator 50 may be the same as or larger than the diameter of the hole DH in the upper surface of the insulator 33 on the uppermost layer. Then, the sacrificial film 56 in the hole DH is removed. For example, in the case where the sacrificial film 56 is a carbon film, O passes 2 Ashing is performed to remove the sacrificial film 56 in the hole DH.
As shown in fig. 16 to 19, the side surface of the sacrificial film 55 exposed in the hole DH is processed by wet etching, thereby forming a concave region extending concentrically from the hole DH. Hereinafter, the step of forming the concave regions by machining the side surfaces of the holes is referred to as "recess etching", and the concave regions are referred to as "recess regions RC". As shown in fig. 19, in the recess etching using the holes DH, the etching amount (hereinafter also referred to as "recess amount"), that is, the recess width RC1 — W of the recess region RC1 is adjusted so that the sacrificial film 55 between the holes DH arranged in the Y direction is removed. The recess width RC1_ W is the distance from the end of the opening portion of the insulator 33 formed by the hole DH to the portion where the insulator 33 meets the semiconductor 36. Thus, the recess width RC1_ W of the recess region RC1 is longer than the distance DH _ W between 2 holes DH. Therefore, the recessed region RC1 has a shape connected in the Y direction to a cylindrical recessed region RC1 provided on the outer periphery of the hole DH.
As shown in fig. 20 to 22, the semiconductor 36 is formed to fill the recess region RC 1. For example, as the semiconductor 36, phosphorus-doped Amorphous Silicon (P doped Amorphous Silicon) formed by cvd (chemical Vapor deposition) is formed. At this time, the film thickness of the semiconductor 36 is set to a film thickness that fills the recess region RC1 and does not close the opening of the hole DH.
As shown in fig. 23 to 25, the semiconductor 36 on the insulator 50 and on the side and bottom surfaces of the hole DH is removed by wet etching or isotropic etching such as cde (chemical Dry etching). At this time, the etching conditions of the recess etching are controlled so that semiconductor 36 remains in recess region RC1 and is not connected to other layers of semiconductor 36. Hereinafter, the step of filling the recess region RC in this manner will be referred to as "recess filling". As shown in fig. 24, when the opening diameter of the hole DH in the bottom surface of the insulator 50 is smaller than the diameter of the hole DH in the upper surface of the insulator 33 in the uppermost layer, a step occurs between the insulator 33 and the insulator 50. In such a case, the semiconductor 36 may remain in the step portion. Further, the semiconductor 36 may be left at the bottom of the hole DH.
As shown in fig. 26 and 27, the hole DH is filled with an insulator 35, and the insulator 35 on the insulator 50 is removed. Further, the insulator 35 may be left on the insulator 50. Further, a void may be formed inside the insulator 35.
As shown in fig. 28 to 30, the insulator 50 above the hole RH is processed (opened) to expose the sacrificial film 56 in the hole RH, and then the sacrificial film 56 in the hole RH is removed.
Next, the sacrificial film 55 is removed by wet etching or isotropic etching such as cde (chemical Dry etching), and a gap GP is formed between the insulator 31 and the insulator 33 and between the insulators 33. At this time, as shown in fig. 30, the sacrificial film 55 is removed until the side surface of the semiconductor 36 in contact with the sacrificial film 55 is exposed.
As shown in fig. 31 to 33, the semiconductor 32 is formed to fill the gap GP. At this time, the film thickness of the semiconductor 32 is set to a film thickness that fills the gap GP and does not close the opening of the hole RH. Next, a sacrifice film 57 is formed to fill the hole RH. SiN, for example, is used for the sacrificial film 57.
Next, the sacrificial film 57, the semiconductor 32, and the insulator 50 on the insulator 33 of the uppermost layer are removed. This exposes the surfaces of the uppermost insulator 33, the semiconductor 32 and the sacrificial film 57 in the hole RH, and the sacrificial film 56 and the insulator 35 corresponding to the hole CH.
As shown in fig. 34 to 36, after the insulator 50 is formed, the insulator 50 on the hole CH is processed (opened) to expose the sacrificial film 56 in the hole CH. Next, the sacrificial film 56 in the hole CH is removed.
Next, the side surface of the semiconductor 32 exposed in the hole CH is processed by recess etching, and a recess region RC2 extending concentrically from the hole CH is formed. As shown in fig. 36, in the recess etching using the holes CH, the recess amount, that is, the recess width RC2 — W of the recess region RC2 is adjusted so that the semiconductor 32 remains between the holes CH arranged alternately along the X direction. In addition, the recess width RC2_ W is the distance from the end of the opening portion of the insulator 33 formed by the hole CH to the portion where the insulator 33 meets the semiconductor 32. Therefore, if the distance of the holes CH arranged alternately is set to CH _ W, CH _ W and RC2_ W have a relationship of (RC2_ W) < ((CH _ W)/2). Therefore, the recessed regions RC2 provided in the respective holes CH are not connected to each other.
As shown in fig. 37 to 39, for example, the side surface of the semiconductor 32 exposed in the recess region RC2 is oxidized to form an insulator 45. The insulator 45 may be formed by CVD, for example.
Next, the charge trapping layer 44 is formed in the recess region RC2 by recess filling. In the example of fig. 38, the side surfaces of the charge accumulation layer 44 are curved in a concave shape, but may not be curved. Further, the charge trapping layer 44 may remain in the step portion between the insulator 33 and the insulator 50 or in the bottom of the hole CH.
As shown in fig. 40 to 42, for example, the side surface of the charge trapping layer 44 exposed in the hole CH is oxidized to form an insulator 43. The insulator 43 may be formed by CVD, for example.
Next, the insulator 42, the conductor 41, and the insulator 40 are sequentially formed into a film, and the hole CH is filled. Next, the insulator 42, the conductor 41, and the insulator 40 on the insulator 50 are removed. Thereby, the electrode pillars CGP are formed.
As shown in fig. 43 to 45, after the insulator 51 is formed, the insulator 51 on the hole RH is processed (opened) to expose the sacrificial film 57 in the hole RH. Next, the sacrificial film 57 in the hole RH is removed by wet etching or the like.
As shown in fig. 46 to 48, the side surface of semiconductor 32 exposed in hole RH is processed by recess etching, and recess region RC3 extending concentrically from hole RH is formed. Thereby, ST1 connection portion SC and active region portion AA of semiconductor 32 are formed. As shown in fig. 48, in the recess etching using the hole RH, the recess amount, that is, the recess width RC3 — W of the recess region RC3 is adjusted so that the recess regions RC3 of the holes RH adjacent in the X direction are connected and the active region AA does not disappear. In addition, the recess width RC3_ W is a distance from an end of the opening portion of the insulator 33 formed by the hole RH to a portion where the insulator 33 contacts the semiconductor 32. The distance between the holes RH provided adjacent to each other in the X direction is RH _ W1, and the distance between the holes RH provided adjacent to each other in the Y direction and the insulator 45 is RH _ W2. Therefore, RC3_ W, RH _ W1 and RH _ W2 have a relationship of ((RH _ W1)/2) < (RC3_ W) < (RH _ W2).
As shown in fig. 49 to 51, the insulator 34 is formed to fill the recess region RC3 and the hole RH. In addition, the recess region RC3 and the hole RH may not be completely filled. The opening portions of the holes RH of the insulators 50 and 51 may be closed by the insulators 34. In other words, an air gap may be formed in the recess region RC3 and the hole RH.
3 effects of the present embodiment
With the structure according to this embodiment, a semiconductor memory device with improved reliability can be provided. This effect will be described in detail with reference to fig. 52. Fig. 52 is a plan view of the memory cell transistor MC.
As shown in fig. 52, in the memory cell transistor MC according to the present embodiment, a cylindrical charge trapping layer 44 functioning as an FG surrounds the outer periphery of a conductor 41 functioning as a gate electrode with insulators 42 and 43 functioning as barrier insulating films interposed therebetween. A part of the outer periphery of the charge trapping layer 44 faces the semiconductor 32 functioning as the channel of the memory cell transistor MC through the insulator 45 functioning as a tunnel insulating film. Therefore, according to this embodiment, the memory cell transistor MC having the arc-shaped channel can be formed. Here, if the radius of the cylindrical conductor 41 is r1 and the radius of the cylindrical charge accumulation layer 44 is r2, r1< r2 are in the relationship. The length of the arc portion of the charge trapping layer 44 facing the arc-shaped channel is shorter than 2 × pi × r 2.
Here, the parasitic capacitance between the arc-shaped channel (semiconductor 32) and the charge trapping layer 44 is assumed to be C FG The parasitic capacitance between the charge accumulation layer 44 and the cylindrical conductor 41 is C CG . If a capacitor C is set FG And a capacitor C CG The coupling ratio of (b) is Cr, which can be expressed as Cr ═ C CG /(C FG +C CG ). By forming the memory cell transistor MC in an arc shape, the coupling ratio Cr can be increased. This can increase the total film thickness of the insulators 42 and 43, which are the block insulating films of the memory cell transistors MC. By increasing the thickness of the barrier insulating film, leakage of charges from the charge accumulating layer 44 to the conductor 41 can be suppressed. Further, the barrier insulating film can be made thicker, whereby the withstand voltage of the barrier insulating film of the memory cell transistor MC can be improved. This can improve the reliability of the memory cell transistor MC.
Furthermore, with the configuration of the present embodiment, the capacitance C can be controlled by controlling the recess width RC3 — W of the semiconductor 32 FG And (5) controlling. That is, the coupling ratio Cr can be controlled by the amount of recess of the channel (semiconductor 32).
Further, with the structure according to the present embodiment, the holes CH, RH, and DH having high aspect ratios can be processed together. The memory cell array 11 can be formed by selectively removing the sacrificial films in the holes CH, RH, and DH and repeating recess etching and recess filling. Therefore, the number of times of etching of the high aspect ratio holes in the memory cell array 11 can be reduced, and the processing of the memory cell array 11 can be easily performed.
4. Modifications and the like
The semiconductor memory device according to the above embodiment includes a1 st semiconductor (32) extending in a1 st direction (X direction) parallel to a substrate (30), a1 st conductor (41) extending in a2 nd direction (Z direction) perpendicular to the substrate, a1 st charge trapping layer (44) provided so as to surround the outer periphery of the 1 st conductor, a1 st insulator (42 or 43) provided between the 1 st conductor and the 1 st charge trapping layer so as to surround the 1 st conductor, a2 nd insulator (45) provided between the 1 st charge trapping layer and the 1 st semiconductor so as to surround the 1 st charge trapping layer, and a1 st Memory Cell (MC). A part of the outer periphery of the 2 nd insulator is in contact with the 1 st semiconductor. The 1 st memory cell includes a1 st conductor, a1 st semiconductor, a portion of a1 st charge trapping layer provided between the 1 st conductor and the 1 st semiconductor, a portion of a1 st insulator, and a portion of a2 nd insulator. By applying the above embodiment mode, a semiconductor memory device with improved reliability can be provided.
The embodiment is not limited to the above-described embodiment, and various modifications are possible.
The term "connected" in the above embodiments also includes a state in which the elements are indirectly connected with each other with another element such as a transistor or a resistor interposed therebetween.
Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.
Description of the reference numerals
1 … semiconductor memory device; 10 … memory core portion; 11 … memory cell array; row 12 … decoder; 13 … sense amplifier; 20 … peripheral circuit part; 21 … sequencer; 22 … voltage generation circuit; 30 … a semiconductor substrate; 31. 33-35, 40, 42, 43, 45, 50, 51 … insulators; 32. 36 … a semiconductor; 41. 52 … an electrical conductor; 44 … charge trapping layer; 55-57 … sacrificial films, AA … active region parts; recessed areas RC 1-RC 3 …; SC … ST1 linker.

Claims (8)

1. A semiconductor memory device, comprising:
a1 st semiconductor extending in a1 st direction parallel to the substrate;
a1 st conductor extending in a2 nd direction perpendicular to the substrate;
a1 st charge trapping layer provided so as to surround an outer periphery of the 1 st conductor;
a1 st insulator provided between the 1 st conductor and the 1 st charge trapping layer so as to surround the 1 st conductor;
a2 nd insulator provided between the 1 st charge trapping layer and the 1 st semiconductor so as to surround the 1 st charge trapping layer; and
the 1 st storage unit is used for storing the data,
a part of the outer periphery of the 2 nd insulator is in contact with the 1 st semiconductor,
the 1 st memory cell includes the 1 st conductor, the 1 st semiconductor, a part of the 1 st charge trapping layer provided between the 1 st conductor and the 1 st semiconductor, a part of the 1 st insulator, and a part of the 2 nd insulator.
2. The semiconductor storage device according to claim 1,
the other part of the outer periphery of the 2 nd insulator is in contact with the 3 rd insulator.
3. The semiconductor storage device according to claim 2,
the surface of the 1 st semiconductor in contact with the 3 rd insulator is curved.
4. The semiconductor memory device according to claim 1, further comprising:
a2 nd semiconductor provided above the 1 st semiconductor;
a2 nd charge trapping layer provided so as to surround the outer periphery of the 1 st conductor;
a 4 th insulator provided between the 1 st conductor and the 2 nd charge trapping layer so as to surround the 1 st conductor;
a 5 th insulator provided between the 2 nd charge trapping layer and the 2 nd semiconductor so as to surround the 2 nd charge trapping layer; and
the 2 nd storage unit is used for storing the data,
a part of the outer periphery of the 5 th insulator is in contact with the 2 nd semiconductor,
the 2 nd memory cell includes the 1 st conductor, the 2 nd semiconductor, a part of the 2 nd charge trapping layer provided between the 1 st conductor and the 2 nd semiconductor, a part of the 4 th insulator, and a part of the 5 th insulator.
5. The semiconductor memory device according to claim 4,
the diameter of the 1 st charge trapping layer is different from the diameter of the 2 nd charge trapping layer.
6. The semiconductor memory device according to claim 4,
a width of the 1 st semiconductor in a 3 rd direction intersecting the 1 st direction and the 2 nd direction is different from a width of the 2 nd semiconductor in the 3 rd direction.
7. The semiconductor memory device according to any one of claims 1 to 6, further comprising:
a2 nd semiconductor extending in the 2 nd direction;
a 3 rd charge trapping layer provided so as to surround the outer periphery of the 1 st conductor;
a 6 th insulator provided between the 1 st conductor and the 1 st charge trapping layer so as to surround the 1 st conductor;
a 7 th insulator provided between the 3 rd charge trapping layer and the 1 st semiconductor so as to surround the 3 rd charge trapping layer; and
a 3 rd storage unit for storing the data,
a part of the outer periphery of the 7 th insulator is in contact with the 1 st semiconductor;
the 3 rd memory cell includes the 2 nd conductor, the 1 st semiconductor, a part of the 3 rd charge trapping layer provided between the 2 nd conductor and the 1 st semiconductor, a part of the 6 th insulator, and a part of the 7 th insulator.
8. The semiconductor storage device according to claim 7,
between the 1 st charge trapping layer and the 3 rd charge trapping layer, there is a region having a 3-layer structure including the 2 nd insulator, the 1 st semiconductor, and the 7 th insulator.
CN202111001643.4A 2021-03-23 2021-08-30 Semiconductor memory device with a plurality of memory cells Pending CN115117084A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-048655 2021-03-23
JP2021048655A JP2022147421A (en) 2021-03-23 2021-03-23 Semiconductor memory

Publications (1)

Publication Number Publication Date
CN115117084A true CN115117084A (en) 2022-09-27

Family

ID=83325061

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111001643.4A Pending CN115117084A (en) 2021-03-23 2021-08-30 Semiconductor memory device with a plurality of memory cells

Country Status (4)

Country Link
US (1) US20220310647A1 (en)
JP (1) JP2022147421A (en)
CN (1) CN115117084A (en)
TW (1) TWI821718B (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556356B (en) * 2014-01-27 2016-11-01 旺宏電子股份有限公司 Three-dimensional memory and method of forming the same
US20150325585A1 (en) * 2014-05-12 2015-11-12 Macronix International Co., Ltd. Method for forming three-dimensional memory and product thereof
CN108305877B (en) * 2017-01-13 2020-09-25 上海新昇半导体科技有限公司 Back gate non-junction NAND flash memory and manufacturing method thereof
TWI737114B (en) * 2019-02-27 2021-08-21 王振志 Transistor, three dimensional memory device including such transistor and method of fabricating such memory device
US11069704B2 (en) * 2019-04-09 2021-07-20 Macronix International Co., Ltd. 3D NOR memory having vertical gate structures

Also Published As

Publication number Publication date
JP2022147421A (en) 2022-10-06
US20220310647A1 (en) 2022-09-29
TWI821718B (en) 2023-11-11
TW202238943A (en) 2022-10-01

Similar Documents

Publication Publication Date Title
US9893076B2 (en) Access transistor of a nonvolatile memory device and method for fabricating same
US9520485B2 (en) 3D independent double gate flash memory on bounded conductor layer
TWI445164B (en) Nonvolatile semiconductor memory device
US8791464B2 (en) Nonvolatile semiconductor memory device and method for manufacturing same
CN110931488B (en) semiconductor memory
US8643081B2 (en) Semiconductor memory device
CN111370425A (en) Semiconductor memory device and method of manufacturing semiconductor memory device
US10872902B2 (en) Semiconductor memory device
CN112117278B (en) Semiconductor memory device and method for manufacturing the same
US20130170303A1 (en) Nonvolatile memory device, method for operating the same, and method for fabricating the same
CN110880512A (en) Semiconductor memory device and method for manufacturing semiconductor memory device
US10790229B2 (en) Semiconductor memory device
CN110838319B (en) Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell
CN112510047A (en) Semiconductor memory device with a plurality of memory cells
TW202023036A (en) Semiconductor memory device
US20220262811A1 (en) Semiconductor storage device
US11538829B2 (en) Memory device with first switch and word line switches comprising a common control electrode and manufacturing method for the same
TWI821718B (en) semiconductor memory device
JP2022147746A (en) semiconductor storage device
CN114203709A (en) Semiconductor memory device and method of manufacturing the same
US7982244B2 (en) Semiconductor memory device and manufacturing method thereof
US20230298634A1 (en) Semiconductor memory device and method for manufacturing semiconductor memory device
US20230075852A1 (en) Semiconductor storage device and manufacturing method thereof
US20220302023A1 (en) Semiconductor device and manufacturing method thereof
US20230077151A1 (en) Semiconductor storage device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination