CN115117013A - Chip interconnection member and method for manufacturing the same - Google Patents

Abstract

The invention provides a chip interconnection member and a preparation method thereof, wherein the interconnection member comprises: a first conductive structure disposed between the first conductive pillar and the first interconnection conductive pad, and configured to enable the first conductive pillar and the first interconnection conductive pad to be welded to each other, and form a first conductive height after welding; a second conductive structure, disposed between the second conductive pillar and the second interconnection conductive pad, for welding the second conductive pillar and the second interconnection conductive pad to each other, and forming a second conductive height after welding; wherein the first conduction height is the same as the second conduction height; the problem of poor interconnection between the backflow solder balls with small diameters and the conductive pads when I/O pins with different sizes on the same chip are interconnected with the conductive pads on the interconnection carrier in the prior art is solved, and the electrical stability of chip packaging is guaranteed.

Description

Chip interconnection member and preparation method thereof

technical field

The invention relates to the technical field of chip packaging, in particular to a component suitable for chip interconnection and a preparation method thereof.

Background technique

In the prior art, I/O pins of different sizes are arranged on the same chip, and when preparing conductive pillars and solder bumps on the I/O pins, the same nucleation process of sputtering metal and electroplating are usually used. Conductive pillar process, resulting in the same overall height of the corresponding conductive pillars on the I/O pins and solder bumps and interconnection conductive pads, but in the subsequent high temperature reflow process, the same height of solder bumps formed under the action of surface tension spheres, resulting in the shrinkage of the solder balls in height; the larger the diameter of the solder bumps, the smaller the shrinkage of the formed spheres in the vertical direction, resulting in poor conduction between the solder balls formed by the smaller diameter solder bumps and the interconnection conductive pads, And the greater the difference between the cross-sectional areas of the chip I/O pins in the horizontal direction, the more serious the degree of poor conduction between the solder balls and the interconnecting conductive pads.

It can be seen that in the prior art, when I/O pins of different sizes on the same chip are interconnected with the conductive pads on the interconnect carrier, there is a problem of poor interconnection between the reflow solder balls with smaller diameters and the interconnection conductive pads.

SUMMARY OF THE INVENTION

In view of the deficiencies in the prior art, the chip interconnection member and the preparation method thereof provided by the present invention solve the problem that the diameter of I/O pins of different sizes on the same chip in the prior art is interconnected with the conductive pads on the interconnection carrier. The problem of poor interconnection between the smaller reflowed solder balls and the conductive pads.

In a first aspect, the present invention provides a chip interconnection member, which is used in the welding of a chip interconnection base and an interconnection carrier, wherein the chip interconnection base includes a first laminated metal layer, a second laminated metal layer, and a first conductive column. and a second conductive column, the interconnect carrier includes a first interconnect conductive pad corresponding to the first conductive column and a second interconnect conductive pad corresponding to the second conductive column. The cross-sectional area is larger than the cross-sectional area of the second conductive column, and the chip interconnection member includes: a first conduction structure, which is arranged between the first conductive column and the first interconnection conductive pad, and is used for making The conductive connection between the first conductive column and the first interconnection conductive pad, and the first conductive height is formed after welding; the second conductive structure is arranged between the second conductive column and the first conductive pad. Between two interconnected conductive pads, the second conductive column and the second interconnected conductive pad are used for conducting connection, and a second conduction height is formed after soldering; wherein, the second conduction The structure includes a compensating metal column for compensating the conduction height between the chip interconnection base and the second interconnection conductive pad, so that the first conduction height and the second conduction height are the same.

Optionally, the compensation metal column is arranged on the second conductive column.

Optionally, the second conduction structure further includes: a first welding body, disposed on the compensation metal column, for making the second conductive column conduct electricity with the second interconnection through the compensation metal column The pads are soldered to each other.

Optionally, the compensation metal column is disposed on the second interconnection conductive pad.

Optionally, the second conduction structure further includes: a second welding body, disposed on the compensation metal column, for making the second conductive column conduct electricity with the second interconnection through the compensation metal column The pads are soldered to each other.

Optionally, the material of the first conductive column includes copper; or/and the material of the second conductive column includes copper.

Optionally, the first conduction structure includes a solder ball structure; or/and the second conduction structure includes a solder ball structure.

Optionally, the solder ball structure is prepared by depositing tin-based alloy solder and high temperature reflow process.

In a second aspect, the present invention provides a method for preparing a chip interconnection member, the method comprising: providing a chip interconnection base, and coating photoresist on a first conductive column and a second conductive column of the chip interconnection base, obtaining a first interconnecting photoresist layer; exposing and developing the first interconnecting photoresist layer to obtain a first interconnecting mask layer having a first interconnecting opening, wherein the first interconnecting opening and the second interconnecting opening are The conductive pillars correspond; a compensation metal pillar is prepared at the first interconnection opening; photoresist is applied on the compensation metal pillar to obtain a second interconnection photoresist layer, and the second interconnection photoresist layer is subjected to Exposure and development to obtain a second interconnect mask layer having an array of interconnect openings, wherein the array of interconnect openings includes second interconnect openings corresponding to the first conductive pillars and third interconnect openings corresponding to the compensation metal pillars interconnecting openings; depositing solder at the second interconnecting openings and the third interconnecting openings, so that a first conductive structure is formed on the first conductive pillars and a first solder body is formed on the compensation metal pillars, A chip interconnect structure is obtained.

Optionally, providing a chip interconnection base includes: providing a carrier board and a silicon wafer including a plurality of chips, the carrier board is bonded to the passive surface of the silicon wafer by bonding glue, wherein the chips are It includes a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is greater than the cross-sectional area of the second built-in conductive pad; coating the active surface of the silicon wafer The photoresist obtains a first chip photoresist layer, and the first chip photoresist layer is exposed and developed to prepare a first chip mask layer with a first opening array, wherein the first opening array includes the same a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad; a laminated metal layer is prepared on the first chip mask layer; Coating photoresist on the metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to prepare a second chip mask layer with a second opening array, the The second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; at the third chip opening and the fourth chip opening Copper electroplating is carried out, and the chip interconnection base is obtained after the first conductive pillar and the second conductive pillar are prepared.

Optionally, electroplating copper at the opening of the third chip and the opening of the fourth chip to obtain the chip interconnection base after preparing the first conductive column and the second conductive column, comprising: placing the third chip on the third chip. The opening and the opening of the fourth chip are electroplated with copper, and after the first conductive pillar and the second conductive pillar are prepared, the mask layer of the second chip, the laminated metal layer and the mask layer of the first chip are cleaned and removed. Obtaining the chip interconnection matrix; or, electroplating copper at the third chip opening and the fourth chip opening, and after preparing the first conductive column and the second conductive column, retaining the second chip mask layer , stacking the metal layer and the first chip mask layer to obtain the chip interconnection base.

In a third aspect, the present invention provides a method for preparing a chip interconnection member, the method comprising: providing an interconnection carrier, and applying photoresist on the first interconnection conductive pad and the second interconnection conductive pad of the interconnection carrier to obtain a first interconnecting carrier photoresist layer; exposing and developing the first interconnecting carrier photoresist layer to obtain a first interconnecting carrier mask layer having a first interconnecting carrier opening, wherein the first interconnecting carrier opening is The second interconnection conductive pad corresponds to; a compensation metal column is prepared at the opening of the first interconnection carrier; photoresist is applied on the compensation metal column to obtain a second interconnection carrier photoresist layer, and the Two interconnected carrier photoresist layers are exposed and developed to obtain a second interconnected carrier mask layer with an interconnected carrier opening array, wherein the interconnected carrier opening array includes a second interconnected carrier corresponding to the first interconnected conductive pad opening and a third interconnection carrier opening corresponding to the compensation metal post; depositing solder at the second interconnection carrier opening and the third interconnection carrier opening to form a first conductive pad on the first interconnection conductive pad Through the structure, a compensation metal column and a second welding body are formed on the compensation metal column, and the first interconnection carrier photoresist layer and the first interconnection carrier mask layer are cleaned and removed to obtain a chip interconnection member.

Compared with the prior art, the present invention has the following beneficial effects:

In the present invention, through the first conduction structure and the second conduction structure, the conductive pillars with larger cross-sectional area on the chip interconnection base and the interconnection conductive pads on the interconnection carrier are connected to each other to form a first conduction height, so that the chips are interconnected with the base. The conductive column with the smaller cross-sectional area and the conductive pad on the interconnect carrier are connected to each other to form a second conduction height, and the first conduction height and the second conduction height are made the same, thereby solving the problem of existing In the technology, when I/O pins of different sizes on the same chip are connected to the interconnection conductive pads, the problem of poor interconnection between the reflow solder balls with smaller diameters and the interconnection conductive pads ensures the electrical reliability of the chip package.

Description of drawings

FIG. 1 is a schematic diagram of poor soldering between the I/O pins of different sizes on the same chip and the interconnection of the conductive pads on the interconnection carrier in the prior art;

FIG. 2 is a schematic structural diagram of a first chip interconnection component provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of an application scenario of a first chip interconnection component provided by an embodiment of the present invention;

FIG. 4 is a schematic flowchart of a method for preparing a chip interconnection substrate according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of bonding a carrier plate and a chip according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of preparing a first chip mask layer according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of preparing a laminated metal layer according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of preparing a second chip mask layer according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of preparing a first conductive column and a second conductive column according to an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a chip interconnection substrate provided by an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a second type of chip interconnection member provided by an embodiment of the present invention;

FIG. 12 is a schematic diagram of an application scenario of a second type of chip interconnection component provided by an embodiment of the present invention;

FIG. 13 is a schematic flowchart of a method for preparing a first chip interconnection member provided by an embodiment of the present invention;

14 is a schematic diagram of preparing a first interconnect photoresist layer on a chip interconnect substrate according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of preparing a first interconnect mask layer according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of preparing a compensation metal column according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of preparing a second interconnection mask layer according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of preparing a first conduction structure and a second solder bump according to an embodiment of the present invention;

FIG. 19 is a schematic flowchart of a method for preparing a second chip interconnection member provided by an embodiment of the present invention;

FIG. 20 is a schematic diagram of preparing a photoresist layer of a first interconnection carrier provided by an embodiment of the present invention;

21 is a schematic diagram of preparing a first interconnect carrier mask layer according to an embodiment of the present invention;

FIG. 22 is a schematic diagram of another preparation of a compensation metal column provided by an embodiment of the present invention;

FIG. 23 is a schematic diagram of preparing a second interconnect carrier mask layer according to an embodiment of the present invention.

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present application.

Before describing this embodiment, it is necessary to expand on the problems mentioned in the background technology: in the prior art, due to the special circuit design built into the chip, it is usually necessary to realize different current densities and/or different signal strengths on the same chip. Therefore, there will be I/O pins of different sizes on the same chip. As shown in FIG. 1a and FIG. The interconnecting conductive pads 13 are arranged on the interconnecting carrier 1, wherein the interconnecting conductive pads 13 can be designed as the interconnecting conductive pads 13a corresponding to the larger-sized solder bumps 12a on the chip 100 and smaller than those on the chip 100. The interconnected conductive pads 13b corresponding to the solder bumps 12b of the size, or the interconnected conductive pads on the interconnection carrier 1 are designed to be interconnected conductive pads 13a corresponding to the larger-sized solder bumps 12a on the chip 100 . After the solder bumps 12 on the chip 100 are in one-to-one correspondence with the interconnection conductive pads 13 on the interconnection carrier 1, the solder bumps are melted through a high-temperature reflow process, and the solder bumps form solder balls under the action of surface tension to form conductive pillars Alloy interconnect structure between 11 and interconnect conductive pad 13 . However, if there are conductive pillars 11 and solder bumps 12 of different sizes in the same chip, the conventional interconnection structure and fabrication process will result in poor soldering as shown in FIG. 2 . The reason is that: when preparing conductive pillars 11 and solder bumps 12 on I/O pins of different sizes on the chip, the chip is usually uniformly subjected to photolithography opening, deposition of laminated metal layers and copper electroplating processes. The time of the copper electroplating process is the same, so the height of the conductive pillar 11 and the height of the solder block 12 prepared on the corresponding positions of the I/O pins of different sizes are the same. In the high temperature reflow soldering, the solder block 12 will be in the A sphere is formed under the action of surface tension, and the ball diameter of the reflowed solder ball or the height of the reflowed solder ball is positively correlated with the horizontal cross-sectional area of the solder block. Good electrical interconnection, but the reflow solder balls formed by the smaller diameter solder bumps and the interconnection conductive pads cannot form a good interconnection structure, resulting in a large increase in the interconnection resistance between the smaller diameter solder balls and the interconnection conductive pads. If the same chip When the size of the cross-sectional area corresponding to different I/O pins is quite different, it may even cause the situation that the reflow solder ball with a smaller diameter cannot communicate with the interconnection conductive pad.

The interconnection carrier includes but is not limited to: package substrate, metal wiring layer structure (RDL), silicon carrier board with TSV conductive vias, bridge chips with TSV conductive vias, chip packages with electrical connection layers body, glass carrier with conductive vias, ceramic carrier with conductive vias.

In the first aspect, in order to solve the above problems, the present invention provides a chip interconnection member, which specifically includes the following embodiments:

Example 1

FIG. 2 is a schematic structural diagram of a first chip interconnection member provided by an embodiment of the present invention; as shown in FIG. 2 , the chip interconnection member is applied in the welding of a chip interconnection base and an interconnection carrier, wherein the chip interconnection base includes a first chip interconnection base. A stacked metal layer 22a, a first conductive pillar 24a, and a second stacked metal layer 22b, a second conductive pillar 24b, the interconnect carrier includes a first interconnect conductive pad corresponding to the first conductive pillar 24a and The second interconnection conductive pad corresponding to the second conductive column 24b, the cross-sectional area of the first conductive column 24a is larger than the cross-sectional area of the second conductive column 24b, and the chip interconnection member includes:

The first conduction structure is disposed between the first conductive pillar 24a and the first interconnected conductive pad, and is used for interconnecting the first conductive pillar 24a and the first interconnected conductive pad, and during soldering Then the first conduction height is formed;

The second conduction structure is disposed between the second conductive pillar 24b and the second interconnected conductive pad, and is used for interconnecting and welding the second conductive pillar 24b and the second interconnected conductive pad, and during soldering Then a second conduction height is formed;

Wherein, the first conduction height is the same as the second conduction height.

In the first implementation manner of this embodiment, the second conduction structure includes: a compensation metal column 32, which is arranged on the second conductive column 24b and is used to compensate the conduction height between the chip interconnection base and the interconnection carrier; The second welding body 35b is disposed on the compensation metal column 32, and is used for welding the second conductive column 24b to the second interconnection conductive pad through the compensation metal column 32.

Compared with the prior art, the beneficial effects of this embodiment are:

In this embodiment, as shown in FIG. 3 , a compensation metal column 32 with a certain height is prepared on the second conductive column 24 b with a smaller diameter, so that the first welding body 35 b corresponding to the compensation metal column 32 is formed. A good conductive interconnection structure is formed between the second interconnected solder balls 36b formed after high temperature reflow, the second conductive pillars 24b and the second interconnected conductive pads 13b; The first conductive structure forms a good conductive interconnection structure between the first interconnected solder balls 36a formed after high temperature reflow, the first conductive pillars 24a, and the first interconnected conductive pads 13a, so that the first conductive pillars are connected to all the conductive pads 13a. The welding height formed after the first interconnection conductive pad is welded is the same as the welding height formed after the second conductive column and the second interconnection conductive pad are welded, thereby solving the problem of different sizes of I/O pins on the same chip. The problem of poor interconnection between the smaller diameter reflow solder balls and the conductive pads when interconnecting with the conductive pads on the interconnection carrier.

In the second aspect, the present embodiment provides a method for preparing a chip interconnection substrate, and the specific process steps are as follows:

FIG. 4 is a schematic flowchart of a method for preparing a chip interconnection base provided by an embodiment of the present invention; as shown in FIG. 4 , the preparation method of the chip interconnection base specifically includes the following steps:

In step S101, a carrier board and a silicon wafer including a plurality of chips are provided, and the carrier board is bonded to the passive surface of the silicon wafer by bonding glue.

In this embodiment, as shown in FIG. 5 , the silicon wafer S1 includes a plurality of chips 100 , the active surface of the chip 100 includes a first built-in conductive pad 10 a and a second built-in conductive pad 10 b , and the first built-in conductive pad The cross-sectional area of the pad 10a is larger than the cross-sectional area of the second built-in conductive pad 10b; the active surface corresponds to the passive surface of the silicon wafer. The carrier C1 is connected to the passive surface of the silicon wafer S1 through the bonding glue F1; wherein, before the silicon wafer is pasted on the bonding glue, a thinning process needs to be performed.

Step S102, coating photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to prepare a first chip photoresist layer with a first opening array. The first chip mask layer.

It should be noted that, as shown in FIG. 6a, a layer of photoresist is applied on the active surface of the silicon wafer S1 to obtain the first chip photoresist layer 20a; wherein, hot pressing with an ultraviolet sensitizer can also be used. The dielectric film is used as a mask layer. As shown in FIG. 6b, the first chip photoresist layer 20a is exposed and developed through a photolithography process to obtain a first chip mask layer 20b having a first array of openings, wherein the first array of openings includes A first chip opening 211 corresponding to the first built-in conductive pad 10a and a second chip opening 212 corresponding to the second built-in conductive pad 10b.

In step S103, a laminated metal layer is prepared on the first chip mask layer.

In this embodiment, as shown in FIG. 7 , several stacked metal layers 22 are sputtered on the first chip mask layer 20b. In a specific stacked metal layer structure, the stacked metal layers The layer includes a sputtering metal barrier layer and a copper seed layer; the metal barrier layer includes Ti, Ni, Cu, Pd, Pt or Ti-W, and its function is to block the diffusion of copper atoms to the chip substrate.

Step S104, coating photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to prepare a second chip having a second opening array. Chip mask layer.

It should be noted that, as shown in FIG. 8a, a photoresist layer is coated on the laminated metal layer to obtain a second chip photoresist layer 23a;

As shown in FIG. 8b, the second chip photoresist layer 23a is exposed and developed through a photolithography process to obtain a second chip mask layer 23b having a second opening array, wherein the second opening array includes A third chip opening 221 corresponding to one chip opening 211 and a fourth chip opening 222 corresponding to the second chip opening 212 .

Further, the laminated metal layer 22 includes a laminated metal layer on the first opening array and a mask laminated metal layer outside the first opening array.

Step S105 , electroplating copper at the openings of the third chip and the openings of the fourth chip to prepare the first conductive pillar and the second conductive pillar to obtain the chip interconnection base.

In this embodiment, copper electroplating is performed at the third chip opening and the fourth chip opening, and the first conductive pillar and the second conductive pillar are prepared to obtain the chip interconnection base, including: The openings of the three chips and the openings of the fourth chip are electroplated with copper, and after the first conductive pillar and the second conductive pillar are prepared, the mask layer of the second chip, the laminated metal layer and the mask of the first chip are cleaned and removed. The film layer obtains the chip interconnection substrate.

Optionally, electroplating copper at the opening of the third chip and the opening of the fourth chip to obtain the chip interconnection base after preparing the first conductive column and the second conductive column, comprising: placing the third chip on the third chip. The opening and the opening of the fourth chip are electroplated with copper, and after the first conductive column and the second conductive column are prepared, the mask layer of the second chip, the laminated metal layer and the mask layer of the first chip are retained to obtain The chip interconnection substrate.

In this embodiment, as shown in FIGS. 8 to 9 , a copper electroplating process is performed on the stacked metal layers corresponding to the third chip opening 221 and the fourth chip opening 222 to prepare the first conductive pillars 24 a and the first conductive pillars 24 a and the fourth chip opening 222 . Two conductive pillars 24b. The height of the conductive pillars may be greater than or less than or equal to the height of the second chip mask layer 23b.

In the first method of the obtained chip interconnection base, as shown in FIG. 10a, the second chip mask layer 23b, the mask stack metal layer other than the first opening array, and the first chip mask layer 20b are sequentially cleaned and removed , to prepare a chip interconnection base P1 connected to the chip built-in conductive pads on the active surface of the chip, wherein the chip interconnection base P1 includes a laminated metal layer, a first conductive column 24a and a second conductive column 24b.

In the second method of the obtained chip interconnection base, as shown in FIG. 10b, copper is electroplated at the opening of the third chip and the opening of the fourth chip to prepare a first conductive column and a second conductive column, Different from the above-mentioned first method, the chip interconnection base P1' here does not need to remove the second chip mask layer, the mask stack metal layer and the first chip mask layer other than the first opening array, That is, the photoresist mask layer and the stacked metal layer together surround the first conductive pillar and the second conductive pillar.

In the second aspect, the present embodiment provides a method for preparing a chip interconnection member, and the specific process steps are as follows:

FIG. 11 is a schematic flowchart of a method for preparing a first chip interconnection member provided by an embodiment of the present invention; as shown in FIG. 11 , the preparation method of the chip interconnection member specifically includes the following steps:

Step S201 , providing a chip interconnection substrate P1, and coating photoresist on the first conductive pillar and the second conductive pillar of the chip interconnection substrate to obtain a first interconnection photoresist layer.

It should be noted that, as shown in FIG. 12 , the first interconnecting photoresist layer 30a is obtained by coating photoresist on the first conductive pillars 24a and the second conductive pillars 24b of the chip interconnection base; wherein, hot pressing can also be used. The dielectric film with UV photosensitive agent acts as a mask layer instead of the first interconnect photoresist layer 30a.

In this process step, as shown in FIG. 10b, photoresist is directly coated on the chip interconnection substrate P1', so as to achieve the purpose of saving photoresist material and simplifying the process flow.

Step S202 , exposing and developing the first interconnecting photoresist layer to obtain a first interconnecting mask layer having first interconnecting openings, wherein the first interconnecting openings correspond to the second conductive pillars.

As shown in FIG. 13, the first interconnection photoresist layer 30a is exposed and developed to obtain a first interconnection mask layer 30b having first interconnection openings 31, wherein the first interconnection openings 31 and the second conductive Column 24b corresponds.

Step S203, preparing a compensation metal column at the first interconnection opening.

As shown in FIG. 14 , a copper electroplating process is performed on the first interconnection opening 31 to obtain the compensation metal column 32 .

Step S204, coating photoresist on the compensation metal post to obtain a second interconnecting photoresist layer, exposing and developing the second interconnecting photoresist layer, to obtain a second interconnecting mask having an array of interconnecting openings Floor.

As shown in FIG. 15a, coating photoresist on the compensation metal column 32 to obtain a second interconnecting photoresist layer 33a;

As shown in FIG. 15b, the second interconnection photoresist layer 33a is exposed and developed to obtain a second interconnection mask layer 33b having an interconnection opening array; wherein the interconnection opening array includes and the first conductive pillars 24a. Corresponding second interconnection openings 341 and third interconnection openings 342 corresponding to the compensation metal pillars 32 .

Step S205, depositing solder on the second interconnection opening and the third interconnection opening, so that a first conduction structure is formed on the first conductive column and a first solder body is formed on the compensation metal column, A chip interconnect structure is obtained.

As shown in FIG. 16, solder is deposited on the second interconnection opening 341 and the third interconnection opening 342, so that a first conductive structure 35a is formed on the first conductive column 24a and a compensation metal column is formed on the first conductive column 24a. A first solder body 35b is formed on 32; after cleaning and removing the second interconnection mask layer 33b and the first interconnection mask layer 30b, a chip interconnection member as shown in FIG. 2 is obtained. Wherein, the solder includes tin-based alloy solder.

In this embodiment, when the chip interconnection member is prepared on the chip interconnection base P1 and then interconnected with the interconnection carrier, the following steps are further included:

As shown in FIGS. 2-3 , the first conductive structures and the first soldering bodies on the chip interconnection member are made to correspond one-to-one with the interconnection conductive pads on the interconnection carrier, wherein the first conductive structure 35a with a larger diameter is connected to The first solder bumps 35b with smaller diameters corresponding to the first interconnected conductive pads 13a correspond to the second interconnected conductive pads 13b. The high temperature reflow process melts the first conductive structure 35a and the first solder body 35b, and prepares the first interconnection solder ball 36a and the second interconnection solder ball 36b under the action of surface tension, so as to make the compensation metal pillar 32 and the second interconnection ball 36b. The solder balls 36b form the same bonding height as the bonding height of the first interconnecting solder balls 36a.

Embodiment 2

FIG. 17 is a schematic structural diagram of a second type of chip interconnection member provided in an embodiment of the present invention; as shown in FIG. 17 , the second conduction structure includes: a compensation metal column 42 disposed on the second interconnection conductive pad 13b , for compensating the second conduction height; the second welding body 43b is arranged on the compensation metal column 42 and is used for realizing the welding connection between the second conductive column and the compensation metal column.

Compared with the prior art, the beneficial effects of this embodiment are:

In this embodiment, it should be noted that, as shown in Figures 18a and 18b, by preparing a compensation metal column 42 with a certain height on the second interconnection conductive pad 13b with a smaller diameter in the interconnection carrier, the compensation The second interconnecting solder balls 44b formed after the corresponding second solder bumps 43b on the metal pillars 42 are formed after high temperature reflow and the second metal layer 22b, the second conductive pillars 24b, the compensation metal pillars 42 and the second interconnected conductive pads 13b. A good conductive interconnection structure is formed between; and the first interconnection solder ball 44a and the first stacked metal layer formed after high temperature reflow through the first conductive structure 43a prepared on the first interconnection conductive pad 13a with a larger diameter 22a, the first conductive pillar 24a, and the first interconnected conductive pad 13a to form a good conductive interconnection structure, so that the welding height formed by the first conductive pillar 24a and the first interconnected conductive pad 13a after soldering, The soldering height is the same as that of the second conductive pillar 24b and the second interconnection conductive pad 13b formed after soldering, thereby solving the problem that the diameters of I/O pins of different sizes on the same chip are relatively small when they are interconnected with the conductive pads on the interconnect carrier. Poor interconnection between small reflowed solder balls and conductive pads.

In the second aspect, the present embodiment provides a method for preparing a chip interconnection member, and the specific process steps are as follows:

FIG. 19 is a schematic flowchart of a method for preparing a second type of chip interconnection member provided by an embodiment of the present invention; as shown in FIG. 19 , the preparation method of the chip interconnection member specifically includes the following steps:

Step S301, providing an interconnection carrier, and coating photoresist on the first interconnection conductive pad and the second interconnection conductive pad of the interconnection carrier to obtain a first interconnection carrier photoresist layer;

As shown in FIG. 20, a layer of photoresist is applied on the base surface corresponding to the interconnection conductive pad on the interconnection carrier to obtain a first interconnection carrier photoresist layer 40a; wherein, the interconnection conductive pad includes a first interconnected conductive pad with a larger cross-sectional area. An interconnected conductive pad 13a and a second interconnected conductive pad 13b with a smaller cross-sectional area.

Step S302, exposing and developing the first interconnecting carrier photoresist layer to obtain a first interconnecting carrier mask layer having a first interconnecting carrier opening, wherein the first interconnecting carrier opening and the second interconnecting carrier are electrically conductive corresponding to the pad;

As shown in FIG. 21, the first interconnection carrier photoresist layer 40a is exposed and developed to form a first interconnection carrier mask layer 40b having a first interconnection carrier opening 41b; wherein the first interconnection carrier opening 41b is connected to the The second interconnection conductive pad 13b corresponds to;

Step S303, preparing a compensation metal column at the opening of the first interconnection carrier;

As shown in FIG. 22 , conductive metal is filled on the first interconnection carrier opening 41 b to prepare a compensation metal column 42 .

Step S304, coating photoresist on the compensation metal post to obtain a second interconnecting carrier photoresist layer, exposing and developing the second interconnecting carrier photoresist layer to obtain a second interconnecting carrier opening array. an interconnect carrier mask layer, wherein the array of interconnect carrier openings includes a second interconnect carrier opening corresponding to the first interconnect conductive pad and a third interconnect carrier opening corresponding to the compensation metal pillar;

As shown in FIG. 23a, a photoresist layer 40c is obtained by coating photoresist on the compensation metal pillars 42 to obtain a second interconnecting carrier photoresist layer 40c. As shown in FIG. 23b, exposure and development are performed on the second interconnected carrier photoresist layer 40c to obtain a second interconnected carrier mask layer 40d having an interconnected carrier opening array, wherein the interconnected carrier opening array includes A second interconnection carrier opening corresponding to an interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar.

Step S305, depositing solder on the second interconnection carrier opening and the third interconnection carrier opening, so that a first conduction structure is formed on the first interconnection conductive pad, and a compensation metal column is formed on the compensation metal column and the second welding body, cleaning and removing the second interconnection carrier mask layer and the first interconnection carrier mask layer to obtain a chip interconnection member.

In this embodiment, as shown in FIG. 23b, solder is deposited on the second interconnection carrier opening and the third interconnection carrier opening, so that a first conductive structure 43a is formed on the first interconnection conductive pad 13a And forming a second welding body 43b on the compensation metal post 42, cleaning and removing the second interconnect carrier mask layer and the first interconnect carrier mask layer, the chip interconnect structure shown in FIG. 17 is obtained.

The second interconnect carrier mask layer, the first interconnect carrier mask layer, the second chip mask layer, the mask stack metal layer in the non-conductive pillar area, and the first chip need to be cleaned and removed respectively on the chip interconnect substrate P1' mask layer.

In this embodiment, after the chip interconnection member is prepared on the interconnection carrier and interconnected with the chip interconnection base P1, the following steps are further included:

As shown in FIG. 18a, the first conductive pillars 24a on the chip interconnection base P1 are in one-to-one correspondence with the first conductive structures 43a on the chip interconnection member, and the second conductive pillars 24b on the chip interconnection base P1 are in a one-to-one correspondence with the chip interconnection member. The first solder bumps 43b are in one-to-one correspondence.

As shown in FIG. 18b, the high temperature reflow process melts the first conductive structure 43a and the second solder body 43b, and prepares the first interconnection solder ball 44a and the second interconnection solder ball 44b respectively under the action of surface tension, so that the compensation metal The post 42 and the second interconnection ball 44b form a bond height that is the same as the bond height of the first interconnection ball 44a.

It should be noted that, in this document, relational terms such as "first" and "second" etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these Any such actual relationship or sequence exists between entities or operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Claims (12)

1. A chip interconnection member, characterized in that, it is used in the welding of a chip interconnection base and an interconnection carrier, wherein the chip interconnection base comprises a first laminated metal layer and a second laminated metal layer, a first conductive column and a second conductive column, the interconnection carrier includes a first interconnected conductive pad corresponding to the first conductive column and a second interconnected conductive pad corresponding to the second conductive column, the transverse direction of the first conductive column is The cross-sectional area is greater than the cross-sectional area of the second conductive column, and the chip interconnection member includes: a first conduction structure, disposed between the first conductive column and the first interconnected conductive pad, and used to make conductive connection between the first conductive column and the first interconnected conductive pad, and forming a first conduction height after soldering; A second conduction structure is disposed between the second conductive column and the second interconnected conductive pad, and is used for conducting conductive connection between the second conductive column and the second interconnected conductive pad, and forming a second conduction height after soldering; Wherein, the second conduction structure includes a compensation metal column for compensating the conduction height between the chip interconnection base and the second interconnection conductive pad, so that the first conduction height and the second conduction height The turn-on height is the same. 2 . The chip interconnection structure of claim 1 , wherein the compensation metal column is disposed on the second conductive column. 3 . 3. The chip interconnection member according to claim 2, wherein the second conduction structure further comprises: The first welding body is disposed on the compensation metal column, and is used for welding the second conductive column and the second interconnection conductive pad to each other through the compensation metal column. 4 . The chip interconnection structure of claim 1 , wherein the compensation metal column is disposed on the second interconnection conductive pad. 5 . 5. The chip interconnection member according to claim 4, wherein the second conduction structure further comprises: A second welding body is disposed on the compensation metal column, and is used for welding the second conductive column and the second interconnection conductive pad to each other through the compensation metal column. 6 . The chip interconnection structure of claim 1 , wherein the material of the first conductive pillars comprises copper; or/and the material of the second conductive pillars comprises copper. 7 . 7 . The chip interconnection structure of claim 1 , wherein the first conduction structure comprises a solder ball structure; or/and the second conduction structure comprises a solder ball structure. 8 . 8 . The chip interconnection structure of claim 7 , wherein the solder ball structure is prepared by depositing tin-based alloy solder and a high temperature reflow process. 9 . 9. A method for preparing a chip interconnection member, wherein the method comprises: A chip interconnection base is provided, and photoresist is coated on the first conductive column and the second conductive column of the chip interconnection base to obtain a first interconnected photoresist layer; exposing and developing the first interconnection photoresist layer to obtain a first interconnection mask layer having a first interconnection opening, wherein the first interconnection opening corresponds to the second conductive pillar; preparing compensation metal pillars at the first interconnection opening; A second interconnected photoresist layer is obtained by coating photoresist on the compensation metal pillar, and the second interconnected photoresist layer is exposed and developed to obtain a second interconnected mask layer with an array of interconnected openings, wherein the interconnection opening array includes a second interconnection opening corresponding to the first conductive pillar and a third interconnection opening corresponding to the compensation metal pillar; Solder is deposited on the second interconnection opening and the third interconnection opening, so that a first conductive structure is formed on the first conductive pillar and a first solder body is formed on the compensation metal pillar to obtain chip interconnection member. 10. The method for preparing a chip interconnection member according to claim 9, wherein providing a chip interconnection substrate, comprising: A carrier board and a silicon wafer including a plurality of chips are provided, the carrier board is bonded to the passive surface of the silicon wafer by bonding glue, wherein the chip includes a first built-in conductive pad and a second built-in conductive pad pads, and the cross-sectional area of the first built-in conductive pad is greater than the cross-sectional area of the second built-in conductive pad; Coating photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to prepare a first chip with a first opening array a mask layer, the first opening array includes a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; Coating photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to prepare a second chip mask with a second opening array layer, the second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; Copper electroplating is performed at the third chip opening and the fourth chip opening, and the chip interconnection base is obtained after the first conductive column and the second conductive column are prepared. 11 . The method for preparing a chip interconnection member according to claim 10 , wherein copper electroplating is performed at the third chip opening and the fourth chip opening to prepare the first conductive column and the second conductive column. 12 . Then, the chip interconnection substrate is obtained, including: Electroplating copper at the opening of the third chip and the opening of the fourth chip, after preparing the first conductive pillar and the second conductive pillar, cleaning and removing the mask layer of the second chip, the laminated metal layer and the The first chip mask layer obtains the chip interconnection base; Or, electroplating copper at the opening of the third chip and the opening of the fourth chip, and after preparing the first conductive column and the second conductive column, keep the mask layer of the second chip, the laminated metal layer and all the The first chip mask layer obtains the chip interconnection base. 12. A method for preparing a chip interconnection member, wherein the method comprises: An interconnection carrier is provided, and photoresist is coated on the first interconnection conductive pad and the second interconnection conductive pad of the interconnection carrier to obtain a photoresist layer of the first interconnection carrier; exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer with a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad ; preparing compensation metal pillars at the first interconnection carrier openings; Coating photoresist on the compensation metal post to obtain a second interconnecting carrier photoresist layer, exposing and developing the second interconnecting carrier photoresist layer to obtain a second interconnecting carrier mask with an interconnecting carrier opening array a film layer, wherein the array of interconnection carrier openings includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar; Solder is deposited at the second interconnect carrier opening and the third interconnect carrier opening to form a first conduction structure on the first interconnect conductive pad, a compensation metal stud and a second on the compensation metal stud Soldering the body, cleaning and removing the photoresist layer of the first interconnection carrier and the mask layer of the first interconnection carrier to obtain a chip interconnection member.

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