CN115117013A - Chip interconnection member and method for manufacturing the same - Google Patents
Chip interconnection member and method for manufacturing the same Download PDFInfo
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- CN115117013A CN115117013A CN202210864407.3A CN202210864407A CN115117013A CN 115117013 A CN115117013 A CN 115117013A CN 202210864407 A CN202210864407 A CN 202210864407A CN 115117013 A CN115117013 A CN 115117013A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
The invention provides a chip interconnection member and a preparation method thereof, wherein the interconnection member comprises: a first conductive structure disposed between the first conductive pillar and the first interconnection conductive pad, and configured to enable the first conductive pillar and the first interconnection conductive pad to be welded to each other, and form a first conductive height after welding; a second conductive structure, disposed between the second conductive pillar and the second interconnection conductive pad, for welding the second conductive pillar and the second interconnection conductive pad to each other, and forming a second conductive height after welding; wherein the first conduction height is the same as the second conduction height; the problem of poor interconnection between the backflow solder balls with small diameters and the conductive pads when I/O pins with different sizes on the same chip are interconnected with the conductive pads on the interconnection carrier in the prior art is solved, and the electrical stability of chip packaging is guaranteed.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip interconnection component and a preparation method thereof.
Background
In the prior art, I/O pins with different sizes are arranged on the same chip, and when conductive posts and solder bumps are prepared on the I/O pins, the same metal sputtering nucleation layer process and conductive post electroplating process are usually adopted, so that the overall heights of the corresponding conductive posts on the I/O pins, the solder bumps and the interconnection conductive pads are consistent, but in the subsequent high-temperature reflow soldering process, the solder bumps with the same height form spheres under the action of surface tension, so that the solder balls shrink in height; the larger the diameter of the solder bump, the smaller the shrinkage of the formed sphere in the vertical direction, which results in poor conduction between the solder ball formed by the solder bump with smaller diameter and the interconnection conductive pad, and the larger the difference of the cross-sectional area of the chip I/O pin in the horizontal direction, the more serious the poor conduction between the solder ball and the interconnection conductive pad.
Therefore, when the I/O pins with different sizes on the same chip are interconnected with the conducting pads on the interconnection carrier in the prior art, the problem of poor interconnection between the reflow solder balls with smaller diameters and the interconnection conducting pads exists.
Disclosure of Invention
Aiming at the defects in the prior art, the chip interconnection component and the preparation method thereof provided by the invention solve the problem that poor interconnection exists between the backflow solder balls with smaller diameters and the conductive pads when I/O pins with different sizes on the same chip are interconnected with the conductive pads on the interconnection carrier in the prior art.
In a first aspect, the present invention provides a chip interconnection component, which is applied to a chip interconnection substrate and an interconnection carrier, wherein the chip interconnection substrate includes a first stacked metal layer and a second stacked metal layer, a first conductive pillar and a second conductive pillar, the interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive pillar and a second interconnection conductive pad corresponding to the second conductive pillar, a cross-sectional area of the first conductive pillar is greater than a cross-sectional area of the second conductive pillar, and the chip interconnection component includes: a first conductive structure, disposed between the first conductive pillar and the first interconnection conductive pad, for making conductive connection between the first conductive pillar and the first interconnection conductive pad, and forming a first conductive height after soldering; the second conduction structure is arranged between the second conductive pillar and the second interconnection conductive pad, and is used for conducting and connecting the second conductive pillar and the second interconnection conductive pad, and a second conduction height is formed after welding; the second conduction structure comprises a compensation metal column which is used for compensating the conduction height between the chip interconnection substrate and the second interconnection conduction pad, so that the first conduction height is the same as the second conduction height.
Optionally, the compensation metal pillar is disposed on the second conductive pillar.
Optionally, the second conduction structure further includes: and the first welding body is arranged on the compensation metal column and used for enabling the second conductive column to be mutually welded with the second interconnection conductive pad through the compensation metal column.
Optionally, the compensation metal pillar is disposed on the second interconnect conductive pad.
Optionally, the second conduction structure further includes: and the second welding body is arranged on the compensation metal column and used for enabling the second conductive column to be mutually welded with the second interconnection conductive pad through the compensation metal column.
Optionally, the material of the first conductive pillar comprises copper; or/and the material of the second conductive pillar comprises copper.
Optionally, the first conducting structure comprises a solder ball structure; and/or the second conducting structure comprises a solder ball structure.
Optionally, the solder ball structure is prepared by depositing tin-based alloy solder and a high temperature reflow process.
In a second aspect, the present invention provides a method for preparing a chip interconnection member, the method comprising: providing a chip interconnection substrate, and coating photoresist on the first conductive column and the second conductive column of the chip interconnection substrate to obtain a first interconnection photoresist layer; exposing and developing the first interconnection photoresist layer to obtain a first interconnection mask layer with a first interconnection opening, wherein the first interconnection opening corresponds to the second conductive column; preparing a compensation metal column at the first interconnection opening; coating photoresist on the compensation metal column to obtain a second interconnection photoresist layer, and exposing and developing the second interconnection photoresist layer to obtain a second interconnection mask layer with an interconnection opening array, wherein the interconnection opening array comprises a second interconnection opening corresponding to the first conductive column and a third interconnection opening corresponding to the compensation metal column; and depositing solder at the second interconnection opening and the third interconnection opening to form a first conduction structure on the first conductive column and a first welding body on the compensation metal column, so as to obtain the chip interconnection component.
Optionally, providing a chip interconnect substrate comprising: providing a carrier plate and a silicon wafer comprising a plurality of chips, wherein the carrier plate is bonded with the passive surface of the silicon wafer through bonding glue, the chips comprise a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is larger than that of the second built-in conductive pad; coating photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, and carrying out exposure and development on the first chip photoresist layer to obtain a first chip mask layer with a first opening array, wherein the first opening array comprises a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; coating photoresist on the laminated metal layer to obtain a second chip photoresist layer, and carrying out exposure and development on the second chip photoresist layer to obtain a second chip mask layer with a second opening array, wherein the second opening array comprises a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; and electroplating copper at the third chip opening and the fourth chip opening to obtain the first conductive column and the second conductive column, and then obtaining the chip interconnection substrate.
Optionally, the step of obtaining the chip interconnection substrate after preparing the first conductive pillar and the second conductive pillar by electroplating copper at the third chip opening and the fourth chip opening includes: electroplating copper at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, and then cleaning and removing the second chip mask layer, the laminated metal layer and the first chip mask layer to obtain the chip interconnection substrate; or, after copper is electroplated at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, the second chip mask layer, the laminated metal layer and the first chip mask layer are reserved to obtain the chip interconnection substrate.
In a third aspect, the present invention provides a method for manufacturing a chip interconnection member, the method comprising: providing an interconnection carrier, and coating photoresist on a first interconnection conductive pad and a second interconnection conductive pad of the interconnection carrier to obtain a first interconnection carrier photoresist layer; exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer with a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad; preparing a compensation metal column at the opening of the first interconnection carrier; coating photoresist on the compensation metal column to obtain a second interconnection carrier photoresist layer, and exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer with an interconnection carrier opening array, wherein the interconnection carrier opening array comprises a second interconnection carrier opening corresponding to the first interconnection conducting pad and a third interconnection carrier opening corresponding to the compensation metal column; and depositing solder at the second interconnection carrier opening and the third interconnection carrier opening to form a first conduction structure on the first interconnection conductive pad, forming a compensation metal column and a second welding body on the compensation metal column, and cleaning and removing the first interconnection carrier photoresist layer and the first interconnection carrier mask layer to obtain a chip interconnection member.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, through the first conduction structure and the second conduction structure, the conductive column with larger cross section area on the interconnected substrate of the chip and the interconnected conductive pad on the interconnected carrier are mutually connected to form a first conduction height, the conductive column with smaller cross section area on the interconnected substrate of the chip and the conductive pad on the interconnected carrier are mutually connected to form a second conduction height, and the first conduction height is the same as the second conduction height, so that the problem of poor interconnection between the backflow solder ball with smaller diameter and the interconnected conductive pad when I/O pins with different sizes on the same chip are connected with the interconnected conductive pad in the prior art is solved, and the electrical reliability of chip packaging is ensured.
Drawings
FIG. 1 is a schematic diagram illustrating the prior art of poor soldering between I/O pins of different sizes on the same chip and the interconnection of conductive pads on an interconnection carrier;
fig. 2 is a schematic structural diagram of a first chip interconnection component according to an embodiment of the present invention;
fig. 3 is a schematic view of an application scenario of a first chip interconnection component according to an embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a chip interconnection substrate according to an embodiment of the present invention;
fig. 5 is a schematic view illustrating a carrier and a chip being attached according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a process for fabricating a first chip mask layer according to an embodiment of the invention;
fig. 7 is a schematic diagram illustrating a method for forming a stacked metal layer according to an embodiment of the invention;
fig. 8 is a schematic diagram illustrating a mask layer for fabricating a second chip according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating the preparation of a first conductive pillar and a second conductive pillar according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a chip interconnection substrate according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a second chip interconnection component according to an embodiment of the present invention;
fig. 12 is a schematic view illustrating an application scenario of a second chip interconnection component according to an embodiment of the present invention;
fig. 13 is a schematic flow chart illustrating a method for manufacturing a first chip interconnection member according to an embodiment of the present invention;
FIG. 14 is a schematic view of a first interconnection photoresist layer formed on a chip interconnection substrate according to an embodiment of the present invention;
fig. 15 is a schematic diagram illustrating a first interconnect mask layer according to an embodiment of the present invention;
FIG. 16 is a schematic diagram illustrating a method for fabricating a compensation metal pillar according to an embodiment of the present invention;
fig. 17 is a schematic diagram illustrating a second interconnect mask layer according to an embodiment of the present invention;
fig. 18 is a schematic diagram illustrating a method for manufacturing a first conductive structure and a second solder bump according to an embodiment of the invention;
fig. 19 is a schematic flow chart illustrating a method for manufacturing a second chip interconnection member according to an embodiment of the present invention;
FIG. 20 is a schematic view of a photoresist layer for a first interconnect carrier according to an embodiment of the present invention;
fig. 21 is a schematic diagram illustrating a mask layer for fabricating a first interconnect carrier according to an embodiment of the invention;
FIG. 22 is a schematic view of another embodiment of the present invention for fabricating a compensation metal pillar;
fig. 23 is a schematic diagram illustrating a process of preparing a second interconnect carrier mask layer according to an embodiment of the invention.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Before describing the present embodiment, a description of the problems mentioned in the background art is needed: in the prior art, due to the special circuit design built in the chip, the transmission of different current densities and/or different signal strengths is generally required to be realized on the same chip, therefore, there are I/O pins with different sizes on the same chip, as shown in fig. 1a and 1b, a conductive pillar 11 electrically connected to the built-in conductive pad 10 of the chip 100, and a solder bump 12 disposed on the conductive pillar 11, an interconnection conductive pad 13 disposed on the interconnection carrier 1, wherein the interconnecting pads 13 can be designed to correspond to the larger size solder bumps 12a on the chip 100, the interconnecting pads 13a corresponding to the smaller size solder bumps 12b on the chip 100, or the interconnecting pads on the interconnecting carrier 1 are each designed as interconnecting pads 13a corresponding to the larger size solder bumps 12a on the chip 100. After the solder bumps 12 on the chip 100 correspond to the interconnection pads 13 on the interconnection carrier 1 one by one, the solder bumps are melted by a high-temperature reflow process, and the solder bumps form solder balls under the action of surface tension, thereby forming an alloy interconnection structure between the conductive posts 11 and the interconnection pads 13. However, if the conductive posts 11 and the solder bumps 12 of different sizes exist in the same chip, the conventional interconnection structure and manufacturing process may cause poor soldering as shown in fig. 2. The reason for this analysis is due to: when the conductive posts 11 and the solder bumps 12 are prepared on the I/O pins with different sizes on the chip, the photolithography opening, the deposition of the laminated metal layer and the copper electroplating process are generally uniformly performed on the chip, because the time of the copper electroplating process is consistent in the same time, the height of the conductive posts 11 and the height of the solder bumps 12 prepared at the corresponding positions of the I/O pins with different sizes are the same, in the high-temperature reflow soldering, the solder bumps 12 form spheres under the action of surface tension, the sphere diameter of the reflow solder balls or the height of the reflow solder balls is in positive correlation with the horizontal sectional area of the solder bumps, therefore, the reflow solder balls obtained from the solder bumps with larger diameters and the interconnection conductive pads can form good electrical interconnection, and the reflow solder balls formed from the solder bumps with smaller diameters and the interconnection conductive pads can not form good interconnection structures, which causes the interconnection resistance between the solder balls with smaller diameters and the interconnection conductive pads to be greatly increased, if the difference between the cross-sectional area sizes of the I/O pins on the same chip is large, the reflow solder balls with smaller diameters may not be connected to the interconnection pads.
The interconnected carrier includes but is not limited to: the chip package comprises a package substrate, a metal wiring layer structure (RDL), a silicon carrier plate with TSV (through silicon via) conductive through holes, a bridge chip with the TSV conductive through holes, a chip package body with an electric connection layer, a glass carrier plate with the TSV conductive through holes and a ceramic carrier plate with the TSV conductive through holes.
In a first aspect, to solve the above problems, the present invention provides a chip interconnection component, which specifically includes the following embodiments:
example one
Fig. 2 is a schematic structural diagram of a first chip interconnection component according to an embodiment of the present invention; as shown in fig. 2, the chip interconnection component is applied to the bonding of a chip interconnection substrate and an interconnection carrier, wherein the chip interconnection substrate includes a first stacked metal layer 22a, a first conductive pillar 24a, and a second stacked metal layer 22b, a second conductive pillar 24b, the interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive pillar 24a and a second interconnection conductive pad corresponding to the second conductive pillar 24b, a cross-sectional area of the first conductive pillar 24a is greater than a cross-sectional area of the second conductive pillar 24b, and the chip interconnection component includes:
a first conductive structure, disposed between the first conductive pillar 24a and the first interconnection conductive pad, for enabling the first conductive pillar 24a and the first interconnection conductive pad to be interconnected and welded, and forming a first conductive height after welding;
a second conductive structure, disposed between the second conductive pillar 24b and the second interconnection conductive pad, for enabling the second conductive pillar 24b and the second interconnection conductive pad to be interconnected and welded, and forming a second conductive height after welding;
wherein the first conduction height is the same as the second conduction height.
In a first implementation manner of this embodiment, the second conduction structure includes: the compensation metal column 32 is arranged on the second conductive column 24b and used for compensating the conduction height between the chip interconnection substrate and the interconnection carrier; and a second solder body 35b disposed on the compensation metal pillar 32 for soldering the second conductive pillar 24b and the second interconnection conductive pad to each other through the compensation metal pillar 32.
Compared with the prior art, the beneficial effect of this embodiment is:
in this embodiment, as shown in fig. 3, a compensation metal pillar 32 with a certain height is prepared on a second conductive pillar 24b with a smaller diameter, so that a good conductive interconnection structure is formed between a second interconnection solder ball 36b formed after a first solder body 35b corresponding to the compensation metal pillar 32 is reflowed at a high temperature and the second conductive pillar 24b and the second interconnection conductive pad 13 b; and a good conduction and interconnection structure is formed among the first interconnection solder ball 36a formed after high-temperature reflow by the first conduction structure prepared on the first conductive pillar 24a with a larger diameter and the first conductive pillar 24a and the first interconnection conductive pad 13a, so that the welding height formed after the first conductive pillar is welded with the first interconnection conductive pad is the same as the welding height formed after the second conductive pillar is welded with the second interconnection conductive pad, thereby solving the problem of poor interconnection between the reflow solder ball with a smaller diameter and the conductive pad when the I/O pins with different sizes on the same chip are interconnected with the conductive pad on the interconnection carrier.
In a second aspect, the present embodiment provides a method for preparing a chip interconnection substrate, which includes the following specific process steps:
FIG. 4 is a schematic flow chart illustrating a method for fabricating a chip interconnection substrate according to an embodiment of the present invention; as shown in fig. 4, the preparation method of the chip interconnection substrate specifically includes the following steps:
step S101, providing a carrier plate and a silicon wafer comprising a plurality of chips, wherein the carrier plate is bonded with the passive surface of the silicon wafer through bonding glue.
In the present embodiment, as shown in fig. 5, a plurality of chips 100 are included in a silicon wafer S1, an active surface of each chip 100 includes a first built-in pad 10a and a second built-in pad 10b, and a cross-sectional area of the first built-in pad 10a is larger than a cross-sectional area of the second built-in pad 10 b; corresponding to the active face is the passive face of the silicon wafer. The carrier plate C1 is connected with the passive surface of the silicon wafer S1 through bonding glue F1; wherein, thinning treatment is needed before the silicon wafer is pasted on the bonding glue.
Step S102, coating a photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, and exposing and developing the first chip photoresist layer to obtain a first chip mask layer having a first opening array.
As shown in fig. 6a, a first chip photoresist layer 20a is formed by coating a layer of photoresist on the active surface of a silicon wafer S1; wherein, the dielectric film with ultraviolet sensitizer can be used as mask layer by hot pressing. As shown in fig. 6b, the first chip photoresist layer 20a is exposed and developed through a photolithography process to obtain a first chip mask layer 20b having a first array of openings, wherein the first array of openings includes a first chip opening 211 corresponding to the first built-in conductive pad 10a and a second chip opening 212 corresponding to the second built-in conductive pad 10 b.
Step S103, a stacked metal layer is prepared on the first chip mask layer.
In this embodiment, as shown in fig. 7, a plurality of stacked metal layers 22 are sputtered on the first chip mask layer 20b, and in a specific stacked metal layer structure, the stacked metal layers include a sputtered metal barrier layer and a copper seed layer; the metal barrier layer comprises Ti, Ni, Cu, Pd, Pt or Ti-W and has the function of blocking copper atoms from diffusing to the chip substrate.
And step S104, coating photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer with a second opening array.
As shown in fig. 8a, a photoresist layer is coated on the stacked metal layer to obtain a second chip photoresist layer 23 a;
as shown in fig. 8b, the second chip photoresist layer 23a is exposed and developed through a photolithography process to obtain a second chip mask layer 23b having a second array of openings, which includes a third chip opening 221 corresponding to the first chip opening 211 and a fourth chip opening 222 corresponding to the second chip opening 212.
Further, the stacked metal layer 22 includes a stacked metal layer on the first array of openings and a mask stacked metal layer outside the first array of openings.
Step S105, copper is electroplated at the third chip opening and the fourth chip opening, and the chip interconnection substrate is obtained after the first conductive column and the second conductive column are prepared.
In this embodiment, the step of obtaining the chip interconnection substrate after preparing the first conductive pillar and the second conductive pillar by electroplating copper at the third chip opening and the fourth chip opening includes: and after copper is electroplated at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, cleaning and removing the second chip mask layer, the laminated metal layer and the first chip mask layer to obtain the chip interconnection substrate.
Optionally, the step of obtaining the chip interconnection substrate after preparing the first conductive pillar and the second conductive pillar by electroplating copper at the third chip opening and the fourth chip opening includes: and after copper is electroplated at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, the second chip mask layer, the laminated metal layer and the first chip mask layer are reserved to obtain the chip interconnection substrate.
In this embodiment, as shown in fig. 8 to 9, a copper plating process is performed on the stacked metal layers corresponding to the third chip opening 221 and the fourth chip opening 222 to obtain the first conductive pillar 24a and the second conductive pillar 24 b. The height of the conductive pillar may be greater than or less than or equal to the height of the second chip mask layer 23 b.
In a first mode of the obtained chip interconnection substrate, as shown in fig. 10a, the second chip mask layer 23b, the mask stack metal layer outside the first opening array, and the first chip mask layer 20b are sequentially cleaned and removed to prepare a chip interconnection substrate P1 coupled to the chip built-in conductive pad on the chip active surface, where the chip interconnection substrate P1 includes the stack metal layer, the first conductive pillar 24a, and the second conductive pillar 24 b.
In a second mode of the obtained chip interconnection substrate, as shown in fig. 10b, copper is electroplated at the third chip opening and the fourth chip opening to prepare a first conductive pillar and a second conductive pillar, which is different from the first mode, in that the chip interconnection substrate P1' does not need to remove the second chip mask layer, the mask stack metal layer and the first chip mask layer except for the first opening array, that is, the first conductive pillar and the second conductive pillar are surrounded by the photoresist mask layer and the stack metal layer.
In a second aspect, the present embodiment provides a method for manufacturing a chip interconnection component, which includes the following specific process steps:
fig. 11 is a schematic flow chart illustrating a method for manufacturing a first chip interconnection member according to an embodiment of the present invention; as shown in fig. 11, the method for manufacturing the chip interconnection member specifically includes the following steps:
step S201, providing a chip interconnection substrate P1, and coating a photoresist on the first conductive pillar and the second conductive pillar of the chip interconnection substrate to obtain a first interconnection photoresist layer.
As shown in fig. 12, a first interconnection photoresist layer 30a is obtained by coating photoresist on the first conductive pillars 24a and the second conductive pillars 24b of the chip interconnection substrate; in this case, a dielectric film with a uv sensitizer may be thermally pressed as a mask layer instead of the first interconnection resist layer 30 a.
The process steps can also be seen in fig. 10b, in which a photoresist is directly coated on the chip interconnection substrate P1' to save photoresist material and simplify the process flow.
Step S202, exposing and developing the first interconnection photoresist layer to obtain a first interconnection mask layer having a first interconnection opening, where the first interconnection opening corresponds to the second conductive pillar.
As shown in fig. 13, the first interconnection photoresist layer 30a is exposed and developed to obtain a first interconnection mask layer 30b having first interconnection openings 31, wherein the first interconnection openings 31 correspond to the second conductive pillars 24 b.
Step S203, preparing a compensation metal pillar at the first interconnection opening.
As shown in fig. 14, an electro-coppering process is performed at the first interconnect opening 31, resulting in a compensation metal pillar 32.
Step S204, coating photoresist on the compensation metal column to obtain a second interconnection photoresist layer, and exposing and developing the second interconnection photoresist layer to obtain a second interconnection mask layer with an interconnection opening array.
As shown in fig. 15a, a photoresist is coated on the compensation metal pillar 32 to obtain a second interconnection photoresist layer 33 a;
as shown in fig. 15b, the second interconnection photoresist layer 33a is exposed and developed to obtain a second interconnection mask layer 33b with an interconnection opening array; wherein the array of interconnect openings includes second interconnect openings 341 corresponding to the first conductive pillars 24a and third interconnect openings 342 corresponding to the compensation metal pillars 32.
Step S205, depositing solder at the second interconnection opening and the third interconnection opening, so as to form a first conductive structure on the first conductive pillar and a first solder body on the compensation metal pillar, thereby obtaining a chip interconnection component.
As shown in fig. 16, solder is deposited at the second interconnection opening 341 and the third interconnection opening 342, so that a first conductive structure 35a is formed on the first conductive pillar 24a and a first solder body 35b is formed on the compensation metal pillar 32; the cleaning removes the second interconnect masking layer 33b and the first interconnect masking layer 30b resulting in the chip interconnect structure as shown in fig. 2. Wherein the solder comprises a tin-based alloy solder.
In this embodiment, when the chip interconnection component is prepared on the chip interconnection substrate P1 and then interconnected with the interconnection carrier, the method further includes the following steps:
as shown in fig. 2 to 3, the first conductive structures and the first solder bodies on the chip interconnection component are respectively in one-to-one correspondence with the interconnection pads on the interconnection carrier, wherein the first conductive structures 35a with a larger diameter correspond to the first interconnection pads 13a, and the first solder bumps 35b with a smaller diameter correspond to the second interconnection pads 13 b. The high-temperature reflow process melts the first conductive structure 35a and the first solder body 35b, and prepares and obtains the first interconnection solder ball 36a and the second interconnection solder ball 36b under the action of surface tension, so that the soldering height formed by the compensation metal pillar 32 and the second interconnection solder ball 36b is the same as the soldering height of the first interconnection solder ball 36 a.
Example two
Fig. 17 is a schematic structural diagram of a second chip interconnection component according to an embodiment of the present invention; as shown in fig. 17, the second conductive structure includes: a compensation metal pillar 42 disposed on the second interconnection pad 13b for compensating the second conduction height; and a second welding body 43b disposed on the compensation metal pillar 42 for realizing the welding connection between the second conductive pillar and the compensation metal pillar.
Compared with the prior art, the beneficial effects of this embodiment are:
in this embodiment, as shown in fig. 18a and 18b, a compensation metal pillar 42 with a certain height is prepared on a second interconnection pad 13b with a smaller diameter in an interconnection carrier, so that a good conductive interconnection structure is formed between a second interconnection solder ball 44b formed after a second solder bump 43b corresponding to the compensation metal pillar 42 is reflowed at a high temperature and the second stacked metal layer 22b, the second conductive pillar 24b, the compensation metal pillar 42, and the second interconnection pad 13 b; and a good conduction interconnection structure is formed among the first interconnection solder ball 44a formed by the first conduction structure 43a prepared on the first interconnection conductive pad 13a with a larger diameter after high-temperature reflow, the first laminated metal layer 22a, the first conductive pillar 24a and the first interconnection conductive pad 13a, so that the soldering height formed by the first conductive pillar 24a and the first interconnection conductive pad 13a after soldering is the same as the soldering height formed by the second conductive pillar 24b and the second interconnection conductive pad 13b after soldering, thereby solving the problem of poor interconnection between the reflow solder ball with a smaller diameter and the conductive pad when the I/O pins with different sizes on the same chip are interconnected with the conductive pads on the interconnection carrier.
In a second aspect, the present embodiment provides a method for manufacturing a chip interconnection component, which includes the following specific process steps:
fig. 19 is a schematic flow chart illustrating a method for manufacturing a second chip interconnection member according to an embodiment of the present invention; as shown in fig. 19, the method for manufacturing the chip interconnection member specifically includes the steps of:
step S301, providing an interconnection carrier, and coating photoresist on a first interconnection conductive pad and a second interconnection conductive pad of the interconnection carrier to obtain a first interconnection carrier photoresist layer;
as shown in fig. 20, a first interconnection carrier photoresist layer 40a is formed by coating a photoresist layer on a base surface corresponding to the interconnection conductive pad on the interconnection carrier; the interconnection pads include a first interconnection pad 13a having a larger cross-sectional area and a second interconnection pad 13b having a smaller cross-sectional area.
Step S302, exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer having a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad;
as shown in fig. 21, the first interconnect carrier photoresist layer 40a is exposed and developed to form a first interconnect carrier mask layer 40b having first interconnect carrier openings 41 b; wherein the first interconnect carrier opening 41b corresponds to the second interconnect conductive pad 13 b;
step S303, preparing a compensation metal column at the opening of the first interconnection carrier;
as shown in fig. 22, a conductive metal is filled in the first interconnection carrier opening 41b to prepare a compensation metal pillar 42.
Step S304, coating a photoresist on the compensation metal pillar to obtain a second interconnection carrier photoresist layer, and exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer having an interconnection carrier opening array, wherein the interconnection carrier opening array includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar;
as shown in fig. 23a, a photoresist is coated on the offset metal stud 42 to obtain a second interconnect carrier photoresist layer 40 c. As shown in fig. 23b, exposing and developing on the second interconnection carrier photoresist layer 40c to obtain a second interconnection carrier mask layer 40d having an interconnection carrier opening array, wherein the interconnection carrier opening array includes second interconnection carrier openings corresponding to the first interconnection conductive pads and third interconnection carrier openings corresponding to the compensation metal pillars.
Step S305, depositing solder at the second interconnection carrier opening and the third interconnection carrier opening, so as to form a first conductive structure on the first interconnection conductive pad, form a compensation metal pillar and a second solder body on the compensation metal pillar, and cleaning and removing the second interconnection carrier mask layer and the first interconnection carrier mask layer to obtain a chip interconnection component.
In this embodiment, as shown in fig. 23b, solder is deposited at the second interconnection carrier opening and the third interconnection carrier opening, so that a first conductive structure 43a is formed on the first interconnection conductive pad 13a and a second solder 43b is formed on the compensation metal pillar 42, and after the second interconnection carrier mask layer and the first interconnection carrier mask layer are cleaned and removed, the chip interconnection component shown in fig. 17 is obtained.
When the chip interconnection substrate P1' is subjected to cleaning, the second interconnection carrier mask layer, the first interconnection carrier mask layer, the second chip mask layer, the mask laminated metal layer in the non-conductive column region and the first chip mask layer are respectively removed.
In this embodiment, when the chip interconnection component is prepared on the interconnection carrier and then interconnected with the chip interconnection substrate P1, the method further includes the following steps:
as shown in fig. 18a, the first conductive pillars 24a on the chip interconnection substrate P1 are in one-to-one correspondence with the first conductive structures 43a on the chip interconnection members, and the second conductive pillars 24b on the chip interconnection substrate P1 are in one-to-one correspondence with the first solder bumps 43b on the chip interconnection members.
As shown in fig. 18b, the high temperature reflow process melts the first conductive structure 43a and the second solder body 43b, and prepares a first interconnection solder ball 44a and a second interconnection solder ball 44b under the action of surface tension, so that the height of the solder formed by the compensation metal pillar 42 and the second interconnection solder ball 44b is the same as the height of the solder formed by the first interconnection solder ball 44 a.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (12)
1. A chip interconnection component, which is applied to a bonding of a chip interconnection substrate and an interconnection carrier, wherein the chip interconnection substrate includes a first stacked metal layer and a second stacked metal layer, a first conductive pillar and a second conductive pillar, the interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive pillar and a second interconnection conductive pad corresponding to the second conductive pillar, a cross-sectional area of the first conductive pillar is greater than a cross-sectional area of the second conductive pillar, and the chip interconnection component includes:
a first conductive structure, disposed between the first conductive pillar and the first interconnection conductive pad, for making conductive connection between the first conductive pillar and the first interconnection conductive pad, and forming a first conductive height after soldering;
the second conduction structure is arranged between the second conductive pillar and the second interconnection conductive pad, and is used for conducting and connecting the second conductive pillar and the second interconnection conductive pad, and a second conduction height is formed after welding;
the second conduction structure comprises a compensation metal column which is used for compensating the conduction height between the chip interconnection substrate and the second interconnection conduction pad, so that the first conduction height is the same as the second conduction height.
2. The chip interconnect structure of claim 1, wherein the offset metal stud is disposed on the second conductive stud.
3. The chip interconnect structure of claim 2, wherein the second conductive structure further comprises:
and the first welding body is arranged on the compensation metal column and used for enabling the second conductive column to be mutually welded with the second interconnection conductive pad through the compensation metal column.
4. The chip interconnect structure of claim 1, wherein the offset metal stud is disposed on a second interconnect conductive pad.
5. The chip interconnect structure of claim 4, wherein the second conductive structure further comprises:
and the second welding body is arranged on the compensation metal column and used for enabling the second conductive column to be mutually welded with the second interconnection conductive pad through the compensation metal column.
6. The chip interconnect structure of claim 1, wherein the material of the first conductive pillar comprises copper; or/and the material of the second conductive pillar comprises copper.
7. The chip interconnect structure of claim 1, wherein the first conductive structure comprises a solder ball structure; and/or the second conduction structure comprises a solder ball structure.
8. The chip interconnect structure of claim 7, wherein said solder ball structure is prepared by depositing a tin-based alloy solder and a high temperature reflow process.
9. A method of making a chip interconnect structure, the method comprising:
providing a chip interconnection substrate, and coating photoresist on the first conductive column and the second conductive column of the chip interconnection substrate to obtain a first interconnection photoresist layer;
exposing and developing the first interconnection photoresist layer to obtain a first interconnection mask layer with a first interconnection opening, wherein the first interconnection opening corresponds to the second conductive column;
preparing a compensation metal column at the first interconnection opening;
coating photoresist on the compensation metal column to obtain a second interconnection photoresist layer, and exposing and developing the second interconnection photoresist layer to obtain a second interconnection mask layer with an interconnection opening array, wherein the interconnection opening array comprises a second interconnection opening corresponding to the first conductive column and a third interconnection opening corresponding to the compensation metal column;
and depositing solder at the second interconnection opening and the third interconnection opening to form a first conduction structure on the first conductive column and a first welding body on the compensation metal column, so as to obtain the chip interconnection component.
10. The method of making a chip interconnect structure according to claim 9, wherein providing a chip interconnect substrate comprises:
providing a carrier plate and a silicon wafer comprising a plurality of chips, wherein the carrier plate is bonded with the passive surface of the silicon wafer through bonding glue, the chips comprise a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is larger than that of the second built-in conductive pad;
coating photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, and carrying out exposure and development on the first chip photoresist layer to obtain a first chip mask layer with a first opening array, wherein the first opening array comprises a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad;
preparing a laminated metal layer on the first chip mask layer;
coating photoresist on the laminated metal layer to obtain a second chip photoresist layer, and carrying out exposure and development on the second chip photoresist layer to obtain a second chip mask layer with a second opening array, wherein the second opening array comprises a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening;
and electroplating copper at the third chip opening and the fourth chip opening to obtain the first conductive column and the second conductive column, and then obtaining the chip interconnection substrate.
11. The method of manufacturing a chip interconnection member according to claim 10, wherein the step of obtaining the chip interconnection substrate after the first conductive pillar and the second conductive pillar are prepared by electroplating copper at the third chip opening and the fourth chip opening comprises:
electroplating copper at the third chip opening and the fourth chip opening to obtain a first conductive column and a second conductive column, and then cleaning and removing the second chip mask layer, the laminated metal layer and the first chip mask layer to obtain the chip interconnection substrate;
or, after copper is electroplated at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, the second chip mask layer, the laminated metal layer and the first chip mask layer are reserved to obtain the chip interconnection substrate.
12. A method of making a chip interconnect structure, the method comprising:
providing an interconnection carrier, and coating photoresist on a first interconnection conductive pad and a second interconnection conductive pad of the interconnection carrier to obtain a first interconnection carrier photoresist layer;
exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer with a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad;
preparing a compensation metal column at the opening of the first interconnection carrier;
coating photoresist on the compensation metal column to obtain a second interconnection carrier photoresist layer, and exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer with an interconnection carrier opening array, wherein the interconnection carrier opening array comprises a second interconnection carrier opening corresponding to the first interconnection conducting pad and a third interconnection carrier opening corresponding to the compensation metal column;
and depositing solder at the second interconnection carrier opening and the third interconnection carrier opening to form a first conduction structure on the first interconnection conductive pad, forming a compensation metal column and a second welding body on the compensation metal column, and cleaning and removing the first interconnection carrier photoresist layer and the first interconnection carrier mask layer to obtain a chip interconnection member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210864407.3A CN115117013A (en) | 2022-07-21 | 2022-07-21 | Chip interconnection member and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210864407.3A CN115117013A (en) | 2022-07-21 | 2022-07-21 | Chip interconnection member and method for manufacturing the same |
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| CN115117013A true CN115117013A (en) | 2022-09-27 |
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| CN202210864407.3A Pending CN115117013A (en) | 2022-07-21 | 2022-07-21 | Chip interconnection member and method for manufacturing the same |
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| Country | Link |
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| CN (1) | CN115117013A (en) |
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