CN115102525A

CN115102525A - Sense amplifier circuit and trigger

Info

Publication number: CN115102525A
Application number: CN202210813423.XA
Authority: CN
Inventors: 史丹丹; 巩启凡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-07-11
Filing date: 2022-07-11
Publication date: 2022-09-23
Also published as: WO2024011738A1

Abstract

The invention provides a sense amplifier circuit, comprising: a charging module configured to charge the set signal node and the reset signal node according to a clock signal; a sensing module configured to sense and amplify the differential input signal according to a clock signal; the sensing module comprises a first amplifying circuit, a second amplifying circuit and a cross jump transfer circuit which is connected between the first amplifying circuit and the second amplifying circuit in a cross mode. The cross jump transfer circuit is used for transferring an effective signal of a newly started amplifying circuit to another amplifying circuit when induction is completed and a differential input signal jumps, so that a set signal/reset signal is kept unchanged, the stability and accuracy of output of the amplifier are improved, and when the cross jump transfer circuit is applied to a trigger, data sampling is fast and energy consumption is low.

Description

Sense amplifier circuit and trigger

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a sense amplifier circuit and a trigger.

Background

A Flip-Flop (FF) is one of basic logic unit circuits constituting a digital system such as a high-speed circuit system. A Flip-Flop (FF) is one of the basic logic unit circuits that constitute a digital system. The switching circuit has a triggering and switching characteristic and can be switched between two stable states under the action of an input signal. The performance of flip-flops has a significant impact on the performance of digital systems, particularly high speed digital systems.

The existing triggers are various in types and have characteristics.

A Transmission Gate Flip-Flop (TGFF) is a kind of master-slave two-phase clock Flip-Flop, and is formed by connecting a master latch sensitive to a low level and a slave latch sensitive to a high level in tandem, and if the setup time is not sufficient, data cannot be stably latched by the Flip-Flop on the rising edge of the clock signal CLK.

The Pulse Triggered Flip Flop (PTFF) well improves the disadvantage of long TGFF setup time, but requires an additional circuit to generate a clock tree, which increases power consumption and area overhead.

Semi-Dynamic Flip-Flop (SDFF), although having a short D-Q delay, does not have the capability to accommodate clock skew and time borrowing.

The sense amplifier based flip-flop is composed of a master stage of a fast differential sense amplifier and a slave stage of an SR latch, has small setup time and hold time, is relatively free from the problems, and is a solution suitable for low supply voltage. The differential sense amplifier in the prior art has the problems of more charge and discharge nodes and easy data acquisition error.

Therefore, a trigger with high sensitivity, high stability and low power consumption is needed.

Disclosure of Invention

In view of the above problems, the present invention provides a sense amplifier circuit comprising:

a charging module configured to charge the set signal node and the reset signal node according to a clock signal; a sensing module coupled to the charging module and configured to sense and amplify a differential input signal according to a clock signal; the sensing module comprises a first amplifying circuit, a second amplifying circuit and a cross jump transfer circuit which is connected between the first amplifying circuit and the second amplifying circuit in a cross mode; the cross-transition transfer circuit comprises a first transfer circuit and a second transfer circuit; the first transfer circuit is used for transferring the effective signal of the second amplifying circuit to the first amplifying circuit when the induction is finished and the differential input signal generates a first jump, so that the setting signal of the setting signal node and the reset signal of the reset signal node are kept unchanged; the second transfer circuit is used for transferring the effective signal of the first amplifying circuit to the second amplifying circuit when the induction is finished and the differential input signal generates second jump, so that the setting signal of the setting signal node and the reset signal of the reset signal node are kept unchanged.

Further, the first amplifying circuit comprises a first input signal amplifying circuit and a first clock signal sensing amplifying circuit which are connected in series; the second amplifying circuit comprises a second input signal amplifying circuit and a second clock signal sensing amplifying circuit which are connected in series; the second clock signal sensing amplifying circuit is connected with the first input signal amplifying circuit through a first transfer circuit; the first clock signal sensing amplifying circuit and the second input signal amplifying circuit are connected through a second transfer circuit.

Furthermore, the first transfer circuit is connected with the first input signal amplifying circuit in parallel, a first end of the first transfer circuit and a first end of the first input signal amplifying circuit are both connected with a set signal node, and a second end of the first transfer circuit and a second end of the first input signal amplifying circuit are both connected with a first end of the first clock signal sensing amplifying circuit; the control end of the first transfer circuit is connected with the second end of the second clock signal sensing amplifying circuit; the second transfer circuit is connected with the second input signal amplifying circuit in parallel, a first end of the second transfer circuit and a first end of the second input signal amplifying circuit are both connected with a reset signal node, and a second end of the second transfer circuit and a second end of the second input signal amplifying circuit are both connected with a first end of the second clock signal sensing amplifying circuit; the control end of the second transfer circuit is connected with the second end of the first clock signal sensing amplifying circuit.

Further, the differential input signal comprises an original data signal and an inverted data signal; the first amplifying circuit receives an original data signal, is used for conducting in an induction stage and pulls down a setting signal to be a low level through a first pull-down path; the second amplifying circuit receives the inverted data signal and is used for conducting in the induction stage and pulling down the reset signal to be low level through the second pull-down path.

Further, the first amplifying circuit further comprises a first grounding amplifying circuit; the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first grounding amplifying circuit are sequentially connected in series, a first end of the first input signal amplifying circuit is connected with a set signal node, and a second end of the first grounding amplifying circuit is grounded; the control end of the first grounding amplification circuit is connected with the reset signal node and is used for switching on or switching off under the action of a reset signal; the second amplifying circuit further comprises a second grounding amplifying circuit; the first input signal amplifying circuit, the second clock signal sensing amplifying circuit and the second grounding amplifying circuit are sequentially connected in series, the first end of the second input signal amplifying circuit is connected with the reset signal node, and the second end of the second grounding amplifying circuit is grounded; and the control end of the second grounding amplification circuit is connected with the setting signal node and is used for switching on or switching off under the action of the setting signal.

Further, the charging module comprises a first charging circuit and a second charging circuit; the first charging circuit is used for charging the setting signal node according to the clock signal; the second charging circuit is used for charging the reset signal node according to the clock signal; the first ends of the first charging circuit and the second charging circuit are both connected with a power supply; the second end of the first charging circuit is connected with the sensing module through a signal node; the second end of the second charging circuit is connected with the sensing module through a reset signal node.

Further, the charging module further comprises a first signal maintaining circuit and a second signal maintaining circuit; the first signal maintaining circuit is connected with the first charging circuit in parallel and is connected with the reset signal node; the second signal maintaining circuit is connected with the second charging circuit in parallel and is connected with a setting signal node; the first signal maintaining circuit is used for maintaining the state of the set signal when the induction is finished and the differential input signal generates second jumping; the second signal maintaining circuit is used for maintaining the state of the reset signal when the sensing is finished and the differential input signal generates a first transition.

Further, the first charging circuit includes a first switching unit, and the first signal maintaining circuit includes a second switching unit; the first switch unit is connected with the second switch unit in parallel; the first end of the first switch unit is connected with the power supply, and the second end of the first switch unit is connected with the signal node; the first end of the second switch unit is connected with the power supply, and the second end of the second switch unit is connected with the signal node; the control end of the first switch unit is used for receiving a clock signal; the control end of the second switch unit is used for receiving a reset signal of the reset signal node; the second charging circuit includes a fourth switching unit; the second signal maintaining circuit includes a third switching unit; the third switching unit is connected with the fourth switching unit in parallel; the first end of the third switching unit is connected with the power supply, and the second end of the third switching unit is connected with the setting signal node; the first end of the fourth switch unit is connected with the power supply, and the second end of the fourth switch unit is connected with the signal node; the control end of the fourth switching unit is used for receiving a clock signal; the control terminal of the third switching unit is used for receiving a setting signal for setting the signal node.

Further, the first input signal amplifying circuit includes a first switching device; the first transfer circuit includes a seventh switching device; the first end of the first switching device and the first end of the seventh switching device are both connected with a set signal node; the second end of the first switching device and the second end of the seventh switching device are both connected with the first end of the first clock signal sensing amplifying circuit; the control end of the seventh switching device is connected with the second end of the second clock signal sensing amplifying circuit; the second input signal amplifying circuit includes a second switching device; the second transfer circuit includes an eighth switching device; the first end of the second switching device and the first end of the eighth switching device are both connected with a reset signal node; a second end of the second switching device and a second end of the eighth switching device are both connected with a first end of the second clock signal sensing amplifying circuit; the control end of the eighth switching device is connected with the second end of the first clock signal sensing amplifying circuit; the control end of the first switching device is used for receiving an original data signal; the control terminal of the second switching device is used for receiving the inverted data signal.

Further, the first clock signal sense amplifying circuit includes a third switching device; the first end of the third switching device is connected with the second end of the first switching device; the second end of the third switching device is connected with the first end of the first grounding amplification circuit; the control end of the third switching device is used for receiving a clock signal; the second clock signal sensing amplifying circuit comprises a fourth switching device; the first end of the fourth switching device is connected with the second end of the second switching device; a second end of the fourth switching device is connected with a second end of the second grounding amplification circuit; the control terminal of the fourth switching device is used for receiving the clock signal.

Further, the first ground amplifying circuit includes a fifth switching device; a first end of the fifth switching device is connected with a second end of the third switching device; a second end of the fifth switching device is grounded; the control end of the fifth switching device is used for receiving a reset signal of the reset signal node; the second ground amplifying circuit includes a sixth switching device; a first end of the sixth switching device is connected with a second end of the fourth switching device; a second end of the sixth switching device is grounded; the control terminal of the sixth switching device is used for receiving a setting signal of the setting signal node.

The present invention also provides a flip-flop comprising:

the sense amplifier circuit and latch described above; the latch is to receive a clock signal, a differential input signal, and a set signal from the sense amplifier circuit and latch a target data signal.

Further, the latch comprises a charge and discharge circuit and a feedback circuit; the charging and discharging circuit receives a clock signal, a differential input signal and a setting signal and outputs a target data signal; and the feedback circuit receives the target data signal and the clock signal and latches the target data signal when the clock signal is invalid.

Further, the charge and discharge circuit comprises a fifth switching unit, a ninth switching device, a tenth switching device and an eleventh switching device which are connected in series in sequence; the first end of the fifth switching unit is connected with the power supply, and the second end of the fifth switching unit is connected with the first end of the ninth switching device; the control end of the fifth switch unit is used for receiving a setting signal; the differential input signal comprises an original data signal and an inverted data signal; the control end of the ninth switching device is used for receiving the inverted data signal; a second terminal of the ninth switching device is connected with a first terminal of a tenth switching device; the control end of the tenth switching device is used for receiving the clock signal; a second terminal of the tenth switching device is connected to a first terminal of the eleventh switching device; a second terminal of the eleventh switching device is grounded; the control end of the eleventh switching device is used for receiving a setting signal; the second end of the fifth switching unit is used for outputting a target data signal; the fifth switching unit and the eleventh switching device are configured such that at most one of them is turned on at the same time.

Further, the feedback circuit comprises a sixth switching unit, a seventh switching unit, a twelfth switching device and an inverter which are sequentially connected in series; the first end of the sixth switching unit is connected with the power supply; the second end of the sixth switching unit is connected with the first end of the seventh switching unit; the input end of the reverser receives the target data signal, and the output end of the reverser is connected with the control end of the sixth switching unit; the second end of the seventh switching unit is connected with the first end of the twelfth switching device; the control end of the seventh switching unit is used for receiving a clock signal; a second end of the twelfth switching device is connected to a second end of the tenth switching unit; the control end of the twelfth switching device is connected with the output end of the inverter; the sixth switching unit and the twelfth switching device are configured such that at most one of them is turned on at the same time.

The sensing amplifier circuit and the trigger provided by the invention can avoid mutual interference of currents on two sides of the differential structure, improve the stability and accuracy of the output of the amplifier, and have the advantages of fast data sampling and low energy consumption when being applied to the trigger. Furthermore, by adopting the latch optimized by the invention, the number of charge and discharge nodes can be reduced, the energy consumption is further reduced, and the efficiency is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of an overall structure of a sense amplifier circuit according to an embodiment of the invention;

FIG. 2a is a schematic diagram of a circuit structure of a sense amplifier circuit according to an embodiment of the present invention;

FIG. 2b is a schematic diagram of a circuit configuration of a secondary of a flip-flop according to an embodiment of the present invention;

FIG. 3a is a schematic diagram of a current path during a sense phase of a sense amplifier circuit according to an embodiment of the present invention;

FIG. 3b illustrates a current path schematic of a transition phase of a sense amplifier circuit according to an embodiment of the present invention;

figure 4 shows a SAFF structure schematic according to the prior art;

FIG. 5 shows a schematic diagram of a main stage fast differential sense amplifier of a SAFF according to the prior art;

fig. 6 shows a schematic diagram of a secondary latch of an SAFF according to the prior art;

fig. 7 illustrates signal waveforms of an SAFF according to the prior art;

fig. 8 illustrates a graph comparing the set signal pull down speed of a SAFF according to an embodiment of the present invention with a SAFF of the prior art;

fig. 9 shows a comparative illustration of the current mutual interference effect of the SAFF according to an embodiment of the present invention and the SAFF of the prior art.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a sense amplifier circuit, including: the device comprises a charging module and a sensing module. A charging module configured to charge the set signal node and the reset signal node according to a clock signal; a sensing module coupled to the charging module and configured to sense and amplify the differential input signal according to a clock signal; the sensing module comprises a first amplifying circuit, a second amplifying circuit and a cross jump transfer circuit which is connected between the first amplifying circuit and the second amplifying circuit in a cross mode; the cross-transition transfer circuit comprises a first transfer circuit and a second transfer circuit; the first transfer circuit is used for transferring an effective signal of the second amplifying circuit to the first amplifying circuit when induction is completed and a differential input signal generates first jump, so that a setting signal of a setting signal node and a reset signal of a reset signal node are kept unchanged, further, the setting signal of the setting signal node continues to discharge through a pull-down path in an induction stage, and the reset signal of the reset signal node continues to charge through a pull-up path of the charging module; the second transfer circuit is used for transferring the effective signal of the first amplifying circuit to the second amplifying circuit when the induction is completed and the differential input signal generates second jump, so that the setting signal of the setting signal node and the reset signal of the reset signal node are kept unchanged, further, the reset signal of the reset signal node continues to discharge through a pull-down path in the induction stage, and the setting signal of the setting signal node continues to charge through a pull-up path of the charging module. The charging module and the sensing module are connected through a setting signal node and a reset signal node.

Specifically, the first transition refers to a transition of an original data signal of the differential input signal from an active signal (e.g., high level) to an inactive signal (e.g., low level). The second transition refers to a transition of the inverted data signal of the differential input signal from the active signal to the inactive signal. Wherein the original data signal and the inverted data signal are a set of complementary signals.

Illustratively, the Sense Amplifier circuit according to the embodiment of the present invention is implemented as a single-ended high-speed low-power consumption Sense Amplifier (SA), specifically, an improved NMOS (N-Metal-Oxide-Semiconductor) Sense Amplifier. The modular structure of the sense amplifier circuit and the corresponding operation are explained in detail below.

As shown in fig. 1 and fig. 2a, the charging module of the sense amplifier circuit includes a first charging circuit and a second charging circuit; the first charging circuit is used for charging the setting signal node according to a clock signal (CLK); the second charging circuit is used for charging the reset signal node according to the clock signal (CLK).

The charging module further comprises a first signal maintaining circuit and a second signal maintaining circuit. The first signal maintaining circuit is connected with the first charging circuit in parallel, connected with the reset signal node and used for maintaining a set signal state when sensing is completed and a differential input signal generates a first jump; the second signal maintaining circuit is connected with the second charging circuit in parallel, connected with the setting signal node and used for maintaining the state of the reset signal when the sensing is finished and the differential input signal generates a second jump.

As shown in fig. 1 and fig. 2a, the sensing module includes two symmetrically coupled amplifying circuits, namely a first amplifying circuit and a second amplifying circuit.

The first amplifying circuit comprises a first input signal amplifying circuit and a first clock signal sensing amplifying circuit which are connected in series; the second amplifying circuit comprises a second input signal amplifying circuit and a second clock signal sensing amplifying circuit which are connected in series; the second clock signal sensing amplifying circuit is connected with the first input signal amplifying circuit through the first transfer circuit; the first clock signal sensing amplifying circuit and the second input signal amplifying circuit are connected through a second transfer circuit. The first input signal amplifying circuit and the second input signal amplifying circuit are used for receiving differential input signals.

The differential input signal includes an original data signal (signal D) and an inverted data signal (DB), which is a complementary signal of the original data signal. Without loss of generality, the first input signal amplification circuit is used to trigger an action in response to the original data signal (signal D). The second input signal amplifying circuit is used for responding to an inverted data signal (signal DB, which is an inverted signal of an original data signal) to trigger action. The inverse data signal DB is an inverse signal of the original data signal D. For example, when the original data signal is a high level signal, the inverted data signal is a low level signal; when the original data signal is a low level signal, the inverted data signal is a high level signal.

In the embodiment of the present invention, the circuit acting in response to the corresponding signal means: a switching device or a switching unit in the circuit is turned on or off in response to a specified electrical signal. Specifically, when the specified electrical signal is an active signal, the corresponding switching device or switching unit is turned on. For example, for a high-level triggered switch unit or switch device, when a high-level signal is received, it is triggered to conduct. The high level signal is an active signal for the switching cell or switching device.

The first amplifying circuit further comprises a first grounding amplifying circuit; the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first grounding amplifying circuit are sequentially connected in series, the first end of the first input signal amplifying circuit is connected with a set signal node, the second end of the first input signal amplifying circuit is connected with the first end of the first clock signal sensing amplifying circuit, the second end of the first clock signal sensing amplifying circuit is connected with the second end of the first grounding amplifying circuit, and the second end of the first grounding amplifying circuit is grounded; the first grounding amplifying circuit is connected with the reset signal node and used for being switched on or switched off under the action of a reset signal; the second amplifying circuit further comprises a second grounding amplifying circuit; the second input signal amplifying circuit, the second clock signal sensing amplifying circuit and the second grounding amplifying circuit are sequentially connected in series; the second end of the second input signal amplifying circuit is connected with the setting signal node, the second end of the second input signal amplifying circuit is connected with the first end of the second clock signal sensing amplifying circuit, the second end of the second clock signal sensing amplifying circuit is connected with the second end of the first grounding amplifying circuit, and the second end of the second grounding amplifying circuit is grounded; and the control end of the second grounding amplifying circuit is connected with the setting signal node and is used for being switched on or switched off under the action of the setting signal.

The first amplifying circuit receives an original data signal, is used for conducting in a sensing stage, and pulls down a setting signal to be a low level through a first pull-down path. The second amplifying circuit receives the inverted data signal and is used for conducting in the induction stage and pulling down the reset signal to be low level through the second pull-down path.

The first charging circuit, the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first grounding amplifying circuit are sequentially connected in series; the second charging circuit, the second input signal amplifying circuit, the second clock signal sensing amplifying circuit and the second grounding amplifying circuit are sequentially connected in series.

In the embodiment of the invention, the cross jump transfer branch can always discharge (pull down) through the original pull-down path in the jump process of the setting signal or the reset signal, the efficiency is high, the power consumption is low, and the error output caused by the jump of the differential input signal can be avoided.

The sensing stage is completed, that is, when the original data signal is at a high level, the setting signal is already pulled down to a low level, that is, a logic "0" signal, and the reset signal is already pulled up to a high level, that is, a logic "1" signal; alternatively, when the original data signal is at a low level, the set signal has been pulled up to a high level, i.e., a logic "1" signal, and the reset signal has been pulled down to a low level, i.e., a logic "0" signal.

The first pull-down path and the second pull-down path will be described in detail below.

The first input signal amplifying circuit and the first clock signal sensing amplifying circuit are connected through a first node (node A); the second input signal amplifying circuit and the second clock signal sensing amplifying circuit are connected through a second node (node B); the first clock signal sensing amplifying circuit is connected with the first grounding amplifying circuit through a third node (node C); the second clock signal sense amplifier circuit and the second ground amplifier circuit are connected through a fourth node (node D).

The first ends of the first charging circuit and the second charging circuit are both connected with a power supply; the second end of the first charging circuit is connected with the sensing module through a signal node; the second end of the second charging circuit is connected with the sensing module through a reset signal node. Specifically, the first charging circuit and the first input signal amplifying circuit are connected through a setting signal node (SB node) for collecting a setting signal; the second charging circuit and the second input signal amplifying circuit are connected through a reset signal node (RB node) for collecting reset signals.

The first grounding amplification circuit and the second grounding amplification circuit are both grounded through grounding points.

When the setting signal node, the first node, the third node and the grounding point are conducted, a first pull-down path for pulling down the setting signal is formed; and when the reset signal node, the second node, the fourth node and the grounding point are conducted, a second pull-down path for pulling down the reset signal is formed.

Without loss of generality, the first clock signal sensing amplifying circuit and the second clock signal sensing amplifying circuit are respectively used for receiving clock signals and are conducted when the clock signals are in high level. The first grounding amplifying circuit and the second grounding amplifying circuit are both high-level trigger circuits, namely, the first grounding amplifying circuit and the second grounding amplifying circuit trigger actions when high levels are acquired.

The triggering action in the embodiment of the present invention includes turning on a switching device (or a switching unit) in the circuit.

The working principle of the sensing module is explained below.

The cross jump transfer circuit is used for transferring the effective signal of the amplifying circuit which is conducted when the differential input signal jumps after the induction stage is finished to the other amplifying circuit which is conducted before the differential input signal jumps (the induction stage). When the differential input signal jumps, the amplifying circuit (the first amplifying circuit or the second amplifying circuit) which is conducted in the sensing stage is temporarily disconnected, and the other amplifying circuit is triggered to be conducted under the condition of the jump of the differential input signal. At this time, the conductive amplifying circuit in the sensing stage can be turned on again through the cross transition transfer branch, so that the signal (the setting signal or the reset signal) is pulled down continuously through the original pull-down path in the sensing stage.

The first transfer circuit is connected with the first input signal amplifying circuit in parallel, a first end of the first transfer circuit and a first end of the first input signal amplifying circuit are both connected with a set signal node, and a second end of the first transfer circuit and a second end of the first input signal amplifying circuit are both connected with a first end of the first clock signal sensing amplifying circuit; the control end of the first transfer circuit is connected with the second end of the second clock signal sensing amplifying circuit; the second transfer circuit is connected with the second input signal amplifying circuit in parallel, a first end of the second transfer circuit and a first end of the second input signal amplifying circuit are both connected with a reset signal node, and a second end of the second transfer circuit and a second end of the second input signal amplifying circuit are both connected with a first end of the second clock signal sensing amplifying circuit; the control end of the second transfer circuit is connected with the second end of the first clock signal sensing amplifying circuit.

Illustratively, the first transfer circuit is used for transferring the effective signal of the second amplifying circuit to the first amplifying circuit when the induction is completed and the differential input signal jumps, so that the setting signal continues to discharge through a pull-down path in the induction phase. (in the sensing stage, if the original data signal is at a high level, the set signal is discharged through the first pull-down path of the first amplifying circuit, i.e., pulled down.) the second transfer circuit is used for transferring the effective signal of the first amplifying circuit to the second amplifying circuit when the sensing is completed and the differential input signal jumps, so that the reset signal continues to be amplified through the pull-down path of the sensing stage (in the sensing stage, if the original data signal is at a low level, the reset signal is discharged through the second pull-down path of the second amplifying circuit, i.e., pulled down).

The cross-transition transfer circuit allows the differential input signal (e.g., the original data signal) to transition after the sensing stage is completed, yet still discharge through the pull-down path of the data signal sensing stage. The pull-down speed is high, the jump interference of differential input signals is avoided, and the safety and the efficiency are high.

The following sets are illustrative of the various circuits in the charging module.

The charging module comprises a first charging circuit and a first signal maintaining circuit which are connected in parallel, and a second charging circuit and a second signal maintaining circuit which are connected in parallel. The first charging circuit comprises a first switch unit, and the first signal maintaining circuit comprises a second switch unit; the first switch unit is connected with the second switch unit in parallel; the first end of the first switch unit is connected with the power supply, and the second end of the first switch unit is connected with the signal node; the first end of the second switch unit is connected with the power supply, and the second end of the second switch unit is connected with the signal node; the control end of the first switch unit is used for receiving a clock signal; the control end of the second switch unit is used for receiving a reset signal of the reset signal node; the second charging circuit includes a fourth switching unit; the second signal maintaining circuit includes a third switching unit; the third switching unit is connected with the fourth switching unit in parallel; the first end of the third switching unit is connected with the power supply, and the second end of the third switching unit is connected with the setting signal node; the first end of the fourth switch unit is connected with the power supply, and the second end of the fourth switch unit is connected with the signal node; the control end of the fourth switching unit is used for receiving a clock signal; the control terminal of the third switching unit is used for receiving a setting signal for setting the signal node.

In an embodiment of the present invention, the switch unit (e.g., the first switch unit, the second switch unit, etc.) may select an electronic device triggered at a low level, and in another embodiment, the switch unit may also be implemented by selecting a mode of combining an electronic device triggered at a high level with an inverter.

Illustratively, the first charging circuit includes a first PMOS transistor P1, the first signal maintaining circuit includes a second PMOS transistor P2; the second charging circuit includes a third PMOS transistor P3, and the second signal maintaining circuit includes a fourth PMOS transistor P4. The sources of P1, P2, P3 and P4 are all connected with a power supply. The gates of P1, P4 are used to receive a clock signal (CLK). The drains of P1 and P2 are connected to form a first signal node, the set signal node. The drains of P3 and P4 are connected to form a second signal node, the reset signal node. The drains of P1 and P2, the set signal node, are also connected to the gate of P3. The drains of P3 and P4, i.e., the reset signal node, are also connected to the gate of P2.

The following sets of exemplary descriptions are provided for the various circuits in the sense module.

The first input signal amplifying circuit includes a first switching device; the first transfer circuit includes a seventh switching device; a first end of the first switching device and a first end of the seventh switching device are both connected with a set signal node; a second terminal of the first switching device and a second terminal of the seventh switching device are both connected to a first terminal (a first node) of the first clock signal sensing and amplifying circuit; the control end of the seventh switching device is connected with the second end (the fourth node) of the second clock signal sensing amplifying circuit; the second input signal amplifying circuit includes a second switching device; the second transfer circuit includes an eighth switching device; the first end of the second switching device and the first end of the eighth switching device are both connected with a reset signal node; a second end of the second switching device and a second end of the eighth switching device are both connected with a first end (a second node) of the second clock signal sensing amplifying circuit; the control end of the eighth switching device is connected with the second end (the third node) of the first clock signal sensing amplifying circuit; the control end of the first switching device is used for receiving an original data signal; the control terminal of the second switching device is used for receiving the inverted data signal.

In an embodiment of the present invention, the switching device (e.g., the first switching device, the seventh switching device, etc.) may be implemented by selecting an electronic device triggered at a high level, and in another embodiment, may also be implemented by selecting a mode of triggering the electronic device at a low level in combination with an inverter. The embodiment of the invention does not limit the selection of the device.

The first clock signal sensing amplifying circuit comprises a third switching device; a first terminal of the third switching device is connected to a second terminal (first node) of the first switching device; the second end of the third switching device is connected with the first end (third node) of the first grounding amplification circuit; the control end of the third switching device is used for receiving a clock signal; the second clock signal sensing amplifying circuit comprises a fourth switching device; a first end of the fourth switching device is connected with a second end (a second node) of the second switching device; a second end of the fourth switching device is connected with a second end (a fourth node) of the second grounding amplification circuit; the control terminal of the fourth switching device is used for receiving the clock signal.

Illustratively, the first clock signal sense amplifying circuit includes a third NMOS transistor N3 (N-Metal-Oxide-Semiconductor). The gate of N3 is used to receive the clock signal and is turned on when the clock signal is high. The drain of N3 is connected to the first node (node a), specifically the drain of N3 is connected to the source of N1, forming the first node (node a). The source of N3 is connected to the third node (node C). The second clock signal sense amplifying circuit includes a fourth NMOS transistor N4. The gate of N4 is used to receive the clock signal and is turned on when the clock signal is high. The drain of N4 is connected to the second node (node B), specifically, the drain of N4 is connected to the source of N2, forming a second node (node B). The source of N4 is connected to the fourth node (node D).

The first input signal amplifying circuit includes a first NMOS transistor N1, and the first transfer circuit includes a seventh NMOS transistor N7. The gate of N1 is used to receive the original data signal (D). The drain of N1 is connected to the drain of P1 (and P2), the set signal node. The source of N1 is connected to the first node (node A). The drain of N7 is connected to the drain of N1, and the source of N7 is connected to the source of N1. The second input signal amplifying circuit includes a second NMOS transistor N2, and the second transfer circuit includes an eighth NMOS transistor N8. The gate of N2 is used to receive the inverted data signal DB. The drain of N2 is connected to the drain of P3 (and P4), the reset signal node. The source of N2 is connected to the second node (node B). The drain of N8 is connected to the drain of N2, and the source of N8 is connected to the source of N2. The gate of N7 is connected to the source of N4. The gate of N8 is connected to the source of N3.

The first ground amplifying circuit includes a fifth switching device; a first terminal of the fifth switching device is connected to a second terminal (third node) of the third switching device; a second end of the fifth switching device is grounded; the control end of the fifth switching device is used for receiving a reset signal of the reset signal node; the second ground amplifying circuit includes a sixth switching device; a first terminal of the sixth switching device is connected to a second terminal connection (third node) of the fourth switching device; a second end of the sixth switching device is grounded; the control terminal of the sixth switching device is used for receiving a setting signal of the setting signal node.

Illustratively, the first ground amplifying circuit includes a fifth NMOS transistor N5. The gate of N5 is connected to the reset signal node (RB). The drain of N5 is connected to the third node (node C). The source of N5 is grounded. The second ground amplifying circuit includes a sixth NMOS transistor N6. The gate of N6 is connected to the set signal node (SB). The drain of N6 is connected to the fourth node (node C). The source of N6 is grounded.

As shown in fig. 2a, when CLK is low, only the nodes RB, SB, a (or B) are charged, which greatly reduces the waste of charging and discharging of other node circuits. At the same time, the improved SA may capture input data faster on CLK rising edges. This is mainly because the internal node (node on the pull-down path) is kept at a low level during the discharging process, reducing the discharging time of the internal node, resulting in a better retention time and a reduction in power consumption.

The embodiment of the invention also provides a trigger based on the sensing amplifier circuit, which is applied to the rising edge sampling data of a high-speed circuit system by utilizing the improved sensitive amplifier main-stage trigger to sample the data of the rising edge of the clock signal and then latching the data through the latch. Wherein the latch is configured to receive a clock signal, a differential input signal, and a set signal from the sense amplifier circuit and latch a target data signal.

The structure of the latch of the embodiment of the present invention is exemplarily described below.

As shown in fig. 2b, the Latch (Latch) of the slave stage is an SR Latch, and includes a charge and discharge circuit and a feedback circuit. The charge and discharge circuit is coupled with the feedback circuit. The charging and discharging circuit receives a clock signal, a differential input signal and a setting signal and outputs a target data signal; and the feedback circuit receives the target data signal and the clock signal and latches the target data signal when the clock signal is invalid.

The charging and discharging circuit comprises a fifth switch unit, a ninth switch device, a tenth switch device and an eleventh switch device which are sequentially connected in series; the first end of the fifth switching unit is connected with the power supply, and the second end of the fifth switching unit is connected with the first end of the ninth switching device; the control end of the fifth switch unit is used for receiving a setting signal; the differential input signal comprises an original data signal and an inverted data signal; the control end of the ninth switching device is used for receiving the inverted data signal; a second terminal of the ninth switching device is connected with a first terminal of the tenth switching device; the control end of the tenth switching device is used for receiving the clock signal; a second terminal of the tenth switching device is connected to a first terminal of the eleventh switching device; a second terminal of the eleventh switching device is grounded; the control end of the eleventh switching device is used for receiving a setting signal; the second terminal of the fifth switching unit is for a target data signal. Wherein the fifth switching unit and the eleventh switching device are configured not to be turned on at the same time, i.e., at most one of them is turned on at the same time.

Illustratively, the charge and discharge circuit includes a fifth PMOS transistor P5, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11 connected in series in this order. The source of P5 is connected to the power supply, the drain of P5 is connected to the drain of N9, and the gate of P5 is used to receive the set Signal (SB). The source of N9 is connected to the drain of N10, and the gate of N9 is used for collecting the inverted data signal (DB). The source of N10 is connected to the drain of N11, and the gate of N10 is used to capture the clock signal (CLK). The source of N11 is grounded and the gate of N11 is used to collect the set Signal (SB). The connection point of the drain of the P5 and the drain of the N9 is used as an output sampling point for collecting a target data signal Q.

The feedback circuit comprises a sixth switching unit, a seventh switching unit, a twelfth switching device and an inverter which are sequentially connected in series; the first end of the sixth switching unit is connected with the power supply; the second end of the sixth switching unit is connected with the first end of the seventh switching unit; the input end of the inverter is used for receiving a target data signal, and the output end of the inverter is connected with the control end of the sixth switching unit; the output end of the inverter is used for outputting an inverted signal of the target data signal; the second end of the seventh switching unit is connected with the first end of the twelfth switching device; the control end of the seventh switching unit is used for receiving a clock signal; a second terminal of the twelfth switching device is connected to a second terminal of the tenth switching device; the control end of the twelfth switching device is connected with the output end of the inverter; a second terminal of the seventh switching unit is connected to a first terminal of the twelfth switching device. Wherein the sixth switching unit and the twelfth switching device are configured not to be turned on at the same time, i.e., at most one of them is turned on at the same time.

Illustratively, the feedback circuit includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a twelfth NMOS transistor N12. The source of P6 is connected to the power supply, and the drain of P6 is connected to the source of P7. The gate of P6 is connected to the charge and discharge circuit through an inverter. Specifically, the input end of the inverter (INV1) is connected to the output sampling point, and the output end of the inverter is connected to the gate of P6. The drain of P7 is connected to the drain of N12, and the gate of P7 is for receiving a clock signal (CLK). The source of N12 is connected to the source of N10, and the gate of N12 is connected to the output of the inverter. The output end of the inverter is used for outputting an inverted signal of the target data signal Q. The junction of P7 and N12 forms a sixth node that connects to the output sample point.

Compared with the SAFF in the prior art, the latch of the slave stage exchanges the positions of the transistors controlled by DB and CLK, so that the charging and discharging of the node between the two tubes are avoided, and the power consumption is further optimized.

The operation of the sense amplifier of the main stage is exemplarily described below.

A charging stage: when the clock signal is at a low level, the set signal node and the reset signal node are charged to a high level (1), and the cross-jump transfer circuit is discharged to a low level (0). As shown in fig. 2a, when CLK is 0, P1, P4 are turned on, and the set signal node (SB) and the reset signal node (RB) are charged to a high level, i.e., 1; n5, N6 turned on, nodes C, D discharged to 0, N7, N8 turned off.

And in the induction stage, the sensitive amplifier acquires the rising edge of the clock signal, namely, the sensitive amplifier enters the induction stage when the clock signal jumps from low level to high level. At this time, if the original data signal is at a high level, the set Signal (SB) is pulled down to a low level by the first amplification circuit. Specifically, the set Signal (SB) is pulled down to a low level through the first pull-down path.

The first pull-down path is a signal path for setting the signal node, the first node, and the third node to the ground point. As shown in fig. 3a, a first pull-down path is formed through the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first ground amplifying circuit in the first amplifying circuit.

As shown in FIG. 3a, if D is 1, the SB node (i.e. the set signal node) is pulled down to 0 from N1, N3, N5, then P3 is turned on and RB remains 1.

A jump stage: after the sensing stage, when the clock signal is continuously at the high level and the data signal jumps to the low level, the first pull-down path is temporarily disconnected, the second amplifying circuit is partially connected (including the second input signal amplifying circuit and the second clock signal sensing amplifying circuit) to form an effective signal, the effective signal is transferred to the first amplifying circuit through the first transfer circuit, and the first pull-down path is connected again. The setting signal continues to discharge through the first pull-down path with low potential, and the discharge speed is high.

After sensing is complete, when CLK is still high, D suddenly jumps to 0, N2 and N4 turn on, node D is charged to 1, and N7 turns on, as shown in fig. 3 b. The pull-down paths of the SB nodes are N7, N3, N5.

The N8 opening process works similarly. In another scenario, the charging phase is the same as the above, and when the data signal in the sensing phase is at a low level, the circuit operation is symmetrical to the above process, which is specifically as follows.

And in the induction stage, the sensitive amplifier acquires the rising edge of the clock signal, and the sensing stage is started when the clock signal jumps from low level to high level. At this time, if the original data signal is at a low level, the reset signal (RB) is pulled down to a low level by the second amplification circuit. Specifically, the reset signal (RB) is pulled down to a low level through the second pull-down path.

The second pull-down path is a signal path from the reset signal node, the second node, the fourth node to the ground point. The second pull-down path is formed by a second input signal amplification circuit, a second clock signal sensing amplification circuit, and a second ground amplification circuit in the second amplification circuit.

Illustratively, if the original data signal D is 0, the inverted data signal DB is 1, the RB node (i.e., the reset signal node) is pulled down to 0 by N2, N4, N6, and then P2 is turned on, and SB maintains the original 1.

After the sensing stage, when the clock signal is continuously at the high level and the original data signal jumps to the high level (correspondingly, the inverted data signal jumps to the low level invalid signal), the second pull-down path is temporarily disconnected, the first amplifying circuit is partially connected (including the first input signal amplifying circuit and the first clock signal sensing amplifying circuit are connected) to form a valid signal, the valid signal (such as the high level connection signal for connecting the circuit) is transferred to the second amplifying circuit through the second transfer circuit, and the second pull-down path is connected again. The reset signal continues to discharge through the second pull-down path with low potential, and the discharge speed is high.

After the sensing is completed, when CLK is still high, D suddenly jumps to 1, at which time N1, N3 turn on, node C is charged to 1, and N8 turns on. The pull-down paths of the RB node are N8, N4, and N6.

The trigger realized by the sensitive amplifier of the embodiment of the invention can reduce power consumption, and has higher data capture speed and higher accuracy.

As shown in fig. 2b, when the flip-flop collects a rising edge of the clock signal (CLK), if the original data signal is 1, the set Signal (SB) is pulled down to low (0), P5 is turned on, and Q is pulled up to high. At this time, the inverted data signal (DB) is 0, N9 is turned off, and the connection node between N9 and N10 is not charged, thereby preventing unnecessary charge and discharge processes.

When the clock signal (CLK) is collected by the master stage and is a rising edge, if the original data signal is 0, the inverted data signal (DB) is 1, and N9 is conducted; the reset signal (RB) is pulled down to be in a low level, the setting Signal (SB) keeps in a high level, P5 is disconnected, and N11 is conducted; if the clock signal is high level, N10 is conducted; q is pulled down low through N9, N10, and N11.

The feedback circuit is capable of latching the last data when the clock signal is low.

When the clock signal CLK is at low level, if the target data signal Q is 1, QB is 0, P6 and P7 are turned on, and the target data signal remains 1; if the target data signal Q is 0, QB is 1, N12, N11 is turned on, and the target data signal Q remains 0.

The flip-flop realized by the latch of the embodiment of the invention reduces the energy consumption due to the reduction of the number of charge and discharge nodes.

The sense amplifier circuit and the trigger of the invention can be applied to a high-speed circuit system and realize the sampling of data by the rising edge of a clock.

The following is an example of an amplifier circuit in the prior art, and a comparison is made between technical effects of the sense amplifier circuit according to the embodiments of the present invention, but the use scenarios of the sense amplifier circuit according to the embodiments of the present invention are not limited.

Fig. 4 shows a structure diagram of a SAFF (sense-amplifier-based flip-flop) proposed by Heng young et al, in which a main differential sense amplifier of the single-ended SAFF senses input data at a rising edge of a clock, and a sampling window is closed and output from a slave stage once a transition of a clock signal CLK from low to high occurs. As shown in fig. 4, when the main stage CLK is low, SN and RN in the circuit are precharged to high, and when CLK is high, if D is high, SN is discharged to low, and the output Q is pulled up to 1 by MP 5; if D is low, RN is discharged to low, the output Q is pulled down to 0 by MN8, MN9, MN11, and Feedback inverter and INV1 can latch the last data when CLK is low. The SAFF structure mainly has the following problems:

(1) for the main stage SA, when CLK is low level, nodes SN, RN, n1, n2, n3 and n4 need to be charged, and then nodes SN, n3, n1 or nodes RN, n4 and n2 need to be discharged when CLK rises, so that energy consumption is high.

(2) When CLK is high, if data D changes from "1" to "0" MN3, MN4 turns on and the RN, n4, n2 nodes discharge. However, since MN7 is a weak transistor that is always on, MN4 turns on and provides a pull-down circuit ground to SN (MN1, MN5, MN7, MN 4). The MN7 transistor reduces the SAFF stability under low supply voltage, and during the SA phase of CLK rising edge, the difference between Vn1 and Vn2 (i.e. the voltages at nodes n1 and n 2) should be large enough to obtain RN, SN quickly and correctly.

As shown in fig. 5, the master stage SA, the differential circuit, is a structure which is asymmetric in both sides because the SAFF slave stage uses only the SN signal, and both the pull-up path and the pull-down path of the SN in the left-side block are larger in size than the pipes in the pull-up path and the pull-down path of the RN in the right-side block to improve the driving capability of the SN node.

When VDD is low, the difference between Vn1 and Vn2 becomes small, and the mismatch between the tubes on both sides of the circuit has a serious effect on the difference between Vn1 and Vn2, and the SA stage may latch erroneous data. If D is 0 and DN is 1, the voltage at point n2 is slowly reduced due to the small size of MN4 tube, and the voltage at point n1 is also reduced by a small amplitude through MN7 tube. The voltage drop at point n1 may cause unnecessary power consumption, even pulling the SN point voltage low to 0.

3) As shown in fig. 6 and 7, at the first time, when the rising edge of CLK reaches a time D equal to 1, SN is 0, MP5 and MN8 are turned on, and the target data signal nodes Q and a are charged to high level.

As shown in fig. 6 and 7, at the second time, when the rising edge of CLK reaches the time point D equal to 0, SN is 1, MN8, MN9, and MN11 are turned on, and the target data signal nodes Q and a are charged to low level. Thus, unnecessary repeated charging and discharging of the node a may increase power consumption.

The measurement of the time delay and the power consumption is completed by the SAFF of the embodiment of the invention on HSPICE software. The simulation conditions are set as room temperature 25 deg.C, 1.2V power supply voltage TT process angle, clock frequency fclk is 500MHz, input data signal frequency fd is 250MHz (alpha is 1), alpha represents data activity factor, and its calculation formula

Where fd represents the frequency of the input signal and fclk represents the frequency of the clock signal.

Compared with the output waveforms of the Heng young SAFF and the improved SAFF simulation diagram in the prior art, it is found that the flip-flop according to the embodiment of the present invention has faster rising edge and falling edge of the level transition of the signal Q, and the power consumption is lower. As shown in fig. 8, the sensing phase SB of the SAFF of the improved embodiment of the present invention can capture input data faster at the rising edge of CLK. The time delay of the improved SAFF from the induction data to the low level is shorter than that of the improved SAFF from the induction data to the low level, and the induction delay is optimized to 21.6%.

As shown in fig. 9, the differential sides of the regulation pull-down circuit provided by the improved SAFF have no mutual interference of currents, the signal that needs to be kept from being pulled down can be stabilized at a high level, compared with Heng You SAFF, the regulation pull-down circuit is affected by a always-on pipe, and when the SB pull-down path is not turned on, the SB voltage is still decreased, and redundant actions not only bring about waste of power consumption, but also cause SB errors.

The sensing amplifier circuit of the embodiment of the invention adopts a symmetrical structure, the type selection of devices on two sides is easy, and the problems of instability and error latch caused by the size difference of the devices can be avoided. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A sense amplifier circuit, comprising:

a charging module configured to charge the set signal node and the reset signal node according to a clock signal; a sensing module coupled to the charging module and configured to sense and amplify a differential input signal according to a clock signal; the sensing module comprises a first amplifying circuit, a second amplifying circuit and a cross jump transfer circuit which is connected between the first amplifying circuit and the second amplifying circuit in a cross mode; the cross-transition transfer circuit comprises a first transfer circuit and a second transfer circuit; the first transfer circuit is used for transferring the effective signal of the second amplifying circuit to the first amplifying circuit when the induction is finished and the differential input signal generates a first jump, so that the setting signal of the setting signal node and the reset signal of the reset signal node are kept unchanged; the second transfer circuit is used for transferring the effective signal of the first amplifying circuit to the second amplifying circuit when the induction is finished and the differential input signal generates a second jump, so that the setting signal of the setting signal node and the reset signal of the reset signal node are kept unchanged.

2. The sense amplifier circuit of claim 1,

the first amplifying circuit comprises a first input signal amplifying circuit and a first clock signal sensing amplifying circuit which are connected in series; the second amplifying circuit comprises a second input signal amplifying circuit and a second clock signal sensing amplifying circuit which are connected in series; the second clock signal sensing amplifying circuit is connected with the first input signal amplifying circuit through a first transfer circuit; the first clock signal sensing amplifying circuit and the second input signal amplifying circuit are connected through a second transfer circuit.

3. The sense amplifier circuit of claim 2,

4. The sense amplifier circuit of claim 1,

the differential input signal comprises an original data signal and an inverted data signal; the first amplifying circuit receives an original data signal, is used for conducting in an induction stage and pulls down a setting signal to be low level through a first pull-down path; the second amplifying circuit receives the inverted data signal and is used for conducting in the induction stage and pulling down the reset signal to be low level through the second pull-down path.

5. The sense amplifier circuit of claim 2,

the first amplifying circuit further comprises a first grounding amplifying circuit; the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first grounding amplifying circuit are sequentially connected in series, the first end of the first input signal amplifying circuit is connected with the set signal node, and the second end of the first grounding amplifying circuit is grounded; the control end of the first grounding amplification circuit is connected with the reset signal node and is used for switching on or switching off under the action of a reset signal; the second amplifying circuit further comprises a second grounding amplifying circuit; the first input signal amplifying circuit, the second clock signal sensing amplifying circuit and the second grounding amplifying circuit are sequentially connected in series, the first end of the second input signal amplifying circuit is connected with the reset signal node, and the second end of the second grounding amplifying circuit is grounded; and the control end of the second grounding amplifying circuit is connected with the setting signal node and is used for being switched on or switched off under the action of the setting signal.

6. The sense amplifier circuit of claim 1,

the charging module comprises a first charging circuit and a second charging circuit; the first charging circuit is used for charging the setting signal node according to the clock signal; the second charging circuit is used for charging the reset signal node according to the clock signal; the first ends of the first charging circuit and the second charging circuit are both connected with a power supply; the second end of the first charging circuit is connected with the sensing module through a signal node; the second end of the second charging circuit is connected with the sensing module through a reset signal node.

7. The sense amplifier circuit of claim 6,

the charging module also comprises a first signal maintaining circuit and a second signal maintaining circuit; the first signal maintaining circuit is connected with the first charging circuit in parallel, and the first signal maintaining circuit is connected with the reset signal node; the second signal maintaining circuit is connected with the second charging circuit in parallel, and the second signal maintaining circuit is connected with the setting signal node; the first signal maintaining circuit is used for maintaining the state of the set signal when the sensing is finished and the differential input signal generates second jumping; the second signal maintaining circuit is used for maintaining the state of the reset signal when the sensing is finished and the differential input signal generates a first transition.

8. The sense amplifier circuit of claim 7,

the first charging circuit comprises a first switch unit, and the first signal maintaining circuit comprises a second switch unit; the first switch unit is connected with the second switch unit in parallel; the first end of the first switch unit is connected with the power supply, and the second end of the first switch unit is connected with the signal node; the first end of the second switch unit is connected with the power supply, and the second end of the second switch unit is connected with the signal node; the control end of the first switch unit is used for receiving a clock signal; the control end of the second switch unit is used for receiving a reset signal of the reset signal node; the second charging circuit includes a fourth switching unit; the second signal maintaining circuit includes a third switching unit; the third switching unit is connected with the fourth switching unit in parallel; the first end of the third switching unit is connected with the power supply, and the second end of the third switching unit is connected with the setting signal node; the first end of the fourth switch unit is connected with the power supply, and the second end of the fourth switch unit is connected with the signal node; the control end of the fourth switching unit is used for receiving a clock signal; the control terminal of the third switching unit is used for receiving a setting signal of the setting signal node.

9. The sense amplifier circuit of claim 5,

the first input signal amplifying circuit includes a first switching device; the first transfer circuit includes a seventh switching device; the first end of the first switching device and the first end of the seventh switching device are both connected with a set signal node; the second end of the first switching device and the second end of the seventh switching device are both connected with the first end of the first clock signal sensing amplifying circuit; the control end of the seventh switching device is connected with the second end of the second clock signal sensing amplifying circuit; the second input signal amplifying circuit includes a second switching device; the second transfer circuit includes an eighth switching device; the first end of the second switching device and the first end of the eighth switching device are both connected with a reset signal node; a second end of the second switching device and a second end of the eighth switching device are both connected with a first end of the second clock signal sensing amplifying circuit; the control end of the eighth switching device is connected with the second end of the first clock signal sensing amplifying circuit; the control end of the first switching device is used for receiving an original data signal; the control terminal of the second switching device is used for receiving the inverted data signal.

10. The sense amplifier circuit of claim 9,

the first clock signal sensing amplifying circuit comprises a third switching device; the first end of the third switching device is connected with the second end of the first switching device; the second end of the third switching device is connected with the first end of the first grounding amplification circuit; the control end of the third switching device is used for receiving a clock signal; the second clock signal sensing amplifying circuit comprises a fourth switching device; the first end of the fourth switching device is connected with the second end of the second switching device; a second end of the fourth switching device is connected with a second end of the second grounding amplification circuit; the control terminal of the fourth switching device is used for receiving the clock signal.

11. The sense amplifier circuit of claim 10,

the first ground amplifying circuit includes a fifth switching device; a first end of the fifth switching device is connected with a second end of the third switching device; a second end of the fifth switching device is grounded; the control end of the fifth switching device is used for receiving a reset signal of the reset signal node; the second ground amplifying circuit includes a sixth switching device; a first end of the sixth switching device is connected with a second end of the fourth switching device; a second end of the sixth switching device is grounded; the control terminal of the sixth switching device is configured to receive a setting signal for setting the signal node.

12. A flip-flop, comprising:

the sense amplifier circuit and latch of any of 1-11; the latch is to receive a clock signal, a differential input signal, and a set signal from the sense amplifier circuit and latch a target data signal.

13. The flip-flop according to claim 12,

the latch comprises a charging and discharging circuit and a feedback circuit; the charging and discharging circuit receives a clock signal, a differential input signal and a setting signal and outputs a target data signal; and the feedback circuit receives the target data signal and the clock signal and latches the target data signal when the clock signal is invalid.

14. The flip-flop of claim 13,

the charge and discharge circuit comprises a fifth switch unit, a ninth switch device, a tenth switch device and an eleventh switch device which are sequentially connected in series; the first end of the fifth switching unit is connected with the power supply, and the second end of the fifth switching unit is connected with the first end of the ninth switching device; the control end of the fifth switch unit is used for receiving a setting signal; the differential input signal comprises an original data signal and an inverted data signal; the control end of the ninth switching device is used for receiving the inverted data signal; a second end of the ninth switching device is connected with a first end of a tenth switching device; the control end of the tenth switching element is used for receiving a clock signal; a second terminal of the tenth switching device is connected to a first terminal of the eleventh switching device; a second terminal of the eleventh switching device is grounded; the control end of the eleventh switching device is used for receiving a setting signal; a second terminal of the fifth switching unit is used for outputting a target data signal; the fifth switching unit and the eleventh switching device are configured such that at most one of them is turned on at the same time.

15. The flip-flop of claim 14,

the feedback circuit comprises a sixth switching unit, a seventh switching unit, a twelfth switching device and an inverter which are sequentially connected in series; the first end of the sixth switching unit is connected with the power supply; the second end of the sixth switching unit is connected with the first end of the seventh switching unit; the input end of the reverser receives the target data signal, and the output end of the reverser is connected with the control end of the sixth switching unit; the second end of the seventh switching unit is connected with the first end of the twelfth switching device; the control end of the seventh switching unit is used for receiving a clock signal; a second end of the twelfth switching device is connected to a second end of the tenth switching unit; the control end of the twelfth switching device is connected with the output end of the inverter; the sixth switching unit and the twelfth switching device are configured such that at most one of them is turned on at the same time.