CN115101595A - High electron mobility transistor, preparation method thereof and semiconductor device - Google Patents

High electron mobility transistor, preparation method thereof and semiconductor device Download PDF

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Publication number
CN115101595A
CN115101595A CN202210813878.1A CN202210813878A CN115101595A CN 115101595 A CN115101595 A CN 115101595A CN 202210813878 A CN202210813878 A CN 202210813878A CN 115101595 A CN115101595 A CN 115101595A
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layer
type doped
doped layer
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type
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胡俊杰
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Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
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Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention provides a high electron mobility transistor, a preparation method thereof and a semiconductor device. In the transistor, the P-type doping layer is arranged between the first source/drain electrode and the two-dimensional electron gas, and the inversion of the P-type doping layer is controlled by the grid electrode to form an N-type conducting channel, so that the two-dimensional electron gas in the channel layer and the N-type conducting channel formed by the inversion in the P-type doping layer are mutually connected. That is, in the HEMT device provided by the present invention, the gate is used to control the inversion condition of the P-type doped layer, so as to turn on or off the HEMT device, and the corresponding control voltage can be adjusted more flexibly, which is beneficial to improving the threshold voltage of the HEMT device, for example, the threshold voltage of the HEMT device can reach 3V or more.

Description

High electron mobility transistor, preparation method thereof and semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-electron-mobility transistor, a preparation method thereof and a semiconductor device.
Background
A High Electron Mobility Transistor (HEMT) is a field effect Transistor based on High Mobility characteristics of two-dimensional Electron gas in a heterojunction, has High Electron Mobility at low temperature and low electric field, and can realize High-speed and low-noise operation.
Fig. 1 is a schematic structural diagram of a HEMT in the prior art, and as shown in fig. 1, the HEMT device includes: a substrate 10, a channel layer 20 and a barrier layer 30 sequentially formed on the substrate 10, and a source electrode 50S, a drain electrode 50D, and a gate electrode 50G. Wherein a two-Dimensional Electron Gas (2 DEG) is to be formed at an interface of the channel layer 20 near the barrier layer 30; the source electrode 50S and the drain electrode 50D are connected to the channel layer 20, thereby electrically connecting the two-dimensional electron gas 2 DEG; and the gate electrode 50G is disposed between the source electrode 50S and the drain electrode 50D for depleting the two-dimensional electron gas 2DEG in the channel layer 20 therebelow, thereby controlling the on/off of the device.
Currently, in order to realize a high threshold voltage HEMT device, an improvement is to provide a P-type gallium nitride layer (P-GaN layer) on a gate region and a gate metal in schottky contact with the P-GaN layer. However, this approach is quite limited to raising the threshold voltage of HEMT devices, for example only up to 1-2V.
Disclosure of Invention
The invention aims to provide a high electron mobility transistor to improve the threshold voltage of a HEMT device.
To this end, the present invention provides a high electron mobility transistor, comprising: a channel layer and a barrier layer formed in this order on a substrate, at least a partial region of the channel layer being for generating a two-dimensional electron gas; a first source/drain and a second source/drain formed on the channel layer; a gate between the first source/drain and the second source/drain. And, the high electron mobility transistor further comprises: the P-type doping layer is at least arranged between the two-dimensional electron gas and the first source/drain electrode, and the grid electrode covers the P-type doping layer and is used for controlling the P-type doping layer to invert to form an N-type conducting channel.
Optionally, the P-type doped layer is formed above the channel layer, the first source/drain is formed above the P-type doped layer, and the gate covers a sidewall of the P-type doped layer.
Optionally, the hemt further comprises: the first N-type doped layer, the P-type doped layer and the second N-type doped layer are sequentially stacked on the channel layer, and the first source/drain is disposed on a top surface of the second N-type doped layer.
Optionally, the P-type doped layer is formed in the channel layer, the two-dimensional electron gas and the first source/drain are respectively located on two opposite sides of the P-type doped layer, and the gate covers a top surface of the P-type doped layer.
Optionally, the high electron mobility transistor further includes: the first N-type doped layer, the P-type doped layer and the second N-type doped layer are sequentially arranged along the extending direction of the two-dimensional electron gas, and the first source/drain electrode is arranged on the top surface of the second N-type doped layer.
Optionally, a gate dielectric layer is further disposed between the gate and the P-type doped layer, and the gate dielectric layer covers the P-type doped layer and extends to cover the top surface of the barrier layer.
Optionally, a first N-type doped layer and a second N-type doped layer are respectively disposed on two sides of the P-type doped layer along the direction of the N-type conductive channel, and the gate covers the P-type doped layer and extends to cover at least a portion of the first N-type doped layer and at least a portion of the second N-type doped layer.
The invention also provides a preparation method of the high electron mobility transistor, which comprises the following steps: sequentially forming a channel layer and a barrier layer on a substrate, wherein at least partial area of the channel layer is used for generating two-dimensional electron gas; etching the barrier layer to form an opening that exposes the channel layer; forming a P-type doped layer in the region of the opening; and forming a first source/drain electrode, a second source/drain electrode and a grid electrode positioned between the first source/drain electrode and the second source/drain electrode, wherein the first source/drain electrode is arranged on one side of the P-type doped layer away from the two-dimensional electron gas, and the grid electrode covers the P-type doped layer and is used for controlling the P-type doped layer to reversely form an N-type conductive channel.
Optionally, the method for forming the P-type doped layer includes: epitaxially growing a P-type material layer covering portions of the barrier layer and the channel layer exposed to the opening; and performing an etching process to remove the part of the P-type material layer outside the opening region so as to form the P-type doped layer on the surface of the channel layer in the opening region.
Optionally, the preparation method further comprises: and respectively forming a first N-type doping layer and a second N-type doping layer below and above the P-type doping layer, wherein the first N-type doping layer, the P-type doping layer and the second N-type doping layer are sequentially stacked on the surface of the channel layer exposed to the opening.
Optionally, the first source/drain is formed on the second N-type doped layer, and the gate covers a sidewall of the P-type doped layer.
Optionally, the method for forming the P-type doped layer includes: and performing P-type ion implantation on the part of the channel layer exposed to the opening to form the P-type doped layer.
Optionally, the preparation method further comprises: and performing N-type ion implantation on the part of the channel layer exposed to the opening to form a first N-type doped layer and a second N-type doped layer, wherein the first N-type doped layer and the second N-type doped layer are respectively positioned at two opposite sides of the P-type doped layer.
Optionally, the first source/drain is formed on the second N-type doped layer, and the gate covers a top surface of the P-type doped layer.
Another object of the present invention is to provide a semiconductor device including the high electron mobility transistor as described above.
Optionally, the semiconductor device includes at least two high electron mobility transistors, wherein adjacent high electron mobility transistors share the first source/drain.
Optionally, the first source/drain is disposed between adjacent high electron mobility transistors and above the channel layer, a P-type doped layer is disposed between the first source/drain and the channel layer, and gates are formed on sidewalls of two sides of the P-type doped layer, respectively.
Optionally, the first source/drain is disposed between adjacent high electron mobility transistors, and P-type doped layers are disposed on two sides of the first source/drain, respectively, the P-type doped layers are disposed in the channel layer, and a gate is formed on a top surface of each P-type doped layer.
In the high electron mobility transistor provided by the invention, the P-type doping layer is arranged between the first source/drain electrode and the two-dimensional electron gas in the channel layer, and the inversion of the P-type doping layer is controlled by the grid electrode to form the N-type conducting channel, so that the two-dimensional electron gas 2DEG in the channel layer can be mutually connected with the N-type conducting channel in the P-type doping layer, and the current flow between the first source/drain electrode and the second source/drain electrode is realized. Therefore, in the HEMT device provided by the invention, the inversion condition of the P-type doped layer can be controlled by using the grid, so that the on or off of the HEMT device is realized. Compared with the voltage of two-dimensional electron gas in a grid depletion channel layer in the traditional HEMT device, the voltage of the grid of the HEMT device can be adjusted more flexibly when the inversion of the P-type doping layer is controlled, so that the threshold voltage of the HEMT device can be improved, and the threshold voltage of the HEMT device can reach more than 3V.
Drawings
Fig. 1 is a schematic structural diagram of a conventional high electron mobility transistor.
Fig. 2 is a schematic structural diagram of a semiconductor device having a high electron mobility transistor according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a semiconductor device having a high electron mobility transistor according to a second embodiment of the present invention.
Fig. 4 is a flowchart illustrating a method for manufacturing a high electron mobility transistor according to a third embodiment of the present invention.
Fig. 5-8 are schematic structural diagrams of a high electron mobility transistor in a third embodiment of the invention in a manufacturing process thereof.
Fig. 9-10 are schematic structural diagrams of a hemt in the fourth embodiment of the present invention during the manufacturing process.
Wherein the reference numbers are as follows:
10-a substrate;
20-a channel layer;
30-a barrier layer;
a 50S-source;
a 50D-drain electrode;
a 50G-grid;
100-a substrate;
110-a transition layer;
120-a buffer layer;
200-a channel layer;
300-barrier layer;
400-a gate dielectric layer;
500S-source;
500D-drain electrode;
500G-grid;
610N-first N-type doped layer;
620N-a second N-type doped layer;
600P-P type doped layer.
Detailed Description
The present invention provides a high electron mobility transistor, a method for manufacturing the same, and a semiconductor device. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
< example one >
Fig. 2 is a schematic structural diagram of a semiconductor device having a high electron mobility transistor according to a first embodiment of the present invention. Specifically, referring to fig. 2, the high electron mobility transistor provided in this embodiment includes: a channel layer 200 and a barrier layer 300 disposed on a substrate 100 are sequentially stacked.
Among them, the substrate 100 may be further a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or the like.
Further, a transition layer 110 is formed on the substrate 100, and the transition layer 110 is, for example, a gallium nitride (GaN) transition layer or an aluminum nitride (AlN) transition layer. By arranging the transition layer 110, on one hand, lattice mismatch between the substrate 100 and an epitaxial layer epitaxially grown thereon can be reduced, and the crystal quality of the epitaxial layer can be improved; on the other hand, the film can also be used as a high-resistance layer to reduce the leakage of the device and the like. Further, a buffer layer 120 may be further disposed on the substrate 100, and the buffer layer 120 may be, for example, a gallium nitride buffer layer.
In this embodiment, the channel layer 200 and the barrier layer 300 are sequentially stacked on the buffer layer 120, and at least a partial region of the channel layer 200 is used to generate a 2-Dimensional Electron Gas (2 DEG). Specifically, the band gap width of the barrier layer 300 is larger than that of the channel layer 200, so that electrons in the wide band gap barrier layer 300 and electrons on the surface of the barrier layer overflow and move to the channel layer 200 near the interface of the barrier layers to be confined in the potential well formed at the interface, thereby forming the two-dimensional electron gas 2 DEG. Because these electrons in the potential well are spatially separated from the ionized impurities in the barrier layer, coulomb scattering is greatly reduced, thereby significantly improving electron mobility in the conduction channel.
In a specific example, the material of the barrier layer 300 includes gallium aluminum nitride (AlGaN). Further, the material of the barrier layer 300 may be an undoped material (e.g., an undoped gallium aluminum nitride layer); alternatively, the barrier layer 300 may be an N-doped material layer (e.g., an N-type doped aluminum gallium nitride layer) to facilitate inducing a higher density of two-dimensional electron gas 2 DEG. And, the material of the channel layer 200 includes gallium nitride (GaN). Further, the channel layer 200 may be a non-doped material layer (e.g., a non-doped gallium nitride layer), so that at least a portion of the channel layer 200 under the two-dimensional electron gas exhibits a high resistance value.
Further, the high electron mobility transistor further includes: a first source/drain electrode and a second source/drain electrode formed on the channel layer 200, a gate electrode 500G between the first source/drain electrode and the second source/drain electrode, and a P-type doping layer 600P. In a specific example, the first source/drain is, for example, a source, and the second source/drain is, for example, a drain; alternatively, the first source/drain is, for example, a drain, and the second source/drain is, for example, a source.
And the P-type doped layer 600P is disposed at least between the first source/drain electrode and the two-dimensional electron gas 2DEG along a current flowing direction of the transistor. The "current flowing direction of the transistor" is a current flowing direction between the first source/drain and the second source/drain, that is, a direction of a conductive channel of the HEMT device. The conduction channel of the HEMT device in this embodiment includes the two-dimensional electron gas 2DEG in the channel layer 200 and an N-type conduction channel formed by P-inversion of the P-doped layer 600, which will be described in detail in the subsequent section.
That is, the P-type doped layer 600P is spaced between the first source/drain electrode and the two-dimensional electron gas 2DEG within the channel layer 200. In a specific example, the first source/drain electrode may be a source electrode or a drain electrode, and thus the P-type doped layer 600P may be disposed between the source electrode and the two-dimensional electron gas 2DEG or between the drain electrode and the two-dimensional electron gas 2 DEG. Of course, in an alternative scheme, the P-type doped layer 600P may also be disposed between the second source/drain electrode and the two-dimensional electron gas 2DEG, that is, the P-type doped layer 600P is disposed between the source electrode and the two-dimensional electron gas 2DEG and between the drain electrode and the two-dimensional electron gas 2 DEG.
In this embodiment, the first source/drain is taken as the source electrode 500S as an example, that is, the P-type doped layer 600P is disposed between the source electrode 500S and the two-dimensional electron gas 2 DEG.
With continued reference to fig. 2, the gate 500G covers the P-type doped layer 600P for controlling the P-type doped layer 600P to invert to form an N-type conduction channel.
Specifically, during the turning-on process of the HEMT device, the gate 500G controls the P-type doped layer 600 to be inverted to form an N-type conduction channel, so that the source 500S and the drain 500D are connected to each other through the two-dimensional electron gas 2DEG in the channel layer 200 and the inverted N-type conduction channel, thereby realizing current flow. That is, the conductive channel of the HEMT device in this embodiment includes: a two-dimensional electron gas 2DEG within the channel layer 200 and an N-type conduction channel formed by the P-type doped layer 600P inversion.
In this embodiment, the P-type doped layer 600P is disposed between the two-dimensional electron gas 2DEG and the source electrode 500S, so that when the gate electrode 500G controls the P-type doped layer 600P to invert to form an N-type conduction channel, the two-dimensional electron gas 2DEG in the channel layer 200 can be connected to the source electrode 500S through the inverted N-type conduction channel. In another embodiment, the P-type doped layer 600P is disposed between the two-dimensional electron gas 2DEG and the drain electrode 500D, so that when the gate electrode 500G controls the P-type doped layer 600P to invert to form an N-type conduction channel, the two-dimensional electron gas 2DEG in the channel layer 200 can be connected to the drain electrode 500D through the inverted N-type conduction channel.
It should be appreciated that the gate in the prior art is typically used to control the generation or suppression of the two-dimensional electron gas 2DEG in the channel layer underneath the gate, and thus the turning on or off of the HEMT device, such as the HEMT device shown in fig. 1, where the gate directly acts on the two-dimensional electron gas 2DEG in the channel layer. However, in the HEMT device in this embodiment, the gate 500G is used for performing inversion control on the additionally disposed P-type doped layer 600P, so as to turn on or off the device. Compared with the traditional HEMT device, the HEMT device provided by the embodiment has more flexible adjustment on the threshold voltage, and is favorable for realizing the high threshold voltage of the HEMT device.
Referring to fig. 2, in the present embodiment, the P-type doped layer 600P is formed above the channel layer 200 to protrude from the top surface of the channel layer 200, the first source/drain (i.e., the source 500S in the present embodiment) is formed above the P-type doped layer 600P, and the gate 500G covers the sidewall of the P-type doped layer 600P. At this time, the HEMT device is configured such that the conduction channel thereof includes: a two-dimensional electron gas 2DEG in a horizontal direction and an N-type conduction channel in a vertical direction formed by a P-type doped layer 600P inversion in the channel layer 200. It should be noted that the "horizontal direction" described herein refers to a direction parallel to the top surface of the channel layer 200, and the "vertical direction" described herein refers to a direction perpendicular to the top surface of the channel layer 200.
Optionally, a first N-type doped layer 610N and a second N-type doped layer 620N are further disposed on two sides of the P-type doped layer 600P along the direction of the N-type conductive channel, respectively. That is, a first N-type doping layer 610N is disposed between the P-type doping layer 600P and the channel layer 200; and, a second N-type doped layer 620N may be disposed between the P-type doped layer 600P and the source electrode 500S.
The first N-type doped layer 610N, the P-type doped layer 600P, and the second N-type doped layer 620N are sequentially stacked on the channel layer to form an NPN structure, and the gate 500G covers the P-type doped layer 600P and extends to cover at least a portion of the first N-type doped layer 610N and at least a portion of the second N-type doped layer 620N, so as to control on/off of the NPN structure, and accordingly control on/off of the HEMT device. Specifically, when the HEMT device is turned on, the two-dimensional electron gas 2DEG in the channel layer 200 is connected to the source electrode 500S through the first N-type doped layer 610N, the inversion-formed N-type conduction channel, and the second N-type doped layer 620N.
In this embodiment, the P-type doped layer 600P is disposed above the channel layer 200, and based on this, the first N-type doped layer 610N may be disposed below the P-type doped layer 600P and penetrate through the barrier layer 300 to be formed on the surface of the channel layer 200, the P-type doped layer 600P and the second N-type doped layer 620N are sequentially stacked on the first N-type doped layer 610N, and the source electrode 500S is formed on the second N-type doped layer 620N. In a specific example, the thickness of the first N-type doped layer 610N may be greater than the thickness of the barrier layer 300, such that the top surface of the first N-type doped layer 610N protrudes from the top surface of the barrier layer 300, and thus, the gate 500G covering the sidewalls of the NPN structure can extend to cover the sidewalls of the first N-type doped layer 610N.
The material of the P-type doped layer 600 includes, for example, P-type gallium nitride (P-GaN), and the material of the first N-type doped layer 610N and the material of the second N-type doped layer 620N may both include N-type gallium nitride (N-GaN).
With continued reference to fig. 2, a gate dielectric layer 400 is further disposed between the gate 500G and the P-type doped layer 600P. In this embodiment, the gate dielectric layer 400 covers the sidewalls of the first N-type doped layer 610N, the P-type doped layer 600P, and the second N-type doped layer 620N, and the gate dielectric layer 400 may further extend to cover the top surface of the barrier layer 300 for passivation protection of the barrier layer 300 and improvement of the gate leakage current. The material of the gate dielectric layer 400 includes, for example, aluminum oxide, silicon oxide, or silicon nitride.
In a specific example, the inversion voltage of the gate 500G to the P-type doped layer 600P can be flexibly adjusted by adjusting the thickness of the gate dielectric layer 400. In this embodiment, the inversion voltage of the gate 500G to the P-type doped layer is equivalent to the threshold voltage of the HEMT device, so that the threshold voltage of the HEMT device can be flexibly regulated and controlled, and the higher threshold voltage is favorably achieved.
Based on the same inventive concept, there is also provided in the present embodiment a semiconductor device including the high electron mobility transistor (HEMT device) as described above.
As can be seen with continued reference to fig. 2, the semiconductor device can include at least two HEMT devices in a particular example. Further, the first source/drain may be shared between adjacent HEMT devices (i.e., either the source 500S or the drain 500D may be shared). For example, in the example shown in fig. 2, the source 500S is shared by the adjacent HEMT devices, wherein the shared source 500S is disposed between the adjacent HEMT devices, and the two drains 500D of the adjacent HEMT devices are disposed on the two sides of the source 500S, so that the source 500S can form two HEMT devices on the two sides thereof. It should be appreciated that the reduction of the device size and the increase of the line arrangement density can be effectively achieved by the common source 500S or the common drain 500D.
In this embodiment, the P-type doped layer 600P between the source electrode 500S and the two-dimensional electron gas 2DEG is also shared. Specifically, the P-type doped layer 600P and the source 500S are stacked above the channel layer 200 and located between adjacent HEMT devices, and the two sidewalls of the two opposite sides of the P-type doped layer 600P are respectively provided with a gate 500G for respectively controlling the two HEMT devices of the two sides. In a more specific example, the NPN structure and the source 500S are sequentially stacked between adjacent HEMT devices to achieve sharing. It should be noted that, in this embodiment, on the basis of the common source 500S, the P-type doped layer 600P and the source 500S are further disposed above the channel layer 200 in a stacked manner, so that the gate 500G can laterally control the N-type conductive channel in the P-type doped layer 600P, which is beneficial to further reducing the size of the semiconductor device.
< example II >
It should be noted that, in the first embodiment, the P-type doped layer 600P is disposed above the channel layer 200 and protrudes from the top surface of the channel layer 200, and the gate 500G can laterally cover the sidewall of the P-type doped layer, so that the formation of the N-type conductive channel in the vertical direction can be controlled. However, in the second embodiment, the P-type doped layer may also be disposed in the channel layer, and the gate 500G may cover the top surface of the P-type doped layer, so that the formation of the N-type conductive channel in the horizontal direction may be controlled.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor device having a high-electron mobility transistor according to a second embodiment of the present invention. In the example shown in fig. 3, the P-type doped layer 600P is disposed in the channel layer 200, and the two-dimensional electron gas 2DEG and the first source/drain electrodes in the channel layer are respectively located at opposite sides of the P-type doped layer 600P.
In this embodiment, the first source/drain is taken as the source electrode 500S, that is, the source electrode 500S and the two-dimensional electron gas 2DEG are respectively located at two opposite sides of the P-type doped layer 600P. And, the gate electrode 500G covers the top surface of the P-type doped layer 600P. At this time, the HEMT device is configured such that the conduction channel thereof includes the two-dimensional electron gas 2DEG in the horizontal direction in the channel layer 200 and the N-type conduction channel in the horizontal direction formed by the P-type doped layer 600P inversion.
In a further embodiment, a first N-type doped layer 610N and a second N-type doped layer 620N are further disposed on two opposite sidewalls of the P-type doped layer 600P, respectively. That is, the first N-type doping layer 610N, the P-type doping layer 600P, and the second N-type doping layer 620N are sequentially arranged along the extending direction of the two-dimensional electron gas 2 DEG. Similarly, in this embodiment, the first N-type doped layer 610N, P-type doped layer 600P and the second N-type doped layer 620N disposed laterally may form an NPN structure, and the gate 500G covers the P-type doped layer 600P and extends to cover at least a portion of the first N-type doped layer 610N and at least a portion of the second N-type doped layer 620N, so as to control the turning on or off of the NPN structure, and accordingly control the turning on or off of the HEMT device.
Specifically, when the HEMT device is turned on, the two-dimensional electron gas 2DEG in the channel layer 200 is connected to the source electrode 500S through the first N-type doped layer 610N, the inversion-formed N-type conduction channel, and the second N-type doped layer 620N. In this embodiment, the source electrode 500S is disposed on the top surface of the second N-type doped layer 620N to be electrically connected to the second N-type doped layer 620.
In addition, similar to the embodiment, the semiconductor device provided in the embodiment may also share the source 500S or the drain 500D between its adjacent HEMT devices. For example, in the example shown in fig. 3, the source 500S is shared by the adjacent HEMT devices, wherein the shared source 500S is disposed between the adjacent HEMT devices, and the two drains 500D of the adjacent HEMT devices are disposed on the two sides of the source 500S, so that the source 500S can form two HEMT devices on the two sides thereof.
With continued reference to fig. 3, P-type doped layers 600P are respectively disposed at both sides of the first source/drain electrode in common, the P-type doped layers 600P are disposed within the channel layer 200, and a gate electrode 500G is formed on a top surface of each of the P-type doped layers 600P. In this embodiment, the first N-type doped layer 610N and the second N-type doped layer 620N are respectively disposed on two sides of the P-type doped layer 600P, at this time, the second N-type doped layers 620N of the two NPN structures in the two adjacent HEMT devices are connected to each other and disposed at a middle position, and the P-type doped layer 600P and the first N-type doped layer 610N are respectively disposed on two sides of the second N-type doped layer 620N. Correspondingly, two gates 500G of two adjacent HEMT devices are respectively arranged on two sides of the source 500S and respectively cover the top surface of the P-type doped layer 600P.
Further, a gate dielectric layer 400 is further disposed between the gate 500G and the P-type doped layer 600P. In this embodiment, the gate dielectric layer 400 covers the top surfaces of the first N-doped layer 610N, the P-doped layer 600P, and the second N-doped layer 620N, and also extends to cover the top surface of the barrier layer 300 for passivation protection of the barrier layer 300. The gate 500G is formed on the gate dielectric layer 400, and the source 500S penetrates the gate dielectric layer 400 to be connected to the second N-type doped layer 620N.
< example three >
Based on the high electron mobility transistor as described above, a method for manufacturing the same will be described in detail below. Referring specifically to fig. 4, the method for forming the high electron mobility transistor may include the following steps.
Step S100, a channel layer and a barrier layer are sequentially formed on a substrate, and at least a partial region of the channel layer is used for generating a two-dimensional electron gas.
Step S200, etching the barrier layer to form an opening, wherein the opening exposes the channel layer.
Step S300, forming a P-type doped layer in the region of the opening.
Step S400, forming a first source/drain electrode, a second source/drain electrode and a gate electrode positioned between the first source/drain electrode and the second source/drain electrode, wherein the first source/drain electrode is arranged on one side of the P-type doped layer far away from the two-dimensional electron gas 2DEG, and the gate electrode covers the P-type doped layer and is used for controlling the P-type doped layer to be inverted to form an N-type conductive channel.
The steps of the high electron mobility transistor of the first embodiment in the process of manufacturing the high electron mobility transistor are described in detail below with reference to fig. 5 to 8.
In step S100, specifically referring to fig. 5, a channel layer 200 and a barrier layer 300 are sequentially formed on a substrate 100. Wherein at least a partial region of the channel layer 200 is used to generate a two-dimensional electron gas.
The substrate 100 may be a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or the like. In a specific example, a transition layer 110 and a buffer layer 120 are also epitaxially grown on the substrate 100. The transition layer 110 is specifically an intrinsic gallium nitride layer or an intrinsic aluminum nitride layer, and the buffer layer 120 is, for example, a gallium nitride layer.
Next, an epitaxial process is sequentially performed on the buffer layer 120 to form a channel layer 200 and a barrier layer 300. The method specifically comprises the following steps: forming an undoped gallium nitride layer by using an epitaxial process to form a channel layer 200; and, an N-doped aluminum gallium nitride layer is formed on the channel layer 200 using an epitaxial process to constitute the barrier layer 300.
In step S200, with continued reference to fig. 5, the barrier layer 300 is etched to form an opening 310, the opening 310 exposing the channel layer 200.
In step S300, referring specifically to fig. 6, a P-type doped layer 600P is formed in the region of the opening 310. The P-type doped layer 600P is used for forming an N-type conduction channel in an inversion mode under the control of the gate, and the N-type conduction channel and the two-dimensional electron gas 2DEG are connected to form a conduction channel of the HEMT device together.
In this embodiment, the forming of the P-type doped layer 600P on the surface of the channel layer 200 exposed to the opening specifically includes: epitaxially growing a P-type material layer covering the barrier layer 300 and the portion of the channel layer 200 exposed to the opening; then, an etching process is performed to remove the portion of the P-type material layer outside the opening region, so as to form a P-type doped layer 600P on the surface of the channel layer in the opening region.
Further, a first N-type doped layer 610N and a second N-type doped layer 620N are respectively formed below and above the P-type doped layer 600P, and the first N-type doped layer 610N, the P-type doped layer 600P and the second N-type doped layer 620N are sequentially stacked on a surface of the channel layer 200 exposed to the opening. Specifically, the preparation method of the first N-type doped layer 610N, the P-type doped layer 600P and the second N-type doped layer 620N includes, for example: sequentially epitaxially growing a first N-type material layer, a P-type material layer and a second N-type material layer; then, an etching process is performed to remove the portions of the first N-type material layer, the P-type material layer, and the second N-type material layer outside the opening region, so as to form the first N-type doped layer 610N, P-type doped layer 600P and the second N-type doped layer 620N stacked in the opening region.
In step S400, referring to fig. 7 to 8 in particular, a first source/drain electrode, a second source/drain electrode and a gate electrode 500G located between the first source/drain electrode and the second source/drain electrode are formed, the first source/drain electrode is disposed on a side of the P-type doped layer 600P away from the two-dimensional electron gas 2DEG, and the gate electrode 500G covers the P-type doped layer 600P for controlling the P-type doped layer 600P to form an N-type conduction channel in an inversion manner.
Before forming the source 500S, the drain 500D and the gate 500G, the method further includes: a gate dielectric layer 400 is formed, wherein the gate dielectric layer 400 covers the P-type doped layer 600P and the barrier layer 300. In this embodiment, the gate dielectric layer 400 specifically covers the top surface of the second N-type doped layer 620N, and also covers the sidewalls of the second N-type doped layer 620N, the P-type doped layer 600P, and the first N-type doped layer 610N.
And forming the source electrode 500S, the drain electrode 500D and the gate electrode 500G after forming the gate dielectric layer 400, in this embodiment, the source electrode 500S penetrates through the gate dielectric layer 400 and is connected to the second N-type doping layer 620N, the drain electrode 500D penetrates through the barrier layer 300 and is formed on the channel layer 200, the drain electrode 500D is connected to one end of the two-dimensional electron gas 2DEG, and the source electrode 500S is disposed at the other end of the two-dimensional electron gas 2DEG and is spaced apart from the two-dimensional electron gas 2DEG by a P-type doping layer 600P.
< example four >
This embodiment will describe in detail each step of the high electron mobility transistor in the second embodiment in the manufacturing process thereof with reference to fig. 4 and fig. 9 to fig. 10.
Step S100 and step S200 in this embodiment are similar to the steps S100 and S200 in the third embodiment, and are not described again here.
In step S300, referring specifically to fig. 9, a P-type doped layer 600P is formed in the region of the opening 310. In this embodiment, the P-type doped layer 600P is formed in a portion of the channel layer 200 exposed to the opening.
Specifically, P-type ion implantation may be performed on a portion of the channel layer 200 exposed to the opening to form the P-type doped layer 600P. In a specific example, the material of the channel layer 200 includes gallium nitride, and magnesium ions may be implanted into the channel layer 200 to form the P-type doped layer 600P.
With continued reference to fig. 9, the preparation method in this embodiment further includes: and performing N-type ion implantation on the exposed portion of the channel layer 200 to form a first N-type doped layer 610N and a second N-type doped layer 620N, where the first N-type doped layer 610N and the second N-type doped layer 620N are respectively located at two opposite sides of the P-type doped layer 600P, thereby forming an NPN structure.
In step S400, referring specifically to fig. 10, a first source/drain, a second source/drain, and a gate electrode 500G between the first source/drain and the second source/drain are formed.
Similarly to the third embodiment, in the present embodiment, before forming the source electrode 500S, the drain electrode 500D, and the gate electrode 500G, the method further includes: a gate dielectric layer 400 is formed, the gate dielectric layer 400 covering the top surfaces of the first N-doped layer 610N, P type doped layer 600P and the second N-doped layer 620N and also covering the top surface of the barrier layer 300.
After the gate dielectric layer 400 is formed, the source electrode 500S, the drain electrode 500D and the gate electrode 500G are formed. In this embodiment, the source electrode 500S penetrates the gate dielectric layer 400 to be connected to the second N-type doping layer 620N, the drain electrode 500D penetrates the barrier layer 300 to be formed on the channel layer 200, similarly, the drain electrode 500D is connected to one end of the two-dimensional electron gas 2DEG, and the source electrode 500S is disposed at the other end of the two-dimensional electron gas 2DEG with a P-type doping layer 600P interposed between the source electrode and the two-dimensional electron gas 2 DEG. And, the gate electrode 500G is formed on the gate dielectric layer 400 and covers the top surface of the P-type doped layer 600P.
In the high electron mobility transistor, the P-type doped layer is disposed between the first source/drain electrode and the two-dimensional electron gas, and the inversion of the P-type doped layer is controlled by the gate to form the N-type conduction channel, so that the two-dimensional electron gas 2DEG in the channel layer can be connected to the N-type conduction channel formed by the inversion in the P-type doped layer, thereby realizing current flow between the first source/drain electrode and the second source/drain electrode. That is, the HEMT device described above controls inversion of the P-type doped layer by the gate, and thus turns on or off the HEMT device. Compared with the traditional HEMT device which uses the grid to exhaust two-dimensional electron gas in the channel layer, the HEMT device of the invention can more flexibly adjust the grid voltage for controlling the inversion of the P-type doping layer, is beneficial to improving the threshold voltage of the HEMT device, and can enable the threshold voltage of the HEMT device to reach more than 3V.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Also, while the present invention has been described with reference to the preferred embodiments, the embodiments are not intended to be limiting. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should also be noted that references in the specification to "one embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
And it should be understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not used to indicate a logical or sequential relationship between various components, elements, steps, and the like, unless otherwise specified or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims (18)

1. A high electron mobility transistor, comprising: a channel layer and a barrier layer formed in this order on a substrate, at least a partial region of the channel layer being for generating a two-dimensional electron gas; a first source/drain and a second source/drain formed on the channel layer; a gate between the first source/drain and the second source/drain; and the number of the first and second groups,
the high electron mobility transistor further includes: the P-type doping layer is at least arranged between the two-dimensional electron gas and the first source/drain electrode, and the grid covers the P-type doping layer and is used for controlling the inversion of the P-type doping layer to form an N-type conducting channel.
2. The hemt of claim 1, wherein said P-type doped layer is formed above said channel layer, said first source/drain is formed above said P-type doped layer, and said gate covers sidewalls of said P-type doped layer.
3. The hemt of claim 2, further comprising: the first N-type doped layer, the P-type doped layer and the second N-type doped layer are sequentially stacked on the channel layer, and the first source/drain is disposed on a top surface of the second N-type doped layer.
4. The hemt of claim 1, wherein said P-type doped layer is formed in said channel layer, said two-dimensional electron gas and said first source/drain are located on opposite sides of said P-type doped layer, respectively, and said gate covers a top surface of said P-type doped layer.
5. The high electron mobility transistor according to claim 4, further comprising: the first N-type doped layer, the P-type doped layer and the second N-type doped layer are sequentially arranged along the extending direction of the two-dimensional electron gas, and the first source/drain electrode is arranged on the top surface of the second N-type doped layer.
6. The hemt of claim 1, further comprising a gate dielectric layer disposed between said gate and said P-type doped layer, said gate dielectric layer overlying said P-type doped layer and extending over a top surface of said barrier layer.
7. The hemt of claim 1, wherein a first N-type doped layer and a second N-type doped layer are disposed on both sides of said P-type doped layer along a direction of an N-type conduction channel, respectively, and said gate electrode covers said P-type doped layer and extends over at least a portion of said first N-type doped layer and at least a portion of said second N-type doped layer.
8. A method for preparing a high electron mobility transistor is characterized by comprising the following steps:
sequentially forming a channel layer and a barrier layer on a substrate, wherein at least part of the region of the channel layer is used for generating two-dimensional electron gas;
etching the barrier layer to form an opening that exposes the channel layer;
forming a P-type doped layer in the region of the opening; and the number of the first and second groups,
and forming a first source/drain electrode, a second source/drain electrode and a grid electrode positioned between the first source/drain electrode and the second source/drain electrode, wherein the first source/drain electrode is arranged on one side of the P-type doped layer away from the two-dimensional electron gas, and the grid electrode covers the P-type doped layer and is used for controlling the P-type doped layer to reversely form an N-type conductive channel.
9. The method of manufacturing a high electron mobility transistor according to claim 8, wherein the method of forming the P-type doped layer comprises:
epitaxially growing a P-type material layer covering portions of the barrier layer and the channel layer exposed to the opening; and the number of the first and second groups,
and performing an etching process to remove the part of the P-type material layer outside the opening region so as to form the P-type doped layer on the surface of the channel layer in the opening region.
10. The method of manufacturing a high electron mobility transistor according to claim 9, further comprising: and respectively forming a first N-type doping layer and a second N-type doping layer below and above the P-type doping layer, wherein the first N-type doping layer, the P-type doping layer and the second N-type doping layer are sequentially stacked on the surface of the channel layer exposed to the opening.
11. The method of claim 10, wherein the first source/drain is formed on the second N-type doped layer and the gate covers a sidewall of the P-type doped layer.
12. The method of manufacturing a high electron mobility transistor according to claim 8, wherein the method of forming the P-type doped layer comprises: and performing P-type ion implantation on the part of the channel layer exposed to the opening to form the P-type doped layer.
13. The method of manufacturing a high electron mobility transistor according to claim 12, further comprising: and performing N-type ion implantation on the part of the channel layer exposed to the opening to form a first N-type doped layer and a second N-type doped layer, wherein the first N-type doped layer and the second N-type doped layer are respectively positioned at two opposite sides of the P-type doped layer.
14. The method of claim 13, wherein the first source/drain is formed on the second N-type doped layer and the gate covers a top surface of the P-type doped layer.
15. A semiconductor device, comprising: the high electron mobility transistor according to any one of claims 1 to 7.
16. The semiconductor device according to claim 15, wherein the semiconductor device comprises at least two high electron mobility transistors, wherein adjacent high electron mobility transistors share a first source/drain.
17. The semiconductor device according to claim 16, wherein the first source/drain is provided between adjacent high electron mobility transistors and above the channel layer, and a P-type doped layer is provided between the first source/drain and the channel layer, and a gate is formed on sidewalls on both sides of the P-type doped layer, respectively.
18. The semiconductor device according to claim 16, wherein the first source/drain is disposed between adjacent high electron mobility transistors, and P-type doped layers are disposed on both sides of the first source/drain, respectively, the P-type doped layers being disposed in the channel layer, and a gate electrode being formed on a top surface of each P-type doped layer.
CN202210813878.1A 2022-07-11 2022-07-11 High electron mobility transistor, preparation method thereof and semiconductor device Pending CN115101595A (en)

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