CN115101501A - Single chip package structure - Google Patents

Abstract

The invention provides a single-chip package structure, which includes a lead frame, and a functional chip located on a chip mounting area and packaged in a plastic package, wherein the functional chip is used for electrical connection with a semiconductor capacitor deployed in an external circuit. In the present invention, the semiconductor capacitor and the functional chip are separately deployed, the semiconductor capacitor is arranged in the external circuit, and the functional chip is packaged on a single chip, which can reduce the volume of the package structure and thus widen its application scenarios. Moreover, reducing one plastic body can reduce one fault location, thereby improving product reliability.

Description

Single chip package structure

technical field

The invention relates to the field of chip technology, in particular to a single-chip packaging structure.

Background technique

Based on the current technological development of automotive electronics, in order to solve the electromagnetic compatibility (EMC, Electromagnetic Compatibility) capability, as shown in Figure 1, the industry used the following two separate plastic packages:

The functional chip 1 and the metal chip capacitor 2 are separately packaged to form two plastic bodies 3 and 4 to realize the thin shape of the chip head plastic body 3, and the metal chip capacitor 2 is used to enhance the EMC resistance. Among them, EMC refers to the ability of a device or system to operate compliantly in its electromagnetic environment without causing intolerable electromagnetic disturbance to any device in its environment.

In this way, when electromagnetic interference is introduced from the power supply terminal and the functional chip itself, the introduction of the chip capacitor between the power supply and the ground can play the role of electrical filtering, thereby improving the EMC resistance of the corresponding device of the packaged device.

However, in practical applications, it is found that the corresponding packaging device adopts a separate plastic body, although it can enhance the EMC resistance, but the separate double plastic body leads to a large product, which limits the application scenarios of the product.

SUMMARY OF THE INVENTION

In view of the problems in the prior art, the purpose of the present invention is to provide a single-chip package structure, which can reduce the volume of the package structure product, and thus is expected to widen its application scenarios.

An embodiment of the present invention provides a single-chip packaging structure, which includes:

a lead frame, including a chip mounting area at the head and pins extending from the chip mounting area;

A functional chip located on the chip mounting area and packaged in a plastic package, wherein the functional chip is used for electrical connection with a semiconductor capacitor in an external circuit.

Optionally, the leads of the functional chip are packaged in the plastic package and are electrically connected to the corresponding pins.

Optionally, between the power access terminal of the functional chip and the power supply pin, the ground terminal and the ground pin of the functional chip are electrically connected by wire bonding.

Optionally, the thickness of the lead frame ranges from 0.1 to 1 mm.

Optionally, the thickness of the plastic package is between 0.5mm and 3mm.

Optionally, the lead frame is made of metal.

The single-chip packaging structure provided by the present invention has the following advantages:

The single-chip package structure includes a lead frame, and a functional chip located on the chip mounting area and packaged in a plastic package. The functional chip is used for electrical connection with a semiconductor capacitor in an external circuit.

In the present invention, the semiconductor capacitor and the functional chip are separately deployed, the semiconductor capacitor is arranged in an external circuit, and the functional chip is packaged on a single chip, which can reduce the volume of the package structure and thus widen its application scenarios. Moreover, reducing one plastic body can reduce one fault location, thereby improving product reliability.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings.

1 is a front cross-sectional view of a package structure of the prior art;

2 is a front cross-sectional view of a single-chip package structure provided by an embodiment of the present disclosure;

3 is a side cross-sectional view of a single-chip package structure provided by an embodiment of the present disclosure;

4 is a circuit diagram of a package in a single-chip package structure according to an embodiment of the present invention.

Detailed ways

The embodiments of the present application are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied to the system through other different specific embodiments, and various details in the present application can also be modified or changed according to different viewpoints and applied systems without departing from the spirit of the present application. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other under the condition of no conflict.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art to which the present application pertains can easily implement. The present application can be embodied in many different forms, and is not limited to the embodiments described herein.

In the representations of this application, references to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., are intended to be combined with the specific features represented by the embodiment or example. , structure, material or feature is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials or characteristics shown may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples presented in this application, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the expression of this application, "plurality" means two or more, unless expressly and specifically defined otherwise.

In order to clearly describe the present application, components irrelevant to the description are omitted, and the same or similar components are assigned the same reference numerals throughout the specification.

Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when it is said that a certain device "includes" a certain constituent element, unless there is no particular description to the contrary, it does not exclude other constituent elements, but means that other constituent elements may also be included.

When a device is said to be "on" another device, this can be directly on the other device, but it can also be accompanied by other devices in between. When a device is said to be "directly on" another device in contrast, there are no other devices in between.

Although in some instances the terms first, second, etc. are used herein to refer to various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first interface and the second interface, etc. are represented. Also, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context dictates otherwise. It should be further understood that the terms "comprising" and "comprising" indicate the presence of features, steps, operations, elements, components, items, kinds, and/or groups, but do not exclude one or more other features, steps, operations, elements, The existence, appearance or addition of components, items, categories, and/or groups. The terms "or" and "and/or" as used herein are to be construed to be inclusive or to mean any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C" . Exceptions to this definition arise only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the application. The singular form used here also includes the plural form, as long as the sentence does not clearly express the opposite meaning. The meaning of "comprising" as used in the specification is to embody particular characteristics, regions, integers, steps, operations, elements and/or components, but not to exclude other characteristics, regions, integers, steps, operations, elements and/or components exist or append.

Although not defined differently, including technical and scientific terms used herein, all terms have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms defined in commonly used dictionaries are additionally interpreted to have meanings consistent with the content of the relevant technical literature and current tips, and as long as they are not defined, they should not be unduly interpreted as ideal or very formulaic meanings.

Analysis of related technologies shows that in the single-chip package structure, the main problem of the double-molded body structure is that the volume of the metal chip capacitor is too large, so that it must be individually plastic-packaged. Therefore, if we want to reduce the package volume and improve the product integration without reducing the EMC resistance, we need to solve the problem of large capacitance.

In order to solve the technical problems of the related art, an embodiment of the present disclosure provides a new single-chip package structure, the single-chip package structure includes a lead frame, and a functional chip located on the chip mounting area and packaged in a plastic package, wherein the functional chip uses It is used for electrical connection with semiconductor capacitors deployed in external circuits to enhance EMC immunity.

The semiconductor capacitor structure is based on a metal-oxide-metal (MOM) structure that can be fabricated in standard CMOS processes without additional cost. A capacitor constructed with an oxide layer as a dielectric material. However, as is widely known by those who are familiar with semiconductor manufacturing technology, the core concept of the present invention is not necessarily realized by the materials described in the embodiments, and other common or innovative conductive materials or dielectric materials can also be used to realize the present invention. Invention of the semiconductor capacitor structure.

In the embodiment of the present disclosure, compared with the metal chip capacitor and the functional chip in the related art using a separate plastic package structure, the present invention separates the semiconductor capacitor from the functional chip, arranges the semiconductor capacitor in the external circuit, and disposes of the functional chip. Single-chip packaging can be performed, which can reduce the volume of the packaging structure, thereby broadening its application scenarios. Moreover, reducing one plastic body can reduce one fault location, thereby improving product reliability.

FIG. 2 is a front cross-sectional view of a single-chip package structure provided by an embodiment of the present disclosure, and FIG. 3 is a side cross-sectional view of the single-chip package structure provided by an embodiment of the present disclosure. Referring to FIGS. 2 and 3 , the package device includes:

The lead frame 20 includes a chip mounting area 21 located at the head and pins 22 extending from the chip mounting area 21;

A functional chip 41 located on the chip mounting area 21 and packaged in the plastic package 30, wherein the functional chip 41 is used for electrical connection with a semiconductor capacitor (not shown in the figure) deployed in an external circuit.

With such a solution, in an application example, referring to FIG. 4 , the semiconductor capacitor 42 and the functional chip 41 are connected in parallel. The semiconductor capacitor 42 plays the role of electrical filtering. When electromagnetic interference is introduced from the power supply terminal VCC (which is regarded as external EMC) and the functional chip (Die) (which is regarded as internal EMC) 41 itself, the electromagnetic interference can pass through the semiconductor. Capacitor 42 is electrically filtered to ground GND without affecting the operation of Die.

In the embodiment of the present disclosure, the semiconductor capacitor 42 is a silicon-based chip capacitor.

Only one functional chip 41 is shown in FIG. 2 and FIG. 3 , which is only an example. In other embodiments, the number of functional chips may also be other, which is not specifically limited herein.

Wherein, the functional chip 41 can be adhered to the carrier area 21 by a patch glue. The plastic sealing body 30 may use a plastic sealing compound resin for packaging the functional chips 41, and a large amount of filler is filled in the plastic sealing compound resin.

In the corresponding process, the functional chip 41 itself is covered with insulating material, or the material of the plastic package 30 also has insulating properties, so that mutual interference will not occur.

The embodiments of the present disclosure provide a single-chip single-package package design solution based on a lead frame. For the first time in the industry, a single functional chip is packaged in the mounting area and packaged into a single plastic package to achieve a new single-chip package structure with a compact shape.

In an embodiment of the present disclosure, the leads of the functional chip 41 are encapsulated in the plastic package 30 and are electrically connected to the corresponding pins. At this time, the plastic package 30 has a protective effect on the leads.

In one embodiment, FIG. 2 and FIG. 3 show two pins 22, which can be used to connect the power terminal and the ground, respectively, one of which is a power pin, and the other pin is a ground pin.

In other optional application scenarios, the lead frame can have other functional pins or other numbers of pins, and the lead connections can be adjusted as required, which is not limited here.

In an embodiment of the present disclosure, wire bonding is used for electrical connection between the power access terminal of the function chip 41 and the power supply pins, and between the ground terminal and the ground pins of the function chip 41 .

In the packaging process, the wires of the functional chip 41 are formed by a wire bonding process. Wire bonding is a method of using thin metal wires, and using heat, pressure and ultrasonic energy to tightly bond the metal wires to the pads corresponding to the mounting area 21 .

In an optional embodiment, the leads of the functional chip 41 and the semiconductor capacitor 42 may be copper wires or gold wires.

In the embodiment of the present disclosure, the thickness h ₁ of the lead frame 20 ranges from 0.1 to 1 mm. If the thickness of the lead frame 20 is less than 0.1, the die mounting area 11 will not be able to effectively support the plastic package 30; and if the thickness of the lead frame 20 is higher than 1 mm, a cost problem will arise.

In an embodiment of the present disclosure, the thickness h ₂ of the plastic sealing body 30 is between 0.5 mm and 3 mm. By setting the thickness of the plastic encapsulation body 30 to be not less than 0.5 mm, a stable package can be formed for the semiconductor capacitor 42 and the functional chip 41, and the function of moisture-proof isolation can be achieved. By setting the thickness of the plastic encapsulation body 30 to be no greater than 3 mm, a suitable degree of product integration can be provided.

In an embodiment of the present disclosure, the lead frame is made of metal.

Embodiments of the present disclosure also provide a magnetic sensor, which is formed in the single-chip package structure, so that the functional chip is a magnetic sensor chip.

A magnetic sensor is a device that converts the magnetic properties of sensitive components caused by external factors such as magnetic field, current, stress and strain, temperature, and light into electrical signals, and detects the corresponding physical quantities in this way. Magnetic sensors are widely used in modern industry and electronic products to measure physical parameters such as current, position, and direction by sensing the strength of magnetic fields. There are also many different types of sensors used to measure magnetic fields and other parameters.

For example, magnetic sensors are widely used in industrial control and automotive electronics to provide a new generation of automotive-grade, low-profile, one-piece packages with enhanced EMC immunity.

Wherein, the basic unit of the magnetic sensor may have a single-chip package structure as shown in FIG. 2 and FIG. 3 . On this basis, other components can also be added to form the final product of the magnetic sensor.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. A single chip package structure, comprising:

the lead frame comprises a chip mounting area positioned at the head part and pins extending from the chip mounting area;

and the functional chip is positioned on the mounting area and packaged in the plastic package, and is used for being electrically connected with the semiconductor capacitor arranged in the external circuit.

2. The single chip package structure of claim 1, wherein the leads of the functional chip are packaged in the plastic package and electrically connected to the corresponding leads.

3. The single chip package structure of claim 2, wherein the power access terminal of the functional chip is electrically connected to the power pin, and the ground terminal of the functional chip is electrically connected to the ground pin by wire bonding.

4. The single chip package structure of claim 1, wherein the thickness of the lead frame is in the range of 0.1-1 mm.

5. The single chip package structure of claim 1, wherein the molding compound thickness is between 0.5mm and 3 mm.

6. The single chip package structure of claim 1, wherein the lead frame is made of metal.

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