CN115101501A - Single chip packaging structure - Google Patents

Single chip packaging structure Download PDF

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Publication number
CN115101501A
CN115101501A CN202210901064.3A CN202210901064A CN115101501A CN 115101501 A CN115101501 A CN 115101501A CN 202210901064 A CN202210901064 A CN 202210901064A CN 115101501 A CN115101501 A CN 115101501A
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CN
China
Prior art keywords
chip
single chip
functional
functional chip
package structure
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Pending
Application number
CN202210901064.3A
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Chinese (zh)
Inventor
尹小平
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Cosemitech (shanghai) Co ltd
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Cosemitech (shanghai) Co ltd
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Priority to CN202210901064.3A priority Critical patent/CN115101501A/en
Publication of CN115101501A publication Critical patent/CN115101501A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a single chip packaging structure which comprises a lead frame and a functional chip, wherein the functional chip is positioned on a chip mounting area and packaged in a plastic package, and the functional chip is used for being electrically connected with a semiconductor capacitor arranged in an external circuit. In the invention, the semiconductor capacitor and the functional chip are respectively deployed, the semiconductor capacitor is arranged in an external circuit, and the functional chip is packaged in a single chip, so that the volume of the packaging structure can be reduced, and the application scene of the packaging structure can be widened. Moreover, one plastic package body is reduced, so that a fault part can be reduced, and the reliability of the product is improved.

Description

Single chip packaging structure
Technical Field
The invention relates to the technical field of chips, in particular to a single-chip packaging structure.
Background
Based on the current technical development of automotive electronics, in order to solve the problem of Electromagnetic Compatibility (EMC) resistance, as shown in fig. 1, the following two separate plastic packages are adopted:
the functional chip 1 and the metal sheet-type capacitor 2 are packaged separately to form two plastic package bodies 3 and 4, so that the thin appearance of the chip head plastic package body 3 is realized, and the EMC resistance is enhanced through the metal sheet-type capacitor 2. EMC refers to the ability of a device or system to operate satisfactorily in its electromagnetic environment without producing intolerable electromagnetic disturbance to any device in its environment.
Therefore, when electromagnetic interference is introduced from the power supply end and the functional chip, the chip capacitor is introduced between the power supply and the ground to play a role in electrical filtering, so that the EMC resistance of a corresponding device of the packaged device can be improved.
However, in practical applications, it is found that the separate plastic package body is adopted for the corresponding packaged device, and although the EMC resistance can be enhanced, the separate double plastic package body leads to a large product volume, which limits the application scenarios of the product.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a single chip package structure, which can reduce the volume of the package structure product, and thus is expected to widen the application scenarios thereof.
An embodiment of the present invention provides a single chip package structure, which includes:
the lead frame comprises a chip mounting area positioned at the head part and pins extending from the chip mounting area;
and the functional chip is positioned on the chip mounting area and packaged in the plastic package, and is used for being electrically connected with a semiconductor capacitor in an external circuit.
Optionally, the leads of the functional chip are packaged in the plastic package and electrically connected to the corresponding pins.
Optionally, the power supply access end of the functional chip is electrically connected to the power supply pin, and the ground end of the functional chip is electrically connected to the ground pin through wire bonding.
Optionally, the thickness of the lead frame ranges from 0.1 mm to 1 mm.
Optionally, the plastic package body has a thickness of between 0.5mm and 3 mm.
Optionally, the lead frame is made of a metal material.
The single chip packaging structure provided by the invention has the following advantages:
the single chip packaging structure comprises a lead frame and a functional chip which is positioned on the chip mounting area and packaged in the plastic package, wherein the functional chip is used for being electrically connected with a semiconductor capacitor in an external circuit.
In the invention, the semiconductor capacitor and the functional chip are respectively deployed, the semiconductor capacitor is arranged in an external circuit, and the functional chip is packaged in a single chip, so that the volume of the packaging structure can be reduced, and the application scene of the packaging structure can be widened. Moreover, one failure part can be reduced by reducing one plastic package body, thereby improving the reliability of the product.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments thereof, with reference to the following drawings.
FIG. 1 is a front cross-sectional view of a prior art package structure;
fig. 2 is a front cross-sectional view of a single chip package structure according to an embodiment of the present disclosure;
fig. 3 is a side cross-sectional view of a single chip package structure according to an embodiment of the present disclosure;
fig. 4 is a circuit diagram of a package in a single chip package structure according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present application. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings so that those skilled in the art to which the present application pertains can easily carry out the present application. The present application may be embodied in many different forms and is not limited to the embodiments described herein.
Reference throughout this specification to "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics illustrated may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of different embodiments or examples presented in this application can be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the expressions of the present application, "plurality" means two or more unless specifically defined otherwise.
In order to clearly explain the present application, components that are not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.
Throughout the specification, when a device is referred to as being "connected" to another device, this includes not only the case of being "directly connected" but also the case of being "indirectly connected" with another element interposed therebetween. In addition, when a device "includes" a certain component, unless otherwise stated, the device does not exclude other components, but may include other components.
When a device is said to be "on" another device, this may be directly on the other device, but may also be accompanied by other devices in between. When a device is said to be "directly on" another device, there are no other devices in between.
Although the terms first, second, etc. may be used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first interface and the second interface are represented. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" include plural forms as long as the words do not expressly indicate a contrary meaning. The term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and/or components.
Although not defined differently, including technical and scientific terms used herein, all terms have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms defined in commonly used dictionaries are to be additionally interpreted as having meanings consistent with those of related art documents and the contents of the present prompts, and must not be excessively interpreted as having ideal or very formulaic meanings unless defined.
Analysis of the related art reveals that, in a single chip package structure, the main problem of the dual plastic package structure is that the volume of the metal sheet capacitor is too large, so that the metal sheet capacitor must be separately plastic-packaged. Therefore, if the packaging volume is reduced and the product integration level is improved without reducing the anti-EMC capability, the problem of large capacitance volume needs to be solved.
In order to solve the technical problems of the related art, the embodiments of the present disclosure provide a new single chip package structure, which includes a lead frame, and a functional chip located on a die attach area and packaged in a plastic package, wherein the functional chip is used for electrically connecting with a semiconductor capacitor disposed in an external circuit to enhance EMC resistance.
The semiconductor capacitor structure is based on a metal-oxide-metal (MOM) structure that can be fabricated in a standard CMOS process without additional cost, i.e., a capacitor formed by using a metal layer as a conductive material and an oxide layer as a dielectric material. However, as is well known to those skilled in the art of semiconductor manufacturing, the core concept of the present invention is not necessarily implemented by the materials described in the embodiments, and various other common or novel conductive materials or dielectric materials can be used to implement the semiconductor capacitor structure of the present invention.
In the embodiment of the disclosure, compared with the structure that the metal chip capacitor and the functional chip are separated by the plastic package body in the related art, the semiconductor capacitor and the functional chip are separated, the semiconductor capacitor is arranged in an external circuit, and the functional chip is packaged in a single chip, so that the size of the packaging structure can be reduced, and the application scene of the packaging structure can be widened. Moreover, one failure part can be reduced by reducing one plastic package body, thereby improving the reliability of the product.
Fig. 2 is a front sectional view of a single chip package structure provided in an embodiment of the disclosure, fig. 3 is a side sectional view of the single chip package structure provided in the embodiment of the disclosure, and referring to fig. 2 and fig. 3, the package device includes:
a lead frame 20 including a mounting region 21 at a head portion and leads 22 extending from the mounting region 21;
and a functional chip 41 located on the die-bonding area 21 and encapsulated in the plastic package 30, wherein the functional chip 41 is used for electrically connecting with a semiconductor capacitor (not shown in the figure) disposed in an external circuit.
By adopting the scheme, in an application example, referring to fig. 4, the semiconductor capacitor 42 and the functional chip 41 are connected in parallel. The semiconductor capacitor 42 functions as an electrical filter, and when electromagnetic interference is introduced from the power supply terminal VCC (considered as EMC from the outside) and the functional chip (Die) (considered as EMC from the inside) 41 itself, the electromagnetic interference can be electrically filtered to the ground GND through the semiconductor capacitor 42 without affecting the operation of Die.
In the embodiment of the present disclosure, the semiconductor capacitor 42 is a chip capacitor based on silicon material.
Fig. 2 and 3 only show one functional chip 41, which is only an example, and in other embodiments, the number of functional chips may be other, and is not limited specifically herein.
Wherein, the functional chip 41 can be adhered to the carrier region 21 by the patch adhesive. The molding compound 30 may use a molding compound resin for packaging the functional chip 41, and the molding compound resin is filled with a large amount of filler.
In the corresponding process, the functional chip 41 itself is wrapped by the insulating material, or the plastic package 30 material has insulation, and will not interfere with each other.
The embodiment of the disclosure provides a single-chip single-package body packaging design scheme based on a lead frame, and an individual functional chip is packaged in a chip packaging area for the first time in the industry and packaged in a single plastic package body, so that a simple appearance of a new single-chip packaging structure is realized.
In an embodiment of the present disclosure, the leads of the functional chip 41 are encapsulated in the plastic package body 30 and electrically connected to the corresponding pins, and at this time, the plastic package body 30 has a protection effect on the leads.
In one embodiment, fig. 2 and 3 show two pins 22 that may be used to connect a power terminal and a ground, respectively, where one pin is a power pin and the other pin is a ground pin.
In other optional application scenarios, the lead frame may have other functional pins or other number of pins, and the wire connection may be adjusted according to the need, which is not limited herein.
In an embodiment of the present disclosure, the power source access terminal of the functional chip 41 is electrically connected to the power source pin, and the ground terminal of the functional chip 41 is electrically connected to the ground pin by wire bonding.
During the packaging process, the leads of the functional chip 41 are formed using a wire bonding process. Wire Bonding (Wire Bonding) is a process that uses a thin metal Wire and uses heat, pressure, and ultrasonic energy to bond the metal Wire tightly to the corresponding pad of the mounting region 21.
In alternative embodiments, the leads of the functional chip 41 and the semiconductor capacitor 42 may be copper wires or gold wires.
In the disclosed embodiment, the thickness h of the lead frame 20 1 The range is 0.1 to 1 mm. Wherein if the thickness of the lead frame 20 is less than 0.1, the die bonding area 11 will not support the plastic package body 30 effectively; and if the thickness of the lead frame 20 is more than 1mm, a cost problem is caused.
In one embodiment of the present disclosure, the plastic package body 30 has a thickness h 2 Between 0.5mm and 3 mm. By setting the thickness of the plastic package body 30 to be not less than 0.5mm, stable packaging can be formed for the semiconductor capacitor 42 and the functional chip 41, and a moisture-proof isolation effect is achieved. By setting the thickness of the plastic package body 30 to be not more than 3mm, a suitable product integration level can be provided.
In one embodiment of the present disclosure, the lead frame is made of metal.
The embodiment of the present disclosure further provides a magnetic sensor, where the magnetic sensor is formed in the single chip package structure, and thus the functional chip is a magnetic sensor chip.
The magnetic sensor is a device for converting the change of the magnetic property of a sensitive element caused by external factors such as magnetic field, current, stress strain, temperature, light, etc. into an electric signal, and detecting the corresponding physical quantity in this way. Magnetic sensors are widely used in modern industry and electronics to sense magnetic field strength to measure physical parameters such as current, position, orientation, etc. there are many different types of sensors used to measure magnetic fields and other parameters.
For example, magnetic sensors are widely used in industrial control and automotive electronics, and can provide a new generation of thin, integrated packages with enhanced EMC resistance at automotive level.
The basic unit of the magnetic sensor can be a single chip package structure as shown in fig. 2 and 3. On the basis, other components can be added to form a finished product of the final magnetic sensor.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A single chip package structure, comprising:
the lead frame comprises a chip mounting area positioned at the head part and pins extending from the chip mounting area;
and the functional chip is positioned on the mounting area and packaged in the plastic package, and is used for being electrically connected with the semiconductor capacitor arranged in the external circuit.
2. The single chip package structure of claim 1, wherein the leads of the functional chip are packaged in the plastic package and electrically connected to the corresponding leads.
3. The single chip package structure of claim 2, wherein the power access terminal of the functional chip is electrically connected to the power pin, and the ground terminal of the functional chip is electrically connected to the ground pin by wire bonding.
4. The single chip package structure of claim 1, wherein the thickness of the lead frame is in the range of 0.1-1 mm.
5. The single chip package structure of claim 1, wherein the molding compound thickness is between 0.5mm and 3 mm.
6. The single chip package structure of claim 1, wherein the lead frame is made of metal.
CN202210901064.3A 2022-07-28 2022-07-28 Single chip packaging structure Pending CN115101501A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210901064.3A CN115101501A (en) 2022-07-28 2022-07-28 Single chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210901064.3A CN115101501A (en) 2022-07-28 2022-07-28 Single chip packaging structure

Publications (1)

Publication Number Publication Date
CN115101501A true CN115101501A (en) 2022-09-23

Family

ID=83300285

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210901064.3A Pending CN115101501A (en) 2022-07-28 2022-07-28 Single chip packaging structure

Country Status (1)

Country Link
CN (1) CN115101501A (en)

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