CN115101446A - PVD (physical vapor deposition) coating equipment and coating method of heterojunction battery - Google Patents
PVD (physical vapor deposition) coating equipment and coating method of heterojunction battery Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
- C23C14/568—Transferring the substrates through a series of coating stations
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
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- Life Sciences & Earth Sciences (AREA)
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- Physical Vapour Deposition (AREA)
Abstract
The invention relates to the technical field of battery manufacturing, and provides PVD (physical vapor deposition) coating equipment, which comprises: the first process chamber is provided with a first sputtering cathode, and the first sputtering cathode is used for loading the TCO target material; the second process cavity is provided with a second sputtering cathode, and the second sputtering cathode is used for loading the metal seed target; the third process cavity is provided with a third sputtering cathode, and the second sputtering cathode is used for loading a mask target; the first vacuum pump is arranged between the first process cavity and the second process cavity and between the second process cavity and the third process cavity and is used for maintaining the atmosphere of each process cavity; the conveying mechanism is used for loading materials to be processed and driving the materials to be processed to move in the first process cavity, the second process cavity and the third process cavity. Can realize the integrated film coating of single equipment and reduce the production cost.
Description
Technical Field
The invention relates to the technical field of battery manufacturing, in particular to PVD (physical vapor deposition) coating equipment and a coating method of a heterojunction battery.
Background
Heterojunction cells have received much attention for their advantages, such as simple structure, high process temperature, high conversion efficiency, and good temperature coefficient. When the heterojunction battery is processed, at least three coatings are required to be sequentially carried out: a TCO (Transparent Conductive Oxide) plating layer, a metal seed plating layer, and a plating mask. In actual processing, a material to be processed needs to be transferred among a plurality of Physical Vapor Deposition (PVD) coating devices, which affects the processing efficiency of the heterojunction battery, and the PVD coating devices are expensive and also affects the production cost of the heterojunction battery.
Disclosure of Invention
The invention provides PVD (physical vapor deposition) coating equipment and a coating method of a heterojunction battery, which are used for solving the defect of high production cost of the heterojunction battery in the prior art, realizing the integrated coating of single equipment and reducing the production cost.
The invention provides a PVD coating equipment, comprising:
the first process chamber is provided with a first sputtering cathode, and the first sputtering cathode is used for loading TCO target materials;
the second process cavity is provided with a second sputtering cathode, and the second sputtering cathode is used for loading a metal seed target;
the third process cavity is provided with a third sputtering cathode, and the second sputtering cathode is used for loading a mask target;
the first vacuum pump is arranged between the first process cavity and the second process cavity and between the second process cavity and the third process cavity and is used for maintaining the atmosphere of each process cavity;
the conveying mechanism is used for loading materials to be processed and driving the materials to be processed to move in the first process cavity, the second process cavity and the third process cavity.
According to the invention, the PVD coating equipment also comprises:
and the PECVD cavity is arranged at the front end of the first process cavity.
According to the PVD coating equipment provided by the invention, the first process chamber, the second process chamber and the third process chamber are positioned in the same process chamber.
According to the PVD coating equipment provided by the invention, the first sputtering cathode, the second sputtering cathode and the third sputtering cathode respectively comprise two sputtering cathodes which are oppositely arranged along the vertical direction, the first vacuum pumps are respectively arranged in the middle parts of the first process cavity, the second process cavity and the third process cavity, and the number of the first vacuum pumps arranged in the middle part of each process cavity is smaller than that of the first vacuum pumps arranged between the two adjacent process cavities.
According to the PVD coating equipment provided by the invention, the front end of the first process cavity is provided with a front vacuum chamber, the rear end of the third process cavity is provided with a rear vacuum chamber, the front end of the front vacuum chamber is provided with an inlet chamber, the rear end of the rear vacuum chamber is provided with an outlet chamber, the working air pressure of the inlet chamber is greater than that of the front vacuum chamber, and the working air pressure of the outlet chamber is greater than that of the rear vacuum chamber.
According to the PVD coating equipment provided by the invention, the front vacuum chamber and the rear vacuum chamber respectively comprise multi-stage chambers, and adjacent two stages of chambers are separated by an isolation door.
According to the PVD coating equipment provided by the invention, the front vacuum chamber is provided with a heating module and a cold trap.
According to the PVD coating equipment provided by the invention, the first process chamber, the second process chamber and the third process chamber are respectively provided with a heating module and a cold trap.
According to the invention, the PVD coating equipment also comprises:
the first process cavity and the second process cavity are isolated by the vacuum isolation cavity, and the second process cavity and the third process cavity are isolated by the vacuum isolation cavity.
According to the invention, the PVD coating equipment also comprises: a vacuum isolation chamber;
the first process cavity and the second process cavity are isolated by the vacuum isolation cavity, and the second process cavity and the third process cavity are positioned in the same process chamber; or the first process cavity and the third process cavity are positioned in the same process chamber, and the second process cavity and the third process cavity are isolated by the vacuum isolation cavity.
The invention also provides a film coating method of the heterojunction battery, which comprises the following steps:
placing the substrate deposited with the amorphous silicon in a first process chamber of target PVD coating equipment, and depositing a TCO layer on the surface of the amorphous silicon;
depositing a metal seed layer on the surface of the TCO layer in a second process cavity of the target PVD coating equipment;
and depositing a mask on the surface of the metal seed layer in a third process cavity of the target PVD coating equipment.
According to the film coating method of the heterojunction cell provided by the invention, before the TCO layer is deposited on the surface of the amorphous silicon, the method further comprises the following steps:
and sequentially depositing a passivation layer and a transmission layer on the surface of the substrate in a PECVD (plasma enhanced chemical vapor deposition) cavity of the target PVD coating equipment.
According to the film coating method of the heterojunction cell, vacuum isolation cavities are arranged at least one of the first process cavity and the second process cavity and the third process cavity;
and the material to be processed is conveyed from the previous process cavity to the next process cavity through the vacuum isolation cavity.
According to the film coating method of the heterojunction battery, the first process cavity, the second process cavity and the third process cavity are positioned in the same process chamber, and a first vacuum pump used for keeping the atmosphere of each process cavity is arranged between the adjacent process cavities;
the sputtering cathodes in the first process chamber, the second process chamber and the third process chamber work in sequence, and each first vacuum pump is kept on.
According to the PVD coating equipment provided by the invention, three process chambers are integrated, and the TCO coating layer, the metal seed coating layer and the mask coating layer are combined into an integrated process, so that the high integration of the manufacturing links is realized, the production processes are reduced, the utilization rate of the equipment is improved to the maximum extent, and the productivity can be effectively released.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a PVD coating apparatus provided in the invention;
FIG. 2 is a second schematic structural view of a PVD coating apparatus provided in the invention;
FIG. 3 is a third schematic structural diagram of a PVD coating apparatus provided in the invention;
FIG. 4 is a fourth schematic structural view of a PVD coating apparatus provided in the invention;
fig. 5 is a schematic flow chart of a coating method of a heterojunction battery provided by the invention.
Reference numerals:
an inlet chamber 110, an inlet buffer chamber 120, an inlet transfer chamber 130;
a process chamber 200, a first process chamber 210, a first sputtering cathode 211, a second process chamber 220, a second sputtering cathode 221, a third process chamber 230, a third sputtering cathode 231;
an outlet transfer chamber 310, an outlet buffer chamber 320, an outlet chamber 330;
a first vacuum pump 410, a heating module 420, a cold trap 430;
a loading chamber 510, a heating chamber 520, a vacuum isolation chamber 530, and an unloading chamber 540.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
The PVD coating apparatus of the present invention is described below with reference to FIGS. 1 to 4.
As shown in fig. 1, a PVD coating apparatus according to an embodiment of the present invention includes: a first process chamber 210, a second process chamber 220, a third process chamber 230, a first vacuum pump 410, and a transfer mechanism (not shown).
The first process chamber 210 is provided with a first sputtering cathode 211, the first sputtering cathode 211 being used for loading a TCO target.
The substrate deposited with the amorphous silicon is placed in the first process chamber 210 of the PVD coating apparatus, and a TCO layer is deposited on the surface of the amorphous silicon.
The type of TCO target loaded on the first sputtering cathode 211 is determined according to the TCO layer to be obtained finally, for example, the TCO target may be an ITO (indium tin oxide) target, a TNO (TIO2: Nb) target, a CdO target, a CTO (Cd2SnO4) target, or the like.
As shown in fig. 1, two first sputtering cathodes 211 may be disposed in the first process chamber 210, and the two first sputtering cathodes 211 are disposed at the top and bottom of the first process chamber 210, respectively. The first sputtering cathode 211 at the top forms an upper cathode, and the TCO target at the upper part is arranged downwards and is used for plating a TCO layer on the amorphous silicon on the upper surface of the substrate; the first sputtering cathode 211 at the bottom forms a lower cathode, and the TCO target at the lower surface of the substrate is disposed upward for plating the amorphous silicon with a TCO layer.
As shown in fig. 1, the two first sputtering cathodes 211 in the first process chamber 210 are arranged in a staggered manner along the horizontal direction, so that two relatively independent atmospheres corresponding to the two first sputtering cathodes 211 are formed in the first process chamber 210.
The substrate with the amorphous silicon deposited thereon may be sequentially deposited with TCO layers on two sides in the first process chamber 210, as shown in fig. 1, the material to be processed (the substrate with the amorphous silicon deposited thereon) is transported from left to right according to an arrow sequence, the TCO layer on the upper surface of the material to be processed is deposited under the first sputtering cathode 211 on the left side, and the TCO layer on the lower surface of the material to be processed is deposited over the first sputtering cathode 211 on the right side.
Of course, the order of the upper and lower cathodes may be reversed. For example, the first sputtering cathode 211 located below is disposed on the left side of the first sputtering cathode 211 located above, so that during processing, the TCO layer on the lower surface is deposited first, and then the TCO layer on the upper surface is deposited.
The second process chamber 220 is provided with a second sputtering cathode 221, and the second sputtering cathode 221 is used for loading the metal seed target.
After depositing the TCO layer on the material to be processed in the first process chamber 210, the material is transported to the second process chamber 220 for depositing the metal seed layer.
In the second process chamber 220 of the target PVD coating apparatus, a metal seed layer is deposited on the surface of the TCO layer of the material to be processed.
The type of the metal seed target material loaded on the second sputtering cathode 221 is determined according to the metal seed layer to be obtained finally, for example, the metal seed layer may be at least one of Cu, Sn, Ni, In, Ti, W, Cr, Co, Mo, and Al, and the metal seed target material may be correspondingly disposed.
As shown in fig. 1, two second sputtering cathodes 221 may be disposed in the second process chamber 220, and the two second sputtering cathodes 221 are disposed at the top and bottom of the second process chamber 220, respectively. The second sputtering cathode 221 at the top forms an upper cathode, and the metal seed target material at the upper part is arranged downwards and is used for plating a metal seed layer on the TCO layer on the upper surface; the second sputtering cathode 221 at the bottom forms a lower cathode, where the metal seed target material is disposed upward for plating the TCO layer on the lower surface with a metal seed layer.
As shown in fig. 1, the two second sputtering cathodes 221 in the second process chamber 220 are arranged in a staggered manner along the horizontal direction, so that two relatively independent atmospheres corresponding to the two second sputtering cathodes 221 are formed in the second process chamber 220.
The material to be processed may be sequentially deposited with metal seed layers on both sides in the second process chamber 220, as shown in fig. 1, the material to be processed is transported from left to right in an arrow sequence, the material to be processed is firstly deposited with the metal seed layer on the upper surface under the left second sputtering cathode 221, and then deposited with the metal seed layer on the lower surface over the right second sputtering cathode 221.
Of course, the order of the upper and lower cathodes can be reversed. For example, the second sputtering cathode 221 located below is disposed at the left side of the second sputtering cathode 221 located above, so that during processing, the metal seed layer on the lower surface can be deposited first, and then the metal seed layer on the upper surface can be deposited.
The metal seed layer may also be a multilayer structure, for example, the metal seed layer is a Ti + Cu composite layer, and correspondingly, two pairs of second sputtering cathodes 221 are disposed in the second process chamber 220, one pair of second sputtering cathodes 221 are loaded with Ti targets, one pair of second sputtering cathodes 221 are loaded with Cu targets, each pair of second sputtering cathodes 221 are staggered in the horizontal direction, four second sputtering cathodes 221 are sequentially arranged in the horizontal direction, the first two are loaded with Ti targets, and the last two are loaded with Cu targets.
The third process chamber 230 is provided with a third sputtering cathode 231 and the second sputtering cathode 221 is used for loading the mask target.
After depositing a metal seed layer on the material to be processed in the second process chamber 220, the material is transported to the third process chamber 230 for depositing a mask.
In the third process chamber 230 of the target PVD coating apparatus, a mask is deposited on the surface of the metal seed layer of the material to be processed.
The type of the mask target loaded on the third sputtering cathode 231 is determined according to the mask to be obtained finally, for example, the mask target may be a SiNx target, a SiOx target, or a SiC target, and of course, the mask required for preparation may also be prepared by introducing different process gases containing a nitrogen source, an oxygen source, or a carbon source into a pure silicon target.
As shown in fig. 1, two third sputtering cathodes 231 may be disposed in the third process chamber 230, and the two third sputtering cathodes 231 are disposed at the top and bottom of the third process chamber 230, respectively. The third sputtering cathode 231 at the top forms an upper cathode, and the mask target material at the upper part is arranged downwards and is used for plating a mask on the metal seed layer on the upper surface of the substrate; the bottom third sputtering cathode 231 forms the lower cathode where the mask target is placed upward for masking the metal seed layer on the lower surface of the substrate.
As shown in fig. 1, the two third sputtering cathodes 231 in the third process chamber 230 are arranged in a staggered manner along the horizontal direction, so that two relatively independent atmospheres corresponding to the two third sputtering cathodes 231 are formed in the third process chamber 230.
The material to be processed may be sequentially deposited with masks on two sides in the third process chamber 230, as shown in fig. 1, the material to be processed is transported from left to right according to the arrow sequence, the material to be processed is firstly deposited with a mask on the upper surface under the left third sputtering cathode 231, and then deposited with a mask on the lower surface over the right third sputtering cathode 231.
Of course, the order of the upper and lower cathodes can be reversed. For example, the third sputtering cathode 231 located below is disposed on the left side of the third sputtering cathode 231 located above, so that during processing, a mask on the lower surface is deposited first, and then a mask on the upper surface is deposited.
A first vacuum pump 410 is disposed between the first process chamber 210 and the second process chamber 220, and between the second process chamber 220 and the third process chamber 230, and the first vacuum pump 410 is used for maintaining the atmosphere of each process chamber.
The first vacuum pump 410 may be a molecular pump or a diffusion pump.
As shown in fig. 1, the first vacuum pump 410 may be disposed on the walls of the first process chamber 210, the second process chamber 220, and the third process chamber 230, where a is a top wall or a side wall of the first process chamber 210, B is a top wall or a side wall at a junction of the first process chamber 210 and the second process chamber 220, C is a top wall or a side wall of the second process chamber 220, D is a top wall or a side wall at a junction of the second process chamber 220 and the third process chamber 230, and E is a top wall or a side wall of the first process chamber 210. A. B, C, D and E may each be provided with a first vacuum pump 410.
Alternatively, as shown in fig. 4, a vacuum isolation chamber 530 is disposed between the first process chamber 210 and the second process chamber 220, the vacuum isolation chamber 530 is disposed with the first vacuum pump 410, a vacuum isolation chamber 530 is disposed between the second process chamber 220 and the third process chamber 230, and the vacuum isolation chamber 530 is disposed with the first vacuum pump 410.
Therefore, a plurality of target combinations are arranged in one PVD coating device, and the separation among the film deposition procedures is realized by vacuumizing, so that the cross contamination of process gases among the procedures is avoided, and the dynamic balance of the gases in a process chamber is maintained.
The transfer structure is used for loading and driving the material to be processed to move in the first process chamber 210, the second process chamber 220 and the third process chamber 230.
In the working process, the material to be processed sequentially enters the first process chamber 210, the second process chamber 220 and the third process chamber 230, the TCO layer is plated in the first process chamber 210, the metal seed layer is plated in the second process chamber 220, and the mask is plated in the third process chamber 230.
The PVD coating equipment disclosed by the embodiment of the invention is integrated with three process chambers, and the TCO coating layer, the metal seed coating layer and the mask coating layer are combined into an integrated process, so that the high integration of the manufacturing links is realized, the production processes are reduced, the utilization rate of the equipment is improved to the maximum extent, and the productivity can be effectively released.
In some embodiments, the PVD coating apparatus may further comprise: the PECVD cavity is arranged at the front end of the first process cavity 210, and because the amorphous silicon deposition process contains toxic process gas, the PVD cavity wall is prevented from being corroded by the toxic gas, and the PECVD cavity is preferably arranged between the multi-stage chambers, so that the PECVD cavity and the PVD cavity are prevented from being directly connected, for example, an isolation chamber can be arranged between the PECVD cavity and the first process cavity 210.
In this embodiment, the material fed into the PVD coating apparatus may be a substrate, the substrate may be a silicon wafer that is pretreated first, the pretreatment may include cleaning and texturing, and the pretreatment may be performed on both sides of the silicon wafer.
The PECVD cavity is used for depositing amorphous silicon, the amorphous silicon can comprise a passivation layer and a transmission layer, the passivation layer is formed between the transmission layer and a substrate, namely the passivation layer is formed on the working surface of the substrate firstly, the transmission layer is formed on the surface, away from the substrate, of the passivation layer, the substrate is in a sheet shape, and the working surface of the substrate can be a top surface and a bottom surface of the substrate, which are oppositely arranged in the thickness direction.
The passivation layer is positioned between the substrate and the transmission layer and used for passivating the dangling bonds on the surface of the substrate, and the passivation layer can be intrinsic amorphous silicon under the condition that the substrate is a silicon substrate.
The transmission layer is of a different conductivity type than the silicon substrate such that the transmission layer forms a heterojunction with the substrate as an emitter of the heterojunction cell. For example, in the case of an N-type silicon substrate, the transmission layers on both sides of the substrate can be N-type amorphous silicon and P-type amorphous silicon, respectively.
During processing, a passivation layer is deposited in a process cavity of PECVD equipment, and then a transmission layer is deposited. In some embodiments, after depositing the passivation layer, the impurity gas may be removed prior to depositing the transmission layer.
The passivation layer and the transmission layer are respectively formed on two sides of the substrate, namely the passivation layer is formed on the two sides of the substrate, and the transmission layer is formed on the surfaces of the two passivation layers. Firstly, cleaning and texturing the two sides of an N-type silicon wafer, then depositing amorphous silicon serving as a passivation layer by PECVD equipment, and then depositing N-type amorphous silicon and P-type amorphous silicon serving as transmission layers on the two sides respectively.
The PVD coating equipment according to the embodiment of the invention is described in detail in three different directions according to the communication condition of the three process chambers.
First, three process chambers are in the same communicating process chamber 200.
As shown in fig. 1-3, the first process chamber 210, the second process chamber 220, and the third process chamber 230 are located within the same process chamber 200.
By arranging the three process chambers in the same process chamber 200, the volume of the PVD coating equipment can be reduced, and the difficulty of the transmission structure for transmitting the material to be processed among the three process chambers is reduced.
In this embodiment, the atmosphere independence of the process chambers is achieved by a first vacuum pump 410 disposed on the wall of the process chamber 200, as shown in FIG. 1, where A is the top wall or the bottom wall of the first process chamber 210, B is the top wall or the bottom wall at the junction of the first process chamber 210 and the second process chamber 220, C is the top wall or the bottom wall of the second process chamber 220, D is the top wall or the bottom wall at the junction of the second process chamber 220 and the third process chamber 230, and E is the top wall or the bottom wall of the first process chamber 210. A. B, C, D and E may each be provided with a first vacuum pump 410.
In some embodiments, as shown in fig. 1 and 3, each of the first sputtering cathode 211, the second sputtering cathode 221, and the third sputtering cathode 231 includes two sputtering cathodes oppositely disposed in the up-down direction, the first vacuum pumps 410 are disposed in the middle portions of the first process chamber 210, the second process chamber 220, and the third process chamber 230, and the number of the first vacuum pumps 410 disposed in the middle portion of each process chamber is smaller than the number of the first vacuum pumps 410 disposed between two adjacent process chambers.
As shown in fig. 1, a is a middle portion of the first process chamber 210, C is a middle portion of the second process chamber 220, E is a middle portion of the first process chamber 210, B is a position between the first process chamber 210 and the second process chamber 220, D is a position between the second process chamber 220 and the third process chamber 230, and A, C and E each have a smaller number of first vacuum pumps 410 than B and D each have.
It is understood that the first vacuum pumps 410 arranged at A, C and E are used for forming independent atmosphere between the upper cathode and the lower cathode with the same target, the process gases at two adjacent positions are basically the same, and a small amount of the first vacuum pumps 410 are arranged; A. the first vacuum pumps 410 arranged at positions C and E are used for forming independent atmosphere between cathodes with different targets, process gases at two adjacent positions are different, and more first vacuum pumps 410 are arranged to prevent pollution.
As shown in fig. 3, the first process chamber 210, the second process chamber 220, and the third process chamber 230 are each provided with a heating module 420 and a cold trap 430. The heating modules 420 are used to ensure a constant temperature processing environment, and the heating modules 420 are provided at the top and bottom of the first, second, and third process chambers 210, 220, and 230. The cold trap 430 is used to remove moisture, and the cold trap 430 is disposed under the lower heating module 420.
As shown in fig. 3, two first sputtering cathodes 211 (a lower cathode and an upper cathode) are respectively disposed in front of and behind the first process chamber 210, and a buffer module is disposed between the lower cathode and the upper cathode, and the buffer module includes a molecular pump, an upper and a lower heating devices, and a cold trap 430 at a lower portion; the buffer module between the first process chamber 210 and the second process chamber 220 is used for buffering coating and isolating sputtering atmosphere, comprises two arranged molecular pump groups for realizing dynamic balance of atmosphere and air pressure in the coating chamber, and is provided with heating devices at the upper part and the lower part, and a cold trap 430 at the lower part; two second sputtering cathodes 221 (a lower cathode and an upper cathode) are respectively arranged in front of and behind the second process chamber 220 and used for double-sided sputtering of the metal seed layer, a buffer module is arranged between the lower cathode and the upper cathode, and the buffer module comprises a molecular pump, an upper heating device, a lower heating device and a cold trap 430 at the lower part; the buffer module between the second process cavity 220 and the third process cavity 230 is used for buffering coating and isolating sputtering atmosphere, comprises two arranged molecular pump groups for realizing dynamic balance of atmosphere and air pressure in the coating cavity, and is provided with heating devices at the upper part and the lower part, and a cold trap 430 at the lower part; the third process chamber 230 is used for double-sided sputtering mask, and two third sputtering cathodes 231 (lower cathode and upper cathode) are respectively arranged in front and at the back, and a buffer module is arranged between the lower cathode and the upper cathode, and the buffer module comprises a molecular pump, an upper heating device, a lower heating device and a cold trap 430 at the lower part.
In some embodiments, the front end of the first process chamber 210 is provided with a front vacuum chamber, the rear end of the third process chamber 230 is provided with a rear vacuum chamber, the front end of the front vacuum chamber is provided with an inlet chamber 110, the rear end of the rear vacuum chamber is provided with an outlet chamber 330, the working pressure of the inlet chamber 110 is greater than that of the front vacuum chamber, and the working pressure of the outlet chamber 330 is greater than that of the rear vacuum chamber.
The inlet chamber 110 is an inlet for the material to be processed, and is a transition module between atmospheric air and vacuum, and the inlet chamber 110 may be maintained at a pressure of 5 pa to 20 pa, such as 10 pa.
The front vacuum chamber is a transition module of low vacuum and high vacuum, a heating module 420 and a cold trap 430 can be further arranged in the front vacuum chamber, wherein the heating module 420 is arranged at the top and the bottom of the front vacuum chamber. The cold trap 430 is used to remove moisture, and the cold trap 430 is disposed under the lower heating module 420. The pre-vacuum chamber is used for balancing atmosphere and isolating atmosphere.
The front vacuum chamber may comprise a plurality of stages, and adjacent two stages are separated by an isolation door. As shown in fig. 2, the front vacuum chamber may include an inlet buffer chamber 120 and an inlet transfer chamber 130, the inlet buffer chamber 120 being provided at the top and bottom thereof with heating modules 420, and a cold trap 430 disposed below the lower heating modules 420; the inlet transfer chamber 130 is provided with heating modules 420 at the top and bottom thereof, and a cold trap 430 is disposed below the lower heating modules 420.
The post-vacuum chamber is a transition module of low vacuum and high vacuum, and because the film is coated out of the chamber, the water vapor is less, and the heating module 420 and the cold trap 430 are not needed for saving the cost.
The post-vacuum chamber can comprise a multi-stage chamber, and adjacent two stages of chambers are separated by an isolation door. As shown in fig. 2, the back vacuum chamber may include an outlet transfer chamber 310 and an outlet buffer chamber 320.
The outlet chamber 330 is used for discharging the coated silicon wafer, and is a transition module between vacuum and atmosphere. The outlet chamber 330 may be maintained at a pressure of 5 pa to 20 pa, such as 10 pa.
And secondly, each process cavity is isolated.
As shown in fig. 4, in this embodiment, the PVD coating apparatus may further include: the vacuum isolation chamber 530, the vacuum isolation chamber 530 is provided with a first vacuum pump 410, the first process chamber 210 and the second process chamber 220 are isolated by the vacuum isolation chamber 530, and the second process chamber 220 and the third process chamber 230 are isolated by the vacuum isolation chamber 530.
In the embodiment mode, the PVD coating process is divided into a plurality of independent chambers, reaction gases are prevented from being polluted by each other through the isolation chambers, and different technological requirements of different films are met.
A heating cavity 520 is arranged at the front end of the first process chamber 210, a heating module 420 and a cold trap 430 can be arranged in the heating cavity 520, and a loading cavity 510 is arranged at the front end of the heating cavity 520; the back end of the first process chamber 210 is provided with an unload chamber 540.
In the actual processing process, the silicon wafer after depositing the amorphous silicon is mounted on the transmission mechanism, enters the heating cavity 520 through the loading cavity 510 for heating, and enters the first process cavity 210, and the first process cavity 210 contains TCO target materials such as ITO palladium and the like; after the TCO film is plated, the TCO film enters a vacuum isolation cavity 530; enters the second process chamber 220 through the isolation chamber, and deposits a metal seed layer, such as one or a combination of more of Cu, Sn, Ni, In, Ti, W, Cr, Co, Mo, Al, etc.; then enters the third process chamber 230 through the vacuum isolation chamber 530, and one or a combination of SiNx, SiOx, SiC and the like is deposited as a mask; finally, the silicon wafer enters an unloading cavity 540 through a vacuum isolation cavity 530 and enters a grid line pattern etching process.
And thirdly, the two process chambers are positioned in the same communicated process chamber, and the other process chamber is independently arranged.
In this case, there are two embodiments:
(1) the first process chamber 210 and the second process chamber 220 are isolated by a vacuum isolation chamber 530, and the second process chamber 220 and the third process chamber 230 are located in the same process chamber;
(2) the first process chamber 210 and the third process chamber 230 are located in the same process chamber, and the second process chamber 220 and the third process chamber 230 are isolated from each other by a vacuum isolation chamber 530.
The above embodiments can be combined with the embodiment that three chambers are located in the same process chamber 200 and the embodiment that three chambers are independent, and are selected according to the interference between the adjacent processes during the actual coating.
The following describes a film coating method for a heterojunction battery provided by the invention, and the film coating method for the heterojunction battery described below and the PVD film coating apparatus described above can be referred to correspondingly.
As shown in fig. 5, the coating method of the heterojunction cell includes steps 610 to 630.
The target PVD coating equipment used in the coating method of the heterojunction battery is the PVD coating equipment of any of the above embodiments.
in the step, the processed TCO layer has good light transmittance and strong transverse conductivity, is used for assisting in carrying out transmission of current carriers, and is beneficial to better collecting the current carriers so as to assist in current transmission and reduce electric energy loss caused by resistance in the heterojunction battery.
The TCO layer can be a single-layer film structure or a composite structure of various films.
in this step, the material to be processed is transported from the first process chamber 210 to the second process chamber 220, and the surface of the TCO layer is completely covered with a metal seed layer, which is equivalent to plating a film on the surface of the TCO layer, and the metal seed layer is used as a base for electrode growth.
The metal seed layer may be deposited on both sides of the material to be processed obtained in the step(s), i.e., the metal seed layer may be deposited on both surfaces of the TCO layers on both sides.
The metal seed layer is at least one of Cu, Sn, Ni, In, Ti, W, Cr, Co, Mo and Al, and the thickness of the metal seed layer is nano-nano.
The metal seed layer may be a single layer structure or a multi-layer structure,
for example, the metal seed layer may be a single layer of Cu, or a composite layer of Ti + Cu.
Step 630, depositing a mask on the surface of the metal seed layer in the third process chamber 230 of the target PVD coating apparatus.
In this step, the material to be processed is transported from the second process chamber 220 to the third process chamber 230, a mask is plated in the third process chamber 230 by a PVD method, the mask is a silicon-containing inorganic compound, the silicon-containing inorganic compound has high hardness, good compactness and few pinholes, and does not react with other acid or base except for the reaction with high-concentration HF, and in the electroplating process, the mask can be realized with a relatively low thickness, and the material has better corrosion resistance compared with an organic film.
In some embodiments, the mask is one or more of SiNx, SiOx, SiC. For example, the mask is SiNx, or the mask is a mixture of SiNx + SiOx. The SiNx has high stability, high hardness, good compactness and few pinholes, and can realize stable isolation under extremely small thickness.
In some embodiments, the thickness of the mask is: 5 nm-30 microns. For example, the thickness of the mask is: 10 nm or 15 nm or 20 nm. That is, the mask is formed as long as film formation is ensured.
The material to be processed after the coating can be subjected to subsequent processes, including: removing part of the mask to form an electrode grid line pattern; forming an electrode at the electrode grid line pattern; removing the mask; and removing the metal seed layer outside the electrode grid line pattern.
According to the film coating method of the table heterojunction battery, the integrated working procedures of TCO layer plating, metal seed layer plating and mask film plating are realized on the same equipment, the high integration of the manufacturing link is realized, the production working procedures are reduced, the utilization rate of the equipment is improved to the maximum extent, and the productivity can be effectively released.
In some embodiments, before depositing the TCO layer on the surface of the amorphous silicon, the method further comprises: and sequentially depositing amorphous silicon on the surface of the substrate in a PECVD (plasma enhanced chemical vapor deposition) cavity of the target PVD coating equipment.
The target PVD coating apparatus may further include: a PECVD chamber provided at the front end of the first process chamber 210.
In this embodiment, the material fed into the PVD coating apparatus may be a substrate, the substrate may be a silicon wafer that is pretreated first, the pretreatment may include cleaning and texturing, and the pretreatment may be performed on both sides of the silicon wafer.
The PECVD cavity is used for depositing amorphous silicon, the amorphous silicon can comprise a passivation layer and a transmission layer, the passivation layer is formed between the transmission layer and a substrate, namely the passivation layer is formed on the working surface of the substrate firstly, the transmission layer is formed on the surface, away from the substrate, of the passivation layer, the substrate is in a sheet shape, and the working surface of the substrate can be a top surface and a bottom surface of the substrate, which are oppositely arranged in the thickness direction.
The passivation layer is positioned between the substrate and the transmission layer and used for passivating the dangling bonds on the surface of the substrate, and the passivation layer can be intrinsic amorphous silicon under the condition that the substrate is a silicon substrate.
The transmission layer is of a different conductivity type than the silicon substrate so that the transmission layer forms a heterojunction with the substrate as an emitter of the heterojunction cell. For example, in the case of an N-type silicon substrate, the transmission layers on both sides of the substrate can be N-type amorphous silicon and P-type amorphous silicon, respectively.
During processing, a passivation layer is deposited in a process cavity of PECVD equipment, and then a transmission layer is deposited. In some embodiments, after depositing the passivation layer, the impurity gas may be removed prior to depositing the transmission layer.
The passivation layer and the transmission layer are respectively formed on two sides of the substrate, namely the passivation layer is formed on the two sides of the substrate, and the transmission layer is formed on the surfaces of the two passivation layers. Firstly, cleaning and texturing two sides of an N-type silicon wafer, then depositing amorphous silicon as a passivation layer by PECVD equipment, and then respectively depositing N-type amorphous silicon and P-type amorphous silicon as transmission layers on the two sides.
In some embodiments, as shown in fig. 1 to fig. 3, the first process chamber 210, the second process chamber 220 and the third process chamber 230 of the target PVD coating apparatus are located in the same process chamber 200, and a first vacuum pump 410 for maintaining the atmosphere of each process chamber is disposed between adjacent process chambers; the sputtering cathodes in the first process chamber 210, the second process chamber 220, and the third process chamber 230 are sequentially operated, and each of the first vacuum pumps 410 is kept on.
In this embodiment, when the material to be processed is fed into the first process chamber 210, the first sputtering cathode 211 is turned on to plate the TCO layer, then the transport mechanism feeds the material to be processed into the second process chamber 220, the second sputtering cathode 221 is turned on to plate the metal seed layer, then the transport mechanism feeds the material to be processed into the third process chamber 230, and the third sputtering cathode 231 is turned on to plate the mask.
In some embodiments, as shown in fig. 4, a vacuum isolation chamber 530 is disposed between the first process chamber 210 and the second process chamber 220 of the target PVD coating apparatus, and a vacuum isolation chamber 530 is disposed between the second process chamber 220 and the third process chamber 230; during processing, material to be processed is transferred from a previous process chamber to a subsequent process chamber through the vacuum isolation chamber 530. This ensures that there is no interference between adjacent chambers.
After depositing the TCO layer on the surface of the amorphous silicon and before depositing the metal seed layer on the surface of the TCO layer, the method further comprises: the material to be processed with the TCO layer deposited is conveyed into the vacuum isolation chamber 530 between the first process chamber 210 and the second process chamber 220, and then conveyed into the second process chamber 220 from the vacuum isolation chamber 530; after depositing the metal seed layer on the surface of the TCO layer and before depositing the mask on the surface of the metal seed layer, the method further comprises: the material to be processed, on which the metal seed layer is deposited, is transferred into the vacuum isolation chamber 530 between the second process chamber 220 and the third process chamber 230, and then is transferred from the vacuum isolation chamber 530 into the third process chamber 230.
In some embodiments, the first process chamber 210 and the second process chamber 220 are isolated by a vacuum isolation chamber 530, and the second process chamber 220 and the third process chamber 230 are located in the same process chamber; or the first process chamber 210 and the third process chamber 230 are located in the same process chamber, and the second process chamber 220 and the third process chamber 230 are isolated by the vacuum isolation chamber 530.
The above embodiment can be combined with an embodiment in which three chambers are located in the same process chamber and an embodiment in which three chambers are independent during processing, and is selected according to the interference between adjacent processes during actual coating.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (14)
1. A PVD coating apparatus, comprising:
the first process chamber is provided with a first sputtering cathode, and the first sputtering cathode is used for loading TCO target materials;
the second process cavity is provided with a second sputtering cathode, and the second sputtering cathode is used for loading a metal seed target;
the third process cavity is provided with a third sputtering cathode, and the second sputtering cathode is used for loading a mask target material;
the first vacuum pump is arranged between the first process cavity and the second process cavity and between the second process cavity and the third process cavity and is used for maintaining the atmosphere of each process cavity;
the conveying mechanism is used for loading materials to be processed and driving the materials to be processed to move in the first process cavity, the second process cavity and the third process cavity.
2. The PVD coating apparatus of claim 1, further comprising:
and the PECVD cavity is arranged at the front end of the first process cavity.
3. The PVD coating apparatus of claim 1 or 2, wherein the first process chamber, the second process chamber and the third process chamber are located in a same process chamber.
4. The PVD coating apparatus according to claim 3, wherein the first sputtering cathode, the second sputtering cathode and the third sputtering cathode each include two oppositely arranged in an up-down direction, the first vacuum pumps are respectively arranged in the middle of the first process chamber, the second process chamber and the third process chamber, and the number of the first vacuum pumps arranged in the middle of each process chamber is smaller than that of the first vacuum pumps arranged between two adjacent process chambers.
5. A PVD coating apparatus according to claim 4, wherein a front end of the first process chamber is provided with a front vacuum chamber, a rear end of the third process chamber is provided with a rear vacuum chamber, a front end of the front vacuum chamber is provided with an inlet chamber, a rear end of the rear vacuum chamber is provided with an outlet chamber, an operating pressure of the inlet chamber is higher than that of the front vacuum chamber, and an operating pressure of the outlet chamber is higher than that of the rear vacuum chamber.
6. The PVD coating apparatus of claim 5, wherein the pre-vacuum chamber and the post-vacuum chamber each comprise a multi-stage chamber, and adjacent two stages of chambers are separated by an isolation door.
7. The PVD coating apparatus of claim 5, wherein the forevacuum chamber is provided with a heating module and a cold trap.
8. The PVD coating apparatus of claim 3, wherein the first process chamber, the second process chamber and the third process chamber are each provided with a heating module and a cold trap.
9. A PVD coating apparatus according to claim 1 or 2, further comprising:
the first process cavity and the second process cavity are isolated by the vacuum isolation cavity, and the second process cavity and the third process cavity are isolated by the vacuum isolation cavity.
10. The PVD coating apparatus of claim 1 or 2, further comprising: a vacuum isolation chamber;
the first process cavity and the second process cavity are isolated by the vacuum isolation cavity, and the second process cavity and the third process cavity are positioned in the same process chamber; or the first process cavity and the third process cavity are positioned in the same process chamber, and the second process cavity and the third process cavity are isolated by the vacuum isolation cavity.
11. A coating method of a heterojunction battery is characterized by comprising the following steps:
placing the substrate deposited with the amorphous silicon in a first process chamber of target PVD (physical vapor deposition) coating equipment, and depositing a TCO (transparent conductive oxide) layer on the surface of the amorphous silicon;
depositing a metal seed layer on the surface of the TCO layer in a second process cavity of the target PVD coating equipment;
and depositing a mask on the surface of the metal seed layer in a third process cavity of the target PVD coating equipment.
12. The plating method for a heterojunction cell as claimed in claim 11, wherein before depositing the TCO layer on the surface of the amorphous silicon, the method further comprises:
and sequentially depositing a passivation layer and a transmission layer on the surface of the substrate in a PECVD (plasma enhanced chemical vapor deposition) cavity of the target PVD coating equipment.
13. The plating method for a heterojunction cell according to claim 11 or 12,
vacuum isolation cavities are arranged at least one of the first process cavity and the second process cavity and the third process cavity;
and the material to be processed is conveyed from the previous process cavity to the next process cavity through the vacuum isolation cavity.
14. The method for coating a heterojunction battery according to claim 11 or 12, wherein the first process chamber, the second process chamber and the third process chamber are located in the same process chamber, and a first vacuum pump for maintaining the atmosphere of each process chamber is arranged between the adjacent process chambers;
the sputtering cathodes in the first process chamber, the second process chamber and the third process chamber work in sequence, and each first vacuum pump is kept on.
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| CN202210731244.1A CN115101446A (en) | 2022-06-24 | 2022-06-24 | PVD (physical vapor deposition) coating equipment and coating method of heterojunction battery |
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| CN202210731244.1A CN115101446A (en) | 2022-06-24 | 2022-06-24 | PVD (physical vapor deposition) coating equipment and coating method of heterojunction battery |
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