CN115099396A - Full weight mapping method and device based on memristor array - Google Patents
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Abstract
The application discloses full weight mapping method and device based on memristor array, wherein the method comprises the following steps: adding preset parameters to all parameters of the target weight matrix at the same time, and generating a shifted weight matrix; storing the shifted weight matrix into a memristor array in a conductance mode, and acquiring a product result of the shifted weight matrix and input information by using the memristor array; and on the basis of the product result, subtracting a preset constant from each row respectively to obtain a product result of the target weight matrix and the input information. Therefore, the problems that in the related art, due to the fact that a differential mapping scheme is used, not only is the overhead of a hardware circuit large, but also the variable resistance range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, not only are the electrical state waste and the hardware efficiency low, but also the weight mapping requirements cannot be effectively met, and the flexibility and the efficiency are low are solved.
Description
Technical Field
The application relates to the technical field of image processing, in particular to a full weight mapping method and device based on a memristor array.
Background
In the related art, common ways of weight mapping include a differential mapping scheme and a symmetric mapping scheme. According to the differential mapping scheme, one piece of weight unit information can be split into two weight values larger than 0, and the two weight values are respectively deployed into two adjacent memristor devices; the symmetric mapping scheme may map the weight units distributed in the (-1, 1) interval to a (0, 1) range.
However, in the related art, a common weight mapping manner cannot effectively utilize the resistance change range of the device for a weight matrix with an asymmetric distribution interval, so that the problems of electrical conductivity waste and low hardware efficiency are solved, the weight mapping requirements cannot be effectively met, the flexibility and the high efficiency are low, and a solution is urgently needed.
Disclosure of Invention
The application provides a full weight mapping method and device based on a memristor array, and aims to solve the problems that in the related art, due to the fact that a differential mapping scheme is used, the overhead of a hardware circuit is large, in addition, the resistance change range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, the electrical conductivity waste and the hardware efficiency are low, in addition, the weight mapping requirements cannot be effectively met, and the flexibility and the high efficiency are low.
The embodiment of the first aspect of the application provides a full weight mapping method based on a memristor array, which includes the following steps: adding preset parameters to all parameters of the target weight matrix at the same time, and generating a shifted weight matrix; storing the weight matrix after the deviation into a memristor array in a conductance mode, and acquiring a product result of the weight matrix after the deviation and input information by using the memristor array; and based on the product result, subtracting a preset constant from each row respectively to obtain the product result of the target weight matrix and the input information.
Optionally, in an embodiment of the application, before adding all the parameters of the target weight matrix to the preset parameter at the same time, the method further includes: determining the preset parameters based on the mapping relation between the elements of the shifted weight matrix and the memristor array, so that the parameter range of the target weight matrix is translated to the mapping range of the memristor array.
Optionally, in an embodiment of the present application, before obtaining a product result of the shifted weight matrix and input information by using the memristor array, the method further includes: acquiring the input information; the input information is encoded into a corresponding series of voltage pulses.
Optionally, in an embodiment of the present application, before subtracting the preset constant from each row, the method further includes: calculating a sum of all components of an input vector of the input information; and multiplying the sum by the preset parameter to obtain the preset constant.
Optionally, in an embodiment of the present application, the subtracting a preset constant from each row to obtain a product result of the target weight matrix and the input information includes: obtaining an output current based on the memristor array; and quantizing the output current ADC to obtain processing information, and subtracting the output information of the last row of the memristor array to obtain the product result.
The embodiment of the second aspect of the present application provides a full weight mapping apparatus based on a memristor array, including: the generating module is used for simultaneously adding preset parameters to all the parameters of the target weight matrix to generate a shifted weight matrix; the first obtaining module is used for storing the shifted weight matrix into a memristor array in a conductance mode and obtaining a product result of the shifted weight matrix and input information by using the memristor array; and the second acquisition module is used for subtracting a preset constant from each row respectively based on the product result to obtain the product result of the target weight matrix and the input information.
Optionally, in an embodiment of the present application, the method further includes: a determining module, configured to determine the preset parameter based on a mapping relationship between the element of the shifted weight matrix and the memristor array before adding the preset parameter to all parameters of the target weight matrix at the same time, so that a parameter range of the target weight matrix is translated to a mapping range of the memristor array.
Optionally, in an embodiment of the present application, the method further includes: a third obtaining module, configured to obtain the input information before obtaining a product result of the shifted weight matrix and the input information by using the memristor array; and the coding module is used for coding the input information into a corresponding series of voltage pulses.
Optionally, in an embodiment of the present application, the method further includes: a first calculating module, configured to calculate a sum of all components of an input vector of the input information before the preset constant is subtracted from each row, respectively; and the second calculation module is used for multiplying the sum by the preset parameter to obtain the preset constant.
Optionally, in an embodiment of the present application, the second obtaining module is further configured to obtain an output current based on the memristor array, obtain processing information by performing ADC quantization on the output current, and subtract the output information of the last row of the memristor array to obtain the product result.
An embodiment of a third aspect of the present application provides an electronic device, including: the memory, the processor and the computer program stored on the memory and capable of running on the processor, the processor executes the program to realize the memristor array-based full weight mapping method according to the embodiment.
A fourth aspect of the present application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the memristor array-based full weight mapping method according to the above embodiments.
According to the embodiment of the application, the shifted weight matrix can be generated and stored in the memristor array in a conductance mode, further, the product result of input information is obtained, the target weight matrix is obtained through calculation, weight compensation is achieved, for the weight matrix with the asymmetric distribution interval, the resistance change range of the device can be utilized to a greater extent, only a small number of additional memristor devices are used as the cost, and the flexibility and the efficiency of the realization of the storage and calculation integrated hardware are improved. Therefore, the problems that in the related art, due to the fact that a differential mapping scheme is used, not only is the overhead of a hardware circuit large, but also the resistance change range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, electric conductivity is wasted, hardware efficiency is low, weight mapping requirements cannot be effectively met, and flexibility and efficiency are low are solved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
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The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a full weight mapping method based on a memristor array provided according to an embodiment of the present application;
FIG. 2 is a technical schematic diagram of a full weight mapping method based on a memristor array according to one embodiment of the present application;
FIG. 3 is a hardware implementation of a memristor array-based full weight mapping approach according to one embodiment of the present application;
FIG. 4 is a flow diagram of a full weight mapping method based on memristor arrays, according to one embodiment of the present application;
FIG. 5 is a schematic structural diagram of a full weight mapping apparatus based on a memristor array according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The full weight mapping method and device based on the memristor array according to the embodiments of the present application are described below with reference to the accompanying drawings. Aiming at the problems that the overhead of a hardware circuit is large, the resistance change range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval due to the adoption of a differential mapping scheme in the related technology mentioned in the center of the background art, the problems of waste of electrical conductivity and low hardware efficiency exist, the weight mapping requirement cannot be effectively met, and the flexibility and the high efficiency are low, the application provides a full weight mapping method based on a memristor array, in the method, a shifted weight matrix can be generated and stored into the memristor array in a conductive form, so that the product result of input information is obtained, a target weight matrix is obtained through calculation, the weight compensation is realized, for the asymmetric weight matrix with the distribution interval, the resistance change range of the device can be utilized to a greater extent, and only a small amount of additional memristor is used as cost, the flexibility and the efficiency of the hardware implementation of the storage and calculation integration are increased. Therefore, the problems that in the related art, due to the fact that a differential mapping scheme is used, not only is the overhead of a hardware circuit large, but also the variable resistance range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, not only are the electrical state waste and the hardware efficiency low, but also the weight mapping requirements cannot be effectively met, and the flexibility and the efficiency are low are solved.
Specifically, fig. 1 is a schematic flowchart of a full weight mapping method based on a memristor array according to an embodiment of the present application.
As shown in fig. 1, the full weight mapping method based on the memristor array includes the following steps:
in step S101, preset parameters are added to all parameters of the target weight matrix at the same time, and a shifted weight matrix is generated.
In an actual execution process, all parameters of the target weight matrix can be added to preset parameters, and then the weight matrix after offset is generated, so that flexibility is improved.
It should be noted that the preset parameters can be set by those skilled in the art according to practical situations, and are not limited in detail herein.
Optionally, in an embodiment of the present application, before adding all the parameters of the target weight matrix to the preset parameter at the same time, the method further includes: and determining preset parameters based on the mapping relation between the elements of the shifted weight matrix and the memristor array, so that the parameter range of the target weight matrix is translated to the mapping range of the memristor array.
Specifically, as shown in fig. 2, the embodiment of the present application may assume a weight matrix W of a scale, and a parameter distribution range is (W) 1 ，W 2 ) Wherein W is 1 ≠-W 2 。
A preset parameter such as a constant a is added to all the parameters in the weight matrix W at the same time, so that the parameter range is translated into an interval (W) which can be mapped by the resistance change unit 1 +a，W 2 + a), the elements of the weight matrix W' after offset are mapped into the memristor array one by one, and one unit corresponds to one weight.
In step S102, the shifted weight matrix is stored in a conductance form into the memristor array, and a product result of the shifted weight matrix and the input information is obtained by using the memristor array.
It can be understood that the memristor-based storage and calculation integrated technology can realize great advantages in the aspect of hardware overhead on the basis of ensuring the algorithm effect in many neural network applications. According to the method and the device, the shifted weight matrix can be stored in the memristor array in a conductance mode, the product result of the shifted weight matrix and input information is obtained by using the memristor array, full weight mapping based on the memristor array is further achieved, for the weight matrix with the asymmetric distribution interval, the resistance change range of the device can be utilized to a greater extent, only a small number of additional memristor devices are used as a cost, and the flexibility and the efficiency of the implementation of the integrated hardware are improved.
Optionally, in an embodiment of the present application, before obtaining a product result of the shifted weight matrix and the input information by using the memristor array, the method further includes: acquiring input information; the input information is encoded into a corresponding series of voltage pulses.
In the practical implementation process, the weight parameter W of the neural network can be stored in the memristor array in a conductance form G, the image or voice information I subjected to encoding processing is encoded into a series of voltage pulses, the voltage pulses are applied to one end of the array, and the output current at the other end of the array is also the product result WI of the voltage vector and the conductance matrix.
Specifically, in the embodiment of the present application, the image or voice information after being encoded is the input information I, and the embodiment of the present application may encode the input information I into a series of voltage pulses [ V ] 1 ,V 2 ,V 3 ,V 4 ,V 5 ,V 6 ]。
In step S103, based on the multiplication result, a preset constant is subtracted from each row to obtain a multiplication result of the target weight matrix and the input information.
In actual implementation, as shown in fig. 3, where circles of different gray levels represent memristive cells of different electrical conductivity states, the memristive cells may be 1R, 1S1R, or 1T1R structures. In the forward reasoning process, W' I corresponds to the actual output of the 1 st row to the 5 th row of the memristor array in fig. 3, and a constant is subtracted from each row result, so that a product result of the original matrix W and the input information I can be obtained, and the calculation formula can be as follows:
W′＝W+aJ，
WI＝W′I-aJI，
where J is an all 1 matrix of size 5X 6. It should be noted that the preset constant is described in detail below.
Optionally, in an embodiment of the present application, before subtracting the preset constant from each row, the method further includes: calculating a sum of all components of an input vector of the input information; and multiplying the sum by a preset parameter to obtain a preset constant.
The calculation of the predetermined constant is described in detail herein.
As a possible implementation manner, the embodiment of the present application may obtain the result of multiplying the target weight matrix and the input information by subtracting a preset constant from each row based on the result of multiplication, where the preset constant may be aJI, and specifically, the preset constant is the sum of all components of the input vector I, and then is multiplied by the offset constant a.
Optionally, in an embodiment of the present application, subtracting a preset constant from each row to obtain a result of multiplying the target weight matrix by the input information, where the result includes: obtaining an output current based on the memristor array; processing information is obtained by quantizing the output current ADC, and the output information of the last row of the memristor array is subtracted to obtain a product result.
As another possible implementation manner, as shown in fig. 3, the embodiment of the present application may store all the cells in the last row of the memristor array, where the output information of the last row is the input vector [ V ] 1 ,V 2 ,V 3 ,V 4 ,V 5 ,V 6 ]Sum, product with offset parameter a results: a.V 1 +a·V 2 +a·V 3 +a·V 4 +a·V 5 +a·V 6 . After output currents of the 1 st row to the 5 th row of the memristor array are subjected to ADC quantization processing, the output information of the last row is uniformly subtracted through a subtracter, and then the product of the original matrix W and the input information I can be obtained.
In summary, the offset parameter a can be adjusted according to the parameters of the weight matrix and the resistance state distribution condition of the memristor, so that mapping of positive and negative weights is achieved, and flexibility is high. Meanwhile, the scheme that one memristor stores one weight unit is adopted, so that the requirement on hardware resources can be greatly reduced. In addition, the product of the input vector and the offset parameter is realized by adopting the memristive device, so that unnecessary circuit overhead is reduced, and the universality of the full-weight mapping method is improved.
The full weight mapping method based on the memristor array according to the embodiment of the present application is described in detail with reference to fig. 2 to 4.
As shown in fig. 4, the embodiment of the present application includes the following steps:
step S401: and uniformly adding the parameter a to the weight matrix W to obtain the weight matrix W' after the deviation. Specifically, as shown in fig. 2, the embodiment of the present application may assume a weight matrix W of scale, and the parameter distribution range is (W) 1 ，W 2 ) Wherein W is 1 ≠-W 2 。
A constant a is added to all parameters in the weight matrix W at the same time, so that the parameter range is translated into an interval (W) which can be mapped by the resistive random access unit 1 +a，W 2 + a), the elements of the weight matrix W' after offset are mapped into the memristor array one by one, and one unit corresponds to one weight.
Step S402: w' is stored in the memristive array in the form of a conductance. Specifically, in the embodiment of the present application, the image or voice information after being encoded is the input information I, and the embodiment of the present application may encode the input information I into a series of voltage pulses [ V ] 1 ,V 2 ,V 3 ,V 4 ,V 5 ,V 6 ]。
Step S403: the W' calculation is implemented in the memristor array. In actual implementation, as shown in fig. 3, where circles of different gray levels represent memristive cells of different electrical conductivity states, the memristive cells may be 1R, 1S1R, or 1T1R structures. In the forward reasoning process, W' I corresponds to the actual output of the 1 st row to the 5 th row of the memristor array in fig. 3, and the calculation formula can be as follows:
W′＝W+aJ，
where J is an all 1 matrix of size 5 × 6.
Step S404: the sum of the input components is subtracted from the calculation result and multiplied by a parameter a. Subtracting a constant from each row of results to obtain a product of the original matrix W and the input information I, wherein the calculation formula may be as follows:
WI＝W′I-aJI，
where J is a full 1 matrix of size 5 × 6, aJI is the sum of all the components of the input vector I, multiplied by an offset constant a.
As another possible implementation manner, as shown in fig. 3, the embodiment of the present application may store all the cells in the last row of the memristor array, where the output information of the last row is the input vector [ V ] 1 ,V 2 ,V 3 ,V 4 ,V 5 ,V 6 ]Sum, product with offset parameter a results: a.V 1 +a·V 2 +a·V 3 +a·V 4 +a·V 5 +a·V 6 . After output currents of the 1 st row to the 5 th row of the memristor array are subjected to ADC quantization processing, the output information of the last row is uniformly subtracted through a subtracter, and then the product of the original matrix W and the input information I can be obtained.
According to the full weight mapping method based on the memristor array, the shifted weight matrix can be generated and stored into the memristor array in a conductance mode, the product result of input information is further obtained, the target weight matrix is obtained through calculation, weight compensation is achieved, for the weight matrix with the asymmetric distribution interval, the resistance change range of the device can be utilized to a greater extent, only a small number of additional memristor devices are used as the cost, and the flexibility and the efficiency of the realization of the memory-computation integrated hardware are improved. Therefore, the problems that in the related art, due to the fact that a differential mapping scheme is used, not only is the overhead of a hardware circuit large, but also the resistance change range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, electric conductivity is wasted, hardware efficiency is low, weight mapping requirements cannot be effectively met, and flexibility and efficiency are low are solved.
The fully weighted mapping device based on the memristor array proposed according to the embodiments of the present application is described next with reference to the accompanying drawings.
FIG. 5 is a block schematic diagram of a full weight mapping device based on a memristor array of an embodiment of the present application.
As shown in fig. 5, the memristor array-based full weight mapping apparatus 10 includes: a generating module 100, a first obtaining module 200 and a second obtaining module 300.
Specifically, the generating module 100 is configured to add preset parameters to all parameters of the target weight matrix at the same time, and generate the shifted weight matrix.
The first obtaining module 200 is configured to store the shifted weight matrix into the memristor array in a conductance form, and obtain a product result of the shifted weight matrix and the input information by using the memristor array.
And a second obtaining module 300, configured to subtract, based on the product result, a preset constant from each row to obtain a product result of the target weight matrix and the input information.
Optionally, in an embodiment of the present application, the memristor array-based full weight mapping apparatus 10 further includes: and determining a module.
The determining module is used for determining preset parameters based on the mapping relation between the elements of the shifted weight matrix and the memristor array before adding the preset parameters to all the parameters of the target weight matrix at the same time, so that the parameter range of the target weight matrix is translated to the mapping range of the memristor array.
Optionally, in an embodiment of the present application, the memristor array-based full weight mapping apparatus 10 further includes: a third obtaining module and an encoding module.
The third obtaining module is used for obtaining the input information before obtaining a product result of the shifted weight matrix and the input information by using the memristor array.
And the coding module is used for coding the input information into a corresponding series of voltage pulses.
Optionally, in an embodiment of the present application, the memristor array-based full weight mapping apparatus 10 further includes: the device comprises a first calculation module and a second calculation module.
The first calculation module is used for calculating the sum of all components of the input vector of the input information before subtracting the preset constant from each line.
And the second calculation module is used for multiplying the sum by the preset parameter to obtain a preset constant.
Optionally, in an embodiment of the present application, the second obtaining module 300 is further configured to obtain an output current based on the memristor array, obtain processing information by quantizing the output current ADC, and subtract the output information of the last row of the memristor array to obtain a product result.
It should be noted that the foregoing explanation of the embodiment of the memristor array-based full weight mapping method is also applicable to the memristor array-based full weight mapping apparatus of this embodiment, and details are not repeated here.
According to the full weight mapping device based on the memristor array, the shifted weight matrix can be generated and stored into the memristor array in a conductance mode, the product result of input information is further obtained, the target weight matrix is obtained through calculation, weight compensation is achieved, for the weight matrix with the asymmetric distribution interval, the resistance change range of the device can be utilized to a greater extent, only a small number of additional memristor devices are used as the cost, and the flexibility and the efficiency of the realization of the memory-calculation integrated hardware are improved. Therefore, the problems that in the related art, due to the fact that a differential mapping scheme is used, not only is the overhead of a hardware circuit large, but also the variable resistance range of a device cannot be effectively utilized for a weight matrix with an asymmetric distribution interval, not only are the electrical state waste and the hardware efficiency low, but also the weight mapping requirements cannot be effectively met, and the flexibility and the efficiency are low are solved.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may include:
a memory 601, a processor 602, and a computer program stored on the memory 601 and executable on the processor 602.
The processor 602, when executing the program, implements the full weight mapping method based on the memristor array provided in the above embodiments.
Further, the electronic device further includes:
a communication interface 603 for communication between the memory 601 and the processor 602.
The memory 601 is used for storing computer programs that can be run on the processor 602.
If the memory 601, the processor 602 and the communication interface 603 are implemented independently, the communication interface 603, the memory 601 and the processor 602 may be connected to each other through a bus and perform communication with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 6, but that does not indicate only one bus or one type of bus.
Alternatively, in practical implementation, if the memory 601, the processor 602, and the communication interface 603 are integrated on a chip, the memory 601, the processor 602, and the communication interface 603 may complete communication with each other through an internal interface.
The processor 602 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present Application.
The present embodiments also provide a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements the memristor array-based full weight mapping method as above.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "N" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more N executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, for example, as a sequential list of executable instructions that may be thought of as implementing logical functions, may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that may fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or N wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (12)
1. A full weight mapping method based on a memristor array is characterized by comprising the following steps:
adding preset parameters to all parameters of the target weight matrix at the same time, and generating a shifted weight matrix;
storing the shifted weight matrix into a memristor array in a conductance mode, and acquiring a product result of the shifted weight matrix and input information by using the memristor array; and
and on the basis of the product result, subtracting a preset constant from each row respectively to obtain a product result of the target weight matrix and the input information.
2. The method according to claim 1, further comprising, before adding all parameters of the target weight matrix to the preset parameters at the same time:
determining the preset parameters based on the mapping relation between the elements of the shifted weight matrix and the memristor array, so that the parameter range of the target weight matrix is translated to the mapping range of the memristor array.
3. The method of claim 1, further comprising, prior to obtaining a product result of the biased weight matrix and input information with the memristor array:
acquiring the input information;
the input information is encoded into a corresponding series of voltage pulses.
4. The method according to claim 1, before subtracting the preset constant from each row, further comprising:
calculating a sum of all components of an input vector of the input information;
and multiplying the sum by the preset parameter to obtain the preset constant.
5. The method according to any one of claims 1-4, wherein subtracting a predetermined constant from each row to obtain a product of the target weight matrix and the input information comprises:
obtaining an output current based on the memristor array;
and quantizing the output current ADC to obtain processing information, and subtracting the output information of the last row of the memristor array to obtain the product result.
6. A full weight mapping apparatus based on a memristor array, comprising:
the generating module is used for simultaneously adding preset parameters to all parameters of the target weight matrix and generating a shifted weight matrix;
the first obtaining module is used for storing the shifted weight matrix into a memristor array in a conductance mode and obtaining a product result of the shifted weight matrix and input information by using the memristor array; and
and the second acquisition module is used for subtracting a preset constant from each row respectively based on the product result to obtain the product result of the target weight matrix and the input information.
7. The apparatus of claim 6, further comprising:
a determining module, configured to determine the preset parameter based on a mapping relationship between the element of the shifted weight matrix and the memristor array before adding the preset parameter to all parameters of the target weight matrix at the same time, so that a parameter range of the target weight matrix is translated to a mapping range of the memristor array.
8. The apparatus of claim 6, further comprising:
a third obtaining module, configured to obtain the input information before obtaining a product result of the shifted weight matrix and the input information by using the memristor array;
and the coding module is used for coding the input information into a corresponding series of voltage pulses.
9. The apparatus of claim 6, further comprising:
a first calculating module, configured to calculate a sum of all components of an input vector of the input information before the preset constant is subtracted from each row, respectively;
and the second calculation module is used for multiplying the sum by the preset parameter to obtain the preset constant.
10. The apparatus of any one of claims 6-9, wherein the second obtaining module is further configured to obtain an output current based on the memristor array, obtain processing information by quantizing the output current ADC, and subtract the output information of the last row of the memristor array to obtain the multiplication result.
11. An electronic device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the memristor array-based full weight mapping method of any of claims 1-5.
12. A computer-readable storage medium having a computer program stored thereon, the program being executable by a processor for implementing the memristor array-based full weight mapping method of any of claims 1-5.
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