CN115098421A - Method and device for supporting parallel bus IO signal positive and negative connection - Google Patents
Method and device for supporting parallel bus IO signal positive and negative connection Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0004—Parallel ports, e.g. centronics
Abstract
The invention provides a method, a system, equipment and a storage medium for supporting the positive and negative connection of parallel bus IO signals, wherein the method comprises the following steps: connecting first pins of a plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in sequence; connecting second pins of a plurality of input/output interfaces of a second chip to corresponding pad circuits through switches in a reverse order; arranging an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter, and controlling a switch corresponding to the second pin according to a second pin of the inverter; and determining the levels of the first pin and the second pin of the phase inverter according to the connection relation between the first chip and the second chip, and respectively controlling the on-off of all switches through the levels. According to the invention, the IO positive and negative connection circuit is built through the combination of the phase inverter and the switch in the chip, so that the parallel bus IO signal supports positive sequence connection communication and also supports reverse sequence connection communication.
Description
Technical Field
The present invention relates to the field of chip design, and more particularly, to a method, system, device and storage medium for supporting a forward/reverse connection of IO signals of a parallel bus.
Background
At present, a plurality of chips are arranged in electronic equipment, and the chips are interconnected through a parallel bus to increase the signal transmission speed and meet the requirements of practical application. When the chip is connected with the chip, IO serial numbers in the parallel bus need to be in one-to-one correspondence, and the parallel bus can normally receive and transmit data, as shown in fig. 1 and fig. 2.
When the Device1 sends data to the Device2 through the connected parallel bus, the IO1 of the Device1 must be connected with the IO1 of the Device2, and the IO1 of the Device2 receives the data and sends the data to the inside of the Device2 chip through the IO1 pad circuit for processing; the IO2 of the Device1 is connected with the IO2 of the Device2, and the IO2 of the Device2 receives data and transmits the data to the interior of the Device2 chip for processing through the IO2 pad circuit; the IO3 of the Device1 is connected with the IO3 of the Device2, and the IO3 of the Device2 receives data and transmits the data to the interior of the Device2 chip for processing through the IO3 pad circuit; the IO4 of the Device1 is connected with the IO4 of the Device2, and the IO4 of the Device2 receives data and transmits the data to the interior of the Device2 chip for processing through the IO4 pad circuit; the parallel bus can work normally.
When the Device1 receives data from the Device2 through the connected parallel bus, the IO1 of the Device1 must be connected with the IO1 of the Device2, the Device2 chip internally transmits the data to the IO1 pad circuit of the Device2, and then transmits the data to the IO1 of the Device1 through the IO1 of the Device 2; the IO2 of the Device1 is connected with the IO2 of the Device2, and the Device2 chip internally sends data to the IO2 pad circuit of the Device2 and then sends the data to the IO2 of the Device1 through the IO2 of the Device 2; the IO3 of the Device1 is connected with the IO3 of the Device2, and the chip of the Device2 internally transmits data to the IO3 pad circuit of the Device2 and then transmits the data to the IO3 of the Device1 through the IO3 of the Device 2; the IO4 of the Device1 is connected with the IO4 of the Device2, and the chip of the Device2 internally transmits data to the IO4 pad circuit of the Device2 and then transmits the data to the IO4 of the Device1 through the IO4 of the Device 2; the parallel bus can operate normally.
In order to enable the interconnection IO serial numbers of the two chips to be in one-to-one correspondence, the PCB often needs to be wound or penetrated when being wired so as to meet the requirement of the one-to-one correspondence of the interconnection IO serial numbers. The flexibility of the connection of the parallel buses among the chips is not enough, the serial numbers of IO signals can only be connected and communicated in a one-to-one correspondence mode, the serial numbers of the IO signals cannot be connected and communicated in a reverse order correspondence mode, the wiring length and area of the PCB are increased, and the manufacturing cost of the PCB is increased.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for supporting forward and reverse connection of parallel bus IO signals.
Based on the above purpose, an aspect of the embodiments of the present invention provides a method for supporting a forward/reverse connection of parallel bus IO signals, including the following steps: connecting first pins of a plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in sequence; connecting second pins of a plurality of input/output interfaces of a second chip to corresponding pad circuits through switches in a reverse order; arranging an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter, and controlling a switch corresponding to the second pin according to a second pin of the inverter; and determining the levels of the first pin and the second pin of the phase inverter according to the connection relation of the first chip and the second chip, and respectively controlling the on-off of all switches through the levels.
In some embodiments, the determining the levels of the first pin and the second pin of the inverter according to the connection relationship between the first chip and the second chip includes: responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and controlling a first pin of the phase inverter to be at a low level and controlling a second pin of the phase inverter to be at a high level in response to the first chip and the second chip being reversely connected.
In some embodiments, the separately controlling the on and off of all the switches by the level includes: responding to the high level of a first pin of the phase inverter, and controlling switches corresponding to the first pin to be closed; and responding to the low level of the second pin of the phase inverter, and controlling the switches corresponding to the second pin to be switched off.
In some embodiments, the method further comprises: connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
In another aspect of the embodiments of the present invention, a system for supporting a forward and reverse connection of IO signals of a parallel bus is provided, including: the first connecting module is configured for connecting the first pins of the plurality of input/output interfaces of the second chip to the corresponding pad circuits through the switches in sequence; the second connecting module is configured to connect second pins of the plurality of input/output interfaces of the second chip to corresponding pad circuits through the switches in a reverse order; the first control module is configured to be used for setting an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter and controlling a switch corresponding to the second pin according to a second pin of the inverter; and the second control module is configured to determine the levels of the first pin and the second pin of the phase inverter according to the connection relation between the first chip and the second chip, and respectively control the on-off of all the switches through the levels.
In some embodiments, the second control module is configured to: responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and controlling a first pin of the phase inverter to be at a low level and controlling a second pin of the phase inverter to be at a high level in response to the first chip and the second chip being reversely connected.
In some embodiments, the second control module is configured to: responding to the high level of a first pin of the phase inverter, and controlling the switches corresponding to the first pin to be closed; and responding to the low level of the second pin of the phase inverter, and controlling the switches corresponding to the second pin to be switched off.
In some embodiments, the system further comprises a power module configured to: connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: an IO positive and negative connection circuit is built through the combination of the phase inverter and the switch in the chip, so that the parallel bus IO signal supports positive sequence connection communication and also supports reverse sequence connection communication.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art two chip being connected in the forward direction;
FIG. 2 is a schematic diagram of a port and a pad connection when two chips are connected in the forward direction in the prior art;
FIG. 3 is a schematic diagram illustrating an embodiment of a method for supporting a forward/reverse connection of IO signals of a parallel bus according to the present invention;
FIG. 4 is a schematic diagram of the two chips provided by the present invention when they are connected;
FIG. 5 is a schematic diagram of the present invention showing two chips connected in reverse;
FIG. 6 is a diagram illustrating an embodiment of a system supporting forward and reverse connection of IO signals of a parallel bus according to the present invention;
FIG. 7 is a schematic diagram of a hardware structure of an embodiment of a computer device supporting forward and reverse connection of parallel bus IO signals according to the present invention;
FIG. 8 is a schematic diagram of an embodiment of a computer storage medium supporting a forward-reverse connection of parallel bus IO signals according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of the embodiments of the present invention, an embodiment of a method for supporting forward and backward connections of IO signals of a parallel bus is provided. Fig. 3 is a schematic diagram illustrating an embodiment of the method for supporting the forward and reverse connection of the parallel bus IO signals according to the present invention. As shown in fig. 3, the embodiment of the present invention includes the following steps:
s1, connecting the first pins of the input/output interfaces of the second chip to the corresponding pad circuits through switches in sequence;
s2, connecting the second pins of the input/output interfaces of the second chip to the corresponding pad circuits through switches in reverse order;
s3, arranging an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter, and controlling a switch corresponding to the second pin according to a second pin of the inverter; and
and S4, determining the levels of the first pin and the second pin of the phase inverter according to the connection relation of the first chip and the second chip, and respectively controlling the on-off of all switches through the levels.
Fig. 4 is a schematic diagram of the two chips provided by the present invention in a forward connection state, and fig. 5 is a schematic diagram of the two chips provided by the present invention in a reverse connection state, as shown in fig. 4 and 5, an embodiment of the present invention includes 2 chips, 1 pull-up resistor or 1 pull-down resistor, 1 inverter, and 8 switches.
As shown in fig. 4, when the chip Device1 is connected to the chip Device2 in the forward direction, the IO serial numbers in the parallel bus need to correspond one to one, the IO1 of the chip Device1 is connected to the IO1 of the chip Device2, the IO2 of the chip Device1 is connected to the IO2 of the chip Device2, the IO3 of the chip Device1 is connected to the IO3 of the chip Device2, the IO4 of the chip Device1 is connected to the IO4 of the chip Device2, and the Device2 is externally connected to the R1 pull-up resistor to the power supply.
After power-on, a pin1 of the chip Device2 detects a high level, and corresponding switches SW1, SW3, SW5 and SW7 in the chip Device2 are all closed; the pin2 of the inverter N1 in the chip Device2 outputs a low level, and the corresponding switches SW0, SW2, SW4 and SW6 in the chip Device2 are all turned off. An IO4 pin in a chip Device2 is connected with an IO4 pad circuit, an IO3 pin in the chip Device2 is connected with an IO3 pad circuit, an IO2 pin in the chip Device2 is connected with an IO2 pad circuit, and an IO1 pin in the chip Device2 is connected with an IO1 pad circuit; the chip Device1 and the chip Device2 can perform data transceiving communication; when the chip Device1 sends data and the chip Device2 receives the data, the data is sent from the IO1-IO4 port of the chip Device1 to the IO1-IO4 port of the chip Device2, and enters the Device2 logic part through the IO1 pad circuit-IO4 pad circuit of the chip Device2 for data processing; when the chip Device1 receives data sent by the data chip Device2, the data is sent from the logic part of the Device2 to the IO1 pad circuit-IO4 pad circuit of the chip Device2, and then enters the chip Device1 through the IO1-IO4 port of the chip Device2 to the IO1-IO4 port of the chip Device1 for data processing.
As shown in fig. 5, when the chip Device1 is connected to the chip Device2 in the reverse direction, the IO serial numbers in the parallel bus need to correspond one-to-one, the IO1 of the chip Device1 is connected to the IO4 of the chip Device2, the IO2 of the chip Device1 is connected to the IO3 of the chip Device2, the IO3 of the chip Device1 is connected to the IO2 of the chip Device2, the IO4 of the chip Device1 is connected to the IO1 of the chip Device2, and the Device2 is externally connected to R2 pull-down resistor to ground.
After power-on, the pin1 of the chip Device2 detects a low level, and the corresponding switches SW1, SW3, SW5 and SW7 in the chip Device2 are all turned off; pin2 of the inverter N1 in the chip Device2 outputs a high level, and corresponding switches SW0, SW2, SW4 and SW6 in the chip Device2 are all closed; an IO4 pin in a chip Device2 is connected with an IO1 pad circuit, an IO3 pin in the chip Device2 is connected with an IO2 pad circuit, an IO2 pin in the chip Device2 is connected with an IO3 pad circuit, and an IO1 pin in the chip Device2 is connected with an IO4 pad circuit; the chip Device1 and the chip Device2 can perform data transceiving communication; when the chip Device1 sends data to the data chip Device2 for receiving data, the data is sent from the IO1-IO4 port of the chip Device1 to the IO4-IO1 port of the chip Device2, and enters the Device2 logic part through the IO1 pad circuit-IO4 pad circuit of the chip Device2 for data processing; when the chip Device1 receives data sent by the data chip Device2, the data is sent from the logic part of the Device2 to the IO1 pad circuit-IO4 pad circuit of the chip Device2, and then enters the chip Device1 through the IO4-IO1 port of the chip Device2 to the IO1-IO4 port of the chip Device1 for data processing.
It should be noted that, the steps in the embodiments of the method for supporting the forward and reverse connection of the parallel bus IO signals may be intersected, replaced, added, or deleted, and therefore, these methods for supporting the forward and reverse connection of the parallel bus IO signals, which are reasonably arranged and combined, should also belong to the protection scope of the present invention, and should not limit the protection scope of the present invention to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a system supporting forward and backward connections of IO signals of a parallel bus. As shown in fig. 6, the system 200 includes the following modules: the first connecting module is used for connecting the first pins of the input/output interfaces of the second chip to the corresponding pad circuits through the switches in sequence; the second connecting module is configured to connect second pins of the plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in a reverse order; the first control module is configured to be used for setting an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter and controlling a switch corresponding to the second pin according to a second pin of the inverter; and the second control module is configured to determine the levels of the first pin and the second pin of the phase inverter according to the connection relation between the first chip and the second chip, and respectively control the on-off of all the switches through the levels.
In some embodiments, the second control module is configured to: responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and controlling a first pin of the phase inverter to be at a low level and controlling a second pin of the phase inverter to be at a high level in response to the first chip and the second chip being reversely connected.
In some embodiments, the second control module is configured to: responding to the high level of a first pin of the phase inverter, and controlling the switches corresponding to the first pin to be closed; and controlling the switches corresponding to the second pins to be switched off in response to the second pin of the inverter being at a low level.
In some embodiments, the system further comprises a power module configured to: connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, connecting the first pins of the input/output interfaces of the second chip to the corresponding pad circuits through switches in sequence; s2, connecting second pins of a plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in a reverse order; s3, arranging an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter, and controlling a switch corresponding to the second pin according to a second pin of the inverter; and S4, determining the levels of the first pin and the second pin of the inverter according to the connection relation of the first chip and the second chip, and respectively controlling the on-off of all switches through the levels.
In some embodiments, the determining the levels of the first pin and the second pin of the inverter according to the connection relationship between the first chip and the second chip includes: responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and responding to the reverse connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a low level, and controlling a second pin of the phase inverter to be at a high level.
In some embodiments, the separately controlling the on and off of all the switches by the level includes: responding to the high level of a first pin of the phase inverter, and controlling the switches corresponding to the first pin to be closed; and responding to the low level of the second pin of the phase inverter, and controlling the switches corresponding to the second pin to be switched off.
In some embodiments, the steps further comprise: connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
Fig. 7 is a schematic diagram of a hardware structure of an embodiment of the computer device supporting positive and negative connections of parallel bus IO signals according to the present invention.
Taking the device shown in fig. 7 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, and fig. 7 illustrates the connection by a bus as an example.
The memory 302 is a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for supporting the forward and reverse connection of the parallel bus IO signals in the embodiment of the present application. The processor 301 executes various functional applications and data processing of the server by running nonvolatile software programs, instructions and modules stored in the memory 302, namely, implements a method for supporting the forward and reverse connection of parallel bus IO signals.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data region may store data created according to the use of a method supporting the forward and reverse connection of the parallel bus IO signals, or the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more computer instructions 303 corresponding to a method for supporting forward and backward connection of parallel bus IO signals are stored in the memory 302, and when executed by the processor 301, the method for supporting forward and backward connection of parallel bus IO signals in any of the above-mentioned method embodiments is executed.
Any embodiment of the computer device executing the method for supporting the forward and reverse connection of the parallel bus IO signals can achieve the same or similar effects as any corresponding method embodiment.
The invention also provides a computer readable storage medium storing a computer program for executing the method of supporting the forward and reverse connection of parallel bus IO signals when executed by a processor.
Fig. 8 is a schematic diagram of an embodiment of the computer storage medium supporting the forward and reverse connection of parallel bus IO signals according to the present invention. Taking the computer storage medium as shown in fig. 8 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for supporting the positive and negative connection of the IO signals of the parallel bus can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for supporting parallel bus IO signal positive and negative connection is characterized by comprising the following steps:
connecting first pins of a plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in sequence;
connecting second pins of a plurality of input/output interfaces of a second chip to corresponding pad circuits through switches in a reverse order;
arranging an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter, and controlling a switch corresponding to the second pin according to a second pin of the inverter; and
and determining the levels of the first pin and the second pin of the phase inverter according to the connection relation of the first chip and the second chip, and respectively controlling the on-off of all switches through the levels.
2. The method of claim 1, wherein the determining the levels of the first pin and the second pin of the inverter according to the connection relationship between the first chip and the second chip comprises:
responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and
and in response to the reverse connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a low level and controlling a second pin of the phase inverter to be at a high level.
3. The method of claim 2, wherein the separately controlling the on and off of all switches by the level comprises:
responding to the high level of a first pin of the phase inverter, and controlling the switches corresponding to the first pin to be closed; and
and controlling the switches corresponding to the second pins to be switched off in response to the second pin of the inverter being at a low level.
4. The method of claim 1, further comprising:
connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and
responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
5. A system for supporting positive and negative connections of parallel bus IO signals, comprising:
the first connecting module is used for connecting the first pins of the input/output interfaces of the second chip to the corresponding pad circuits through the switches in sequence;
the second connecting module is configured to connect second pins of the plurality of input/output interfaces of the second chip to corresponding pad circuits through switches in a reverse order;
the first control module is configured to be used for setting an inverter in the second chip, controlling a switch corresponding to the first pin according to a first pin of the inverter and controlling a switch corresponding to the second pin according to a second pin of the inverter; and
and the second control module is configured to determine the levels of the first pin and the second pin of the phase inverter according to the connection relation between the first chip and the second chip and respectively control the on-off of all the switches through the levels.
6. The system of claim 5, wherein the second control module is configured to:
responding to the positive connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a high level, and controlling a second pin of the phase inverter to be at a low level; and
and in response to the reverse connection of the first chip and the second chip, controlling a first pin of the phase inverter to be at a low level and controlling a second pin of the phase inverter to be at a high level.
7. The system of claim 6, wherein the second control module is configured to:
responding to the high level of a first pin of the phase inverter, and controlling the switches corresponding to the first pin to be closed; and
and controlling the switches corresponding to the second pins to be switched off in response to the second pin of the inverter being at a low level.
8. The system of claim 5, further comprising a power module configured to:
connecting a pull-up resistor externally to a power supply to the second chip in response to the first chip being connected positively to the second chip; and
responding to the first chip and the second chip being reversely connected, and externally connecting the second chip with a pull-down resistor to the ground.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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