CN115097750A - Transparent configuration method and system for online hardware experiment - Google Patents
Transparent configuration method and system for online hardware experiment Download PDFInfo
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- CN115097750A CN115097750A CN202210652190.XA CN202210652190A CN115097750A CN 115097750 A CN115097750 A CN 115097750A CN 202210652190 A CN202210652190 A CN 202210652190A CN 115097750 A CN115097750 A CN 115097750A
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- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention belongs to the field of on-line hardware experiment teaching, and particularly relates to a transparent configuration method and a transparent configuration system for on-line hardware experiments, which are used for hardware configuration between a core control panel and a peripheral module and establishing a remote connection relationship between a user end upper computer and a laboratory configuration server through the Internet; the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory; the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to automatically generate a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file. The invention can realize flexible and transparent configuration of the remote experiment platform, improve the effect of the on-line hardware experiment, achieve the purpose of the on-line hardware experiment and facilitate the application of actual scenes.
Description
Technical Field
The invention belongs to the field of on-line hardware experiment teaching, and particularly relates to a transparent configuration method and system for an on-line hardware experiment.
Background
The development of modern education is greatly promoted by the development of computer and network communication technologies, and the teaching contents, forms and the like are greatly changed from multimedia classrooms to the recently developed MOOC (large open online courseware). On-line courses, online live courses and even main teaching means sometimes become, and online teaching contents, methods and the like also become research hotspots in time. Some software experiment courses are converted from online to online, so that a good effect is achieved, and some worker courses closely related to physical equipment are also used for exploring online experiments and even establishing online laboratories. The online laboratory has two forms, namely a virtual laboratory and a remote laboratory, the virtual laboratory adopts software simulation, does not relate to actual hardware equipment, and has a gap with a real experimental environment in the aspects of experimental experience, effect and the like; the latter utilizes the network to interact with real devices, so that the user has an immersive sensation even though the user is in a remote place. Compared with an offline laboratory, the online laboratory has the following advantages: 1) convenient management and reduced loss. Off-line laboratory facilities are numerous, existing power, circuit board, instrument, circuit module, connecting wire etc. in addition, after the experiment class, it is mixed and disorderly that relevant equipment is placed, and arrangement work load is very big, loses, damages also to take place occasionally. The remote online laboratory also has related equipment, but as students do not directly contact with the equipment, unified deployment and management are facilitated. 2) And the space-time boundary is broken, and the utilization rate of a laboratory is greatly improved. Off-line laboratories mostly have to be developed on class, and the utilization rate is low. To improve utilization, some schools try to open laboratories, but are cumbersome to manage. The on-line remote laboratory can be used for carrying out experiments at any time and any place, so that students can make full use of personal time and experimental equipment conveniently, and the utilization rate and the learning efficiency of the laboratory are effectively improved. 3) The experimental process is convenient to record, and the study condition of students can be comprehensively mastered. When the off-line experiment is carried out, a plurality of students exist, and teachers are difficult to pay attention to the experiment process of each student and are more unlikely to give guidance one by one. The on-line experiment can fully utilize the experiment management system and the experimental live-action monitoring equipment to record the experimental process, so that a teacher can master the learning condition of each student according to the relevant experimental record.
From the above, the online experiment system has very important significance in promoting the construction and development of online experiment courses, exploring a mixed teaching mode of the online experiment courses and the like. However, since the hardware configuration experiment platform is generally composed of a core control board and various sensor peripheral modules, it is often necessary to arrange the field plugging and unplugging related modules according to the experiment contents for system configuration. Therefore, how to automatically and transparently configure an online laboratory platform in an online laboratory becomes an urgent problem to be solved.
Disclosure of Invention
Therefore, the invention provides a transparent configuration method and a transparent configuration system for an online hardware experiment, which can realize flexible and transparent configuration of an online experiment platform, improve the effect of the online hardware experiment, achieve the purpose of the online hardware experiment and facilitate the application of an actual scene.
According to the design scheme provided by the invention, an on-line hardware experiment transparent configuration method is provided, which is used for system configuration between a core control board and a peripheral module, and comprises the following contents:
establishing a remote connection relation between a user end upper computer and a laboratory configuration server through the Internet;
the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory;
the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to acquire a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
As the transparent configuration method for the online hardware experiment, the user side further establishes the connection relationship between the core control panel and the peripheral module by utilizing the upper computer software according to the experiment requirement.
As the transparent configuration method for the online hardware experiment, the connection relation is transmitted to the configuration server by the user side by using a communication transmission protocol between the upper computer and the configuration server.
As the transparent configuration method for the online hardware experiment of the present invention, further, the communication transmission protocol includes: the number of the connecting lines between the core control boards and the peripheral modules, the number of the connecting lines of the core control boards and the number of the connecting lines of the peripheral modules corresponding to the number of the connecting lines of each core control board.
As the transparent configuration method for the online hardware experiment, the invention further determines the use condition of the pin of the FPGA development board according to the connection relation table, and the determined use condition of the pin of the FPGA development board at least comprises the following steps: input and output types and communication logic among pins.
As the transparent configuration method for the on-line hardware experiment, the invention further obtains the circuit logic configuration file and the pin constraint file of the FPGA development board, and respectively generates the circuit logic configuration file and the pin constraint file corresponding to the electrical characteristics according to the electrical characteristics of the connection signal between the core control board and the peripheral module, wherein the electrical characteristics at least comprise: unidirectional transmission of digital signals, bidirectional transmission of digital signals and analog signals.
As the transparent configuration method for the on-line hardware experiment, when a unidirectional digital signal exists between the core control board and the peripheral module, a circuit logic configuration file and a pin constraint file are generated according to whether voltages among the core control board, the FPGA development board and the peripheral module are consistent or compatible, if the voltages among the core control board, the FPGA development board and the peripheral module are consistent or compatible, the pin connection is directly carried out by using internal connection resources of the FPGA development board to generate the circuit logic configuration file and the pin constraint file, and if the voltages among the core control board, the FPGA development board and the peripheral module are not matched, a level conversion chip for voltage matching is arranged on the FPGA development board to regenerate the corresponding circuit logic configuration file and the corresponding pin constraint file.
As the transparent configuration method for the on-line hardware experiment, when bidirectional digital signals or analog signals exist between the core control board and the peripheral module, corresponding signals between the core control board signals and the peripheral module are respectively connected to two ends of the multi-channel selector, configuration signals of the multi-channel selector are connected to pins of the FPGA development board, and corresponding circuit logic configuration files and pin constraint files are generated.
As the transparent configuration method for the online hardware experiment, disclosed by the invention, further, in the automatic configuration of the FPGA development board by calling an FPGA development tool, a target circuit logic configuration file and a pin constraint file are added into a development project by utilizing a TCL script, a bit stream file is generated by running, and the target FPGA development board is automatically configured by utilizing the bit stream file.
Further, the present invention also provides an on-line hardware experiment transparent configuration system for system configuration between a core control board and a peripheral module, comprising: the system comprises a plurality of user end upper computers and a laboratory configuration server which establishes a remote connection relation with each user end upper computer through the Internet; wherein the content of the first and second substances,
the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory;
the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to obtain a circuit logic configuration file and pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
The invention has the beneficial effects that:
the invention establishes the connection relationship between the core control panel and the peripheral module by using the upper computer, transmits the connection relationship to the remotely connected laboratory configuration server, automatically generates the FPGA development board circuit logic configuration file and the pin constraint file based on the hardware description language by the configuration server, and realizes the connection between the core control panel and the peripheral module by using the internal resources of the FPGA development board, namely, the FPGA is used as a bridge to realize the purpose of flexible hardware configuration, thereby really realizing the remote hardware experimental configuration and having better application prospect.
Description of the drawings:
FIG. 1 is a schematic diagram of an on-line transparent configuration process of an on-line hardware experiment in an embodiment;
FIG. 2 is a schematic diagram of circuit classification processing of an FPGA development board in an embodiment;
fig. 3 is a schematic diagram of the working principle of the on-line hardware experiment transparentization configuration in the embodiment.
The specific implementation mode is as follows:
in order to make the objects, technical solutions and advantages of the present invention clearer and more obvious, the present invention is further described in detail below with reference to the accompanying drawings and technical solutions.
An embodiment of the present invention, as shown in fig. 1, provides a transparent configuration method for an online hardware experiment, which is used for hardware configuration between a core control board and a peripheral module, and includes the following contents:
s101, establishing a remote connection relation between a user end upper computer and a laboratory configuration server through the Internet;
s102, a user side generates a connection relation between a core control panel and a peripheral module by using an upper computer, and uploads the connection relation to a configuration server in a laboratory;
s103, the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to automatically generate a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
The method comprises the steps of establishing a connection relation between a core control panel and a peripheral module by using an upper computer, uploading the connection relation to a remotely connected laboratory configuration server, automatically generating a circuit logic configuration file and a pin constraint file of an FPGA development board based on a hardware description language through the configuration server, and realizing the connection between the core control panel and the peripheral module by using internal resources of the FPGA development board, namely realizing the purpose of flexible, efficient and reliable configuration of hardware by using the FPGA as a bridge, thereby really realizing the remote experimental configuration of the hardware.
Further, in the embodiment of the present invention, the user end establishes the connection relationship between the core control board and the peripheral module by using the upper computer software according to the experimental requirements. And further, the user side transmits the connection relation to the configuration server by using a communication transmission protocol between the upper computer and the configuration server. And after receiving the connection relation, the configuration server automatically generates a configuration file based on a hardware description language, and realizes the automatic transparent configuration of the peripheral module through operations such as automatic compiling, layout and wiring, downloading and the like.
Further, in this embodiment, the communication transmission protocol includes: the number of the connecting lines between the core control board and the peripheral module, the number of the connecting lines of the core control boards and the number of the connecting lines of the peripheral module corresponding to the number of the connecting lines of each core control board.
The communication transmission protocol between the upper computer and the configuration server can be shown in the following table:
| N | P1 | S1 | P2 | S2 | ...... | PN | SN |
wherein N represents that N pairs of lines are connected between the core control board and the sensor; p1 and S1 represent the first pair of connection lines of the core control board and the sensor, and PN and SN represent the Nth pair of connection lines of the core control board and the sensor; PN represents the processor pin number of the core control board in the Nth pair of wires, and SN represents the pin number of the sensor in the Nth pair of wires. The upper computer and the configuration server complete information transmission according to the protocol, and the configuration server can generate a connection relation corresponding table according to the information transmission.
Further, in the embodiment of the present disclosure, the usage of the pin of the FPGA development board is determined according to the connection relation table, where the determined usage of the pin of the FPGA development board at least includes: input and output types and communication logic among pins. According to the connection correspondence table between the core control board and the sensor, the use condition (including input and output types, communication logic between pins and the like) of the FPGA pin can be determined by combining the connection relation between the core control board pin, the sensor pin and the FPGA pin. According to the Verilog language format and the actual requirement, after an input pin and an output pin on the FPGA are specified, a python script is used for automatically generating a v file which accords with the grammar specification and the target function; the pin constraint file is generated using python scripts according to the FPGA pins used and the particular format of the pin constraint file (. xdc).
In the embodiment of the present disclosure, further, in the circuit logic configuration file and the pin constraint file obtained from the FPGA development board, the circuit logic configuration file and the pin constraint file corresponding to the electrical characteristics are respectively generated according to the electrical characteristics of the connection signal between the core control board and the peripheral module, where the electrical characteristics at least include: unidirectional transmission of digital signals, bidirectional transmission of digital signals and analog signals.
Referring to fig. 2, in view of a certain difference in electrical characteristics of connection signals between the core control board and the peripheral module, the FPGA development board needs to be designed according to characteristics of signals of the core control board and signals of the peripheral module, and the configuration method of the FPGA needs to be classified to realize reliable connection between the core control board and the peripheral module in an online implementation process. The core control board and the peripheral module are in one-way transmission, such as digital signals output by the core control board and input by the peripheral module or digital signals input by the core control board and output by the peripheral module. For the connection signals, if the driving voltages among the core control board, the FPGA development board and the peripheral module are consistent or compatible, the connection of corresponding pins can be realized by directly using FPGA internal connection line resources; and if the driving voltages among the core control panel, the FPGA development board and the peripheral module are not matched, adding a corresponding level conversion chip on the FPGA development board. The core control board and the peripheral module are digital signals transmitted in two directions, the FPGA circuit board connects relevant signals of the core control board and relevant signals of the peripheral module to two ends of the relay respectively, enabling signals of the relay are connected to pins of the FPGA, and the connection and communication relation of the relevant pins is realized through FPGA configuration. Between the core control board and the peripheral module is an analog signal. The FPGA circuit board connects the relevant signals between the core control board and the peripheral module to two ends of the multichannel analog selector, the configuration signals of the multichannel analog selector are connected to the pins of the FPGA, and the communication relation of the relevant pins is realized through the FPGA configuration.
Further, in the embodiment of the present disclosure, in the automatic configuration of the FPGA development board by calling the FPGA development tool, the TCL script is used to add the target circuit logic configuration file and the pin constraint file to the development project, the bitstream file is generated by running, and the bitstream file is used to automatically configure the target FPGA development board.
According to the connection correspondence table between the core control board and the peripheral module, the service condition of the FPGA pin, including the input and output type, the communication logic between the pins and the like, can be determined by searching the pin correspondence file (including the connection relation between the core control board pin, the peripheral module pin and the FPGA pin, and the function and the pin characteristics of the peripheral module). The specific method comprises the following steps: firstly, determining what the corresponding peripheral module is according to the pin number of the peripheral module, and then determining whether the pin is a digital pin for unidirectional transmission (including a transmission direction) or a digital pin for bidirectional transmission or an analog signal according to the property of the known peripheral module; and then, determining the FPGA pin according to the unidirectional transmission digital signal corresponding table, the bidirectional transmission digital corresponding table and the analog signal corresponding table.
For example, a pin Pn of a core control board processor in a connection correspondence table between a core control board and a peripheral module is connected with a pin Sm of the peripheral module, which peripheral module belongs to is determined according to the number of Sm, if the pin of the peripheral module is a unidirectional digital signal, whether the pin is an input signal or an output signal (both relative to a processor) is determined, then from the unidirectional transmission digital signal correspondence table, the pin Sm is determined to be connected with a pin Gm of an FPGA, and then the pin Fn of the FPGA connected with the pin Pn of the processor is determined. If the input is input, the assign Fn is adopted in the FPGA configuration, and if the output is output, the assign Gm is adopted in the FPGA configuration, so that the connection of the corresponding pins can be realized.
One-way transmission digital signal corresponding table
If the pin of the peripheral module is a bidirectional transmission digital signal, the number of the FPGA pin connected with the enabling end of the relay is determined according to a bidirectional transmission corresponding table, if the pin Pn of the core control board processor in the connection corresponding table between the core control board and the peripheral module is connected with the pin Sn of the peripheral module, and Sn is a bidirectional signal, the connection of Pn and Sn can be realized only by enabling a signal En in the FPGA configuration according to the bidirectional transmission digital signal corresponding table.
Bidirectional transmission digital signal corresponding table
If the pin of the peripheral module is an analog signal, the number of the FPGA pin connected with the enabling end of the multi-channel analog selector is determined according to the bidirectional transmission corresponding table, if the pin Pn of the core control board processor in the connection corresponding table between the core control board and the peripheral module is connected with the pin Sn of the peripheral module, and Sn is an analog signal, the connection of Pn and Sn can be realized only by enabling a signal En in the FPGA configuration according to the analog signal corresponding table.
Analog signal corresponding table
As the FPGA logic related in the embodiment of the invention mainly comprises two types of pin connection and enabling assignment, the corresponding program template can be customized, and for different modules, only the pin or signal name interface needs to be changed, so that the hardware description language code can be easily multiplexed. Therefore, after the FPGA connection or control pins are determined, according to the Verilog language format and the actual needs, the python script can be used for automatically generating the v file which accords with the grammar specification and the target function; for the. xdc file, the format is relatively fixed, and only the pins used in the hardware description language need to be declared in the. xdc file. The format of a pin can be declared as:
set _ property PACKAGE _ PIN + "Pin name on FPGA edition" + [ corresponding Pin name used in get _ ports +. v File ]
set _ property IOSTANDARD LVCMOS33[ corresponding pin name used in get _ ports +. v file ]
The pin constraint file (. xdc) may be automatically generated using python scripts, depending on the FPGA pins used and the particular format of the pin constraint file.
In the case of automatically generating the v file and the xdc file, the TCL (Tool Command Language) Command line provided by Vivado is used to automatically configure the FPGA, and the method mainly includes the following steps:
(1) creating a target project
(2) Adding the target v and xdc files to the target project
(3) Synthesis (Synthesis) is run.
(4) Implementation of execution (Implementation).
(5) A bitstream file is generated.
(6) And downloading the bit stream file to a target development board, and performing programming configuration on the development board.
Further, based on the foregoing method, an embodiment of the present invention further provides an on-line hardware experiment transparent configuration method, for configuring hardware between a core control board and a peripheral module, as shown in fig. 3, including: the system comprises a plurality of user end upper computers and a laboratory configuration server which establishes a remote connection relation with each user end upper computer through the Internet; wherein the content of the first and second substances,
the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory;
the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to acquire a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
Unless specifically stated otherwise, the relative steps, numerical expressions and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present invention.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still make modifications or easily conceive of changes to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features within the technical scope of the present disclosure, and such modifications, changes or substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and are intended to be covered by the present disclosure. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A transparent configuration method for on-line hardware experiment is used for hardware configuration between a core control board and a peripheral module, and is characterized by comprising the following contents:
establishing a remote connection relation between a user end upper computer and a laboratory configuration server through the Internet;
the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory;
the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to acquire a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
2. The on-line hardware experiment transparent configuration method according to claim 1, wherein the client establishes a connection relationship between the core control board and the peripheral module by using upper computer software according to experiment requirements; and the user side transmits the connection relation to the configuration server by using a communication transmission protocol between the upper computer and the configuration server.
3. The on-line hardware experiment transparent configuration method according to claim 2, wherein the communication transmission protocol comprises: the number of the connecting lines between the core control board and the peripheral module, the number of the connecting lines of the core control boards and the number of the connecting lines of the peripheral module corresponding to the number of the connecting lines of each core control board.
4. The on-line hardware experiment transparent configuration method according to claim 1, wherein the use condition of the pins of the FPGA development board is determined according to the connection relation table, and the determined use condition of the pins of the FPGA development board at least comprises: input and output types and communication logic among pins.
5. The on-line hardware experiment transparent configuration method according to claim 1 or 4, wherein in the circuit logic configuration file and the pin constraint file obtained from the FPGA development board, the circuit logic configuration file and the pin constraint file corresponding to the electrical characteristics are respectively generated according to the electrical characteristics of the connection signal between the core control board and the peripheral module, wherein the electrical characteristics at least include: unidirectional transmission of digital signals, bidirectional transmission of digital signals and analog signals.
6. The on-line hardware experiment transparent configuration method according to claim 5, wherein when a unidirectional digital signal is present between the core control board and the peripheral module, a circuit logic configuration file and a pin constraint file are generated according to whether voltages among the core control board, the FPGA development board and the peripheral module are consistent or compatible, if voltages among the core control board, the FPGA development board and the peripheral module are consistent or compatible, the internal wiring resources of the FPGA development board are directly utilized for pin connection to generate the circuit logic configuration file and the pin constraint file, and if voltages among the core control board, the FPGA development board is provided with a level conversion chip for voltage matching, and the corresponding circuit logic configuration file and the corresponding pin constraint file are regenerated.
7. The on-line hardware experiment transparent configuration method according to claim 5, wherein when bidirectional digital signals exist between the core control board and the peripheral module, corresponding signals between the core control board signals and the peripheral module are respectively connected to two ends of the relay, configuration signals of the relay are connected to pins of the FPGA development board, and corresponding circuit logic configuration files and pin constraint files are generated.
8. The on-line hardware experiment transparent configuration method according to claim 5, wherein when analog signals exist between the core control board and the peripheral module, corresponding signals between the core control board signals and the peripheral module are respectively connected to two ends of the multi-channel analog selector, configuration signals of the multi-channel analog selector are connected to pins of the FPGA development board, and corresponding circuit logic configuration files and pin constraint files are generated.
9. The on-line hardware experiment transparent configuration method according to claim 5, wherein in the automatic configuration of the FPGA development board by calling an FPGA development tool, a TCL script is used to add a target circuit logic configuration file and a pin constraint file to a development project, a bitstream file is generated by running, and the target FPGA development board is automatically configured by using the bitstream file.
10. An on-line hardware experiment transparent configuration system, which is used for hardware configuration between a core control board and a peripheral module, and is characterized by comprising: the system comprises a plurality of user end upper computers and a laboratory configuration server which establishes a remote connection relation with each user end upper computer through the Internet; wherein the content of the first and second substances,
the user side generates a connection relation between the core control panel and the peripheral module by using the upper computer, and uploads the connection relation to a configuration server in a laboratory;
the configuration server generates a connection relation table according to the connection relation between the core control board and the peripheral module, and determines the use condition of pins of the FPGA development board according to the connection relation table to generate a circuit logic configuration file and a pin constraint file of the FPGA development board; and carrying out automatic configuration on the FPGA development board by calling an FPGA development tool according to the circuit logic configuration file and the pin constraint file.
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