CN115087220A

CN115087220A - Manufacturing method of circuit board and circuit board

Info

Publication number: CN115087220A
Application number: CN202110261276.5A
Authority: CN
Inventors: 戴俊; 杨梅
Original assignee: Hongqisheng Precision Electronics Qinhuangdao Co Ltd; Avary Holding Shenzhen Co Ltd
Current assignee: Hongqisheng Precision Electronics Qinhuangdao Co Ltd; Avary Holding Shenzhen Co Ltd
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2022-09-20

Abstract

A manufacturing method of a circuit board comprises the following steps: providing a metal layer, wherein the metal layer comprises a first surface; pressing a first shielding layer on the first surface, patterning the first shielding layer to form a first insulating layer and exposing part of the first surface arranged at intervals; forming a first circuit layer on the first surface, wherein the first circuit layer comprises a first sub-circuit and a second sub-circuit which are arranged at intervals; removing the metal layer corresponding to the first sub-circuit, and electroplating the second sub-circuit to form a second circuit layer on the surface of the second sub-circuit; removing the residual metal layer; the first circuit layer is covered with a first solder mask layer and a second solder mask layer on two opposite surfaces respectively, the first solder mask layer is covered with the first insulation layer and the second circuit layer, and the second solder mask layer is covered with the first insulation layer to obtain the circuit board. The application also provides a circuit board.

Description

Manufacturing method of circuit board and circuit board

Technical Field

The present disclosure relates to the field of circuit boards, and particularly to a method for manufacturing a circuit board and a circuit board.

Background

With the trend of miniaturization of electronic products, several products with similar functions need to be connected to the same circuit board. To ensure signal integrity and power efficiency, the thickness of the circuit layers in the circuit board is often required.

The common circuit board manufacturing process adopts a local copper plating or local copper reduction mode to form circuits with different thicknesses. However, both of the two methods require at least two pattern transfers of the photosensitive layer, which easily causes deviation between the line layers formed in different pattern transfer processes, and finally the thickened line layer is step-shaped in appearance; in addition, under the influence of alignment tolerance capability, the line width requirement of the line layer thickened by the scheme is generally more than 200 μm, so that the method is not suitable for small-size packaging, high-density fine lines and thinned design; furthermore, the shadow etch scheme is not suitable for thicker metal layers, resulting in poor etching.

Disclosure of Invention

In view of the above, it is desirable to provide a method for manufacturing a circuit board with high manufacturing accuracy.

In addition, it is necessary to provide a circuit board.

A manufacturing method of a circuit board comprises the following steps:

providing a metal layer, wherein the metal layer comprises a first surface;

pressing a first shielding layer on the first surface, patterning the first shielding layer to form a first insulating layer and exposing part of the first surface arranged at intervals;

forming a first circuit layer on the first surface, wherein the first circuit layer comprises a first sub-circuit and a second sub-circuit which are arranged at intervals;

removing the metal layer corresponding to the first sub-circuit, and electroplating the second sub-circuit to form a second circuit layer on the surface of the second sub-circuit;

removing the residual metal layer;

the first circuit layer is covered with a first solder mask layer and a second solder mask layer on two opposite surfaces respectively, the first solder mask layer is covered with the first insulation layer and the second circuit layer, and the second solder mask layer is covered with the first insulation layer to obtain the circuit board.

In some embodiments, the metal layer further comprises a second surface disposed opposite the first surface; before the step of forming the first circuit layer on the first surface, the method further comprises the steps of laminating a second shielding layer on the second surface, and patterning the second shielding layer to form a second insulating layer.

In some embodiments, the thickness of the first shielding layer is greater than the thickness of the second shielding layer along the stacking direction of the first shielding layer, the metal layer, and the second shielding layer.

In some embodiments, before the step of forming the first wiring layer, the fabrication method further includes: removing the unpatterned second shielding layer to expose part of the second surface; in the step of forming the first wiring layer, a copper plating layer is also formed on the exposed second surface.

In some embodiments, before the step of forming the second circuit layer, the method further includes removing a metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, the second sub-circuit is electroplated by passing a current through a metal layer corresponding to the second sub-circuit, so that the second circuit layer is formed on the surface of the second sub-circuit.

In some embodiments, before the step of forming the second circuit layer, the method further includes removing the metal layers corresponding to the first sub-circuit and the second sub-circuit; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

In some embodiments, the step of forming the second solder mask layer further comprises a step of removing the copper plating layer.

In some embodiments, before the step of forming the first wiring layer, the fabrication method further includes: and covering an anti-plating film on the surface of the second insulating layer, which is far away from the metal layer, wherein the anti-plating film also covers the unpatterned second shielding layer.

In some embodiments, before the step of forming the second circuit layer, the method further includes removing the plating resist and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, the second sub circuit is electroplated by passing current through the metal layer corresponding to the second sub circuit, so that the second circuit layer is formed on the surface of the second sub circuit.

In some embodiments, before the step of forming the second circuit layer, the method further includes removing the plating resist and the metal layer corresponding to the first sub-circuit; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to perform electroplating on the second sub-circuit to form the second circuit layer.

A circuit board comprises a first insulating layer, a circuit layer, a first solder mask layer and a second solder mask layer, wherein the circuit layer is embedded in the first insulating layer, and the first solder mask layer and the second solder mask layer respectively cover two opposite surfaces of the first insulating layer and also cover two opposite surfaces of the circuit layer; the circuit layer comprises a thin copper area and a thick copper area, and the thickness of the circuit layer located in the thin copper area is smaller than that of the circuit layer located in the thick copper area.

According to the manufacturing method of the circuit layer, the first circuit layer is manufactured on the surfaces of the metal layers in different areas through one-time selective patterning treatment, and then the second circuit layer is selectively formed on the surface of the first circuit layer, so that the circuit manufacturing of local thick copper is achieved. The manufacturing method can be formed only by sequential pattern transfer, and deviation between formed circuit layers caused in multiple different pattern transfer processes is avoided; in addition, the manufacturing method has less etching times and is suitable for manufacturing high-precision circuits.

Drawings

Fig. 1 is a schematic cross-sectional view illustrating a first shielding layer and a second shielding layer laminated on two surfaces of a metal layer according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view illustrating the first and second shielding layers shown in the figure being patterned.

Fig. 3 is a schematic cross-sectional view of removing the first shielding layer and the second shielding layer without patterning shown in fig. 2.

Fig. 4 is a schematic cross-sectional view of the exposed first surface of the metal layer shown in fig. 3 after a first circuit layer is formed and a copper plated layer is formed on the exposed second surface.

Fig. 5 is a schematic cross-sectional view of the copper plated layer formed in fig. 4 and a metal layer corresponding to the first sub-line of the first circuit layer removed.

Fig. 6 is a schematic cross-sectional view of the first wiring layer shown in fig. 5 after a second wiring layer is formed on the surface of the second sub-wiring layer.

Fig. 7 is a schematic cross-sectional view of the first circuit layer and the second circuit layer of fig. 6 after the first solder mask layer is covered on the surfaces.

Fig. 8 is a schematic cross-sectional view of the second solder mask layer covered by the second solder mask layer after the metal layer shown in fig. 7 is removed.

Fig. 9 is a schematic cross-sectional view of the circuit board resulting from the removal of the scrap region shown in fig. 8.

Fig. 10 is a schematic cross-sectional view illustrating a patterning process performed on the first shielding layer and the second shielding layer shown in fig. 1 according to another embodiment of the present disclosure.

Fig. 11 is a schematic cross-sectional view of the second insulating layer shown in fig. 10 after being covered with an anti-plating film.

Fig. 12 is a schematic cross-sectional view of removing the unpatterned first shielding layer shown in fig. 11 to expose a portion of the metal layer.

Fig. 13 is a schematic cross-sectional view of the exposed metal layer of fig. 12 after a first circuit layer is formed thereon.

Fig. 14 is a schematic cross-sectional view of the metal layer corresponding to the plating resist, the unpatterned second shielding layer and the unpatterned second shielding layer shown in fig. 13 after removal.

Fig. 15 is a schematic cross-sectional view of a portion of the first circuit layer shown in fig. 14 after a second circuit layer is formed on the surface of the first circuit layer.

Fig. 16 is a schematic cross-sectional view of the first circuit layer and the second circuit layer shown in fig. 15 after the first solder mask layer is covered on the surfaces.

Fig. 17 is a schematic cross-sectional view of a second embodiment of the present invention, after removing metal layers corresponding to a first sub-wiring and a second sub-wiring of a first wiring layer and forming a second wiring layer on a surface of the second sub-wiring.

Fig. 18 is a plan view of the second wiring layer shown in fig. 17 after the second wiring layer is formed by connecting leads.

Description of the main elements

Circuit board	100
		Metal layer	10
First surface	12
		Second surface	14
A first shielding layer	20
		A first insulating layer	22
First region	22a
		Second region	22b
Second shielding layer	30
		A second insulating layer	32
First circuit layer	50
		First sub-circuit	52
The second sub-circuit	55
		Copper plating layer	57
Second circuit layer	60
		First solder mask layer	72
Second solder mask	75
		Product area	82
Waste area	85
		Anti-coating film	90
Thin copper region	I
		Thick copper region	II
Direction of stacking	L
		Distance between each other	d

Detailed Description

In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and the described embodiments are merely a subset of the embodiments of the present application, rather than all embodiments.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.

Referring to fig. 1 to 9, a method for manufacturing a circuit layer 100 includes steps S101 to S109.

Step S101: referring to fig. 1, a metal layer 10 is provided, the metal layer 10 includes a first surface 12 and a second surface 14 disposed opposite to each other, a first shielding layer 20 is laminated on the first surface 12, and a second shielding layer 30 is laminated on the second surface 14.

The metal layer 10 is used for conducting electricity in a subsequent electroplating process and plays a role of bearing a circuit layer in a subsequent process of forming the circuit layer. The material of the metal layer 10 may be copper, silver, nickel, or the like.

The metal layer 10 is removed in the final process. The thickness of the metal may be set according to the capabilities of the device. In the present embodiment, taking a copper foil as an example, the thickness of the copper foil is 9 μm to 18 μm. In other embodiments, this is not limiting.

Along the stacking direction L of the first shielding layer 20, the metal layer 10 and the second shielding layer 30, the thickness of the first shielding layer 20 is greater than that of the second shielding layer 30. The thickness of the first shielding layer 20 is larger because the first shielding layer 20 is selectively plated with copper on the first surface 12 after the subsequent exposure and development process and the exposed and developed part remains in the finally prepared circuit layer 100; the second shielding layer 30 is used for selectively etching the metal layer 10 in the subsequent process, and meanwhile, the metal layer needs to be completely removed in the subsequent process, so that the problem that other parts of the circuit layer 100 which do not need to be removed are damaged due to the increased difficulty in removing the second shielding layer 30 with an excessively large thickness is avoided, and therefore, the thickness of the second shielding layer 30 is small.

In some embodiments, the thickness of the first masking layer 20 is greater than 50 μm and the thickness of the second masking layer 30 is less than 30 μm.

The material of the first shielding layer 20 may be a photosensitive film, such as a photosensitive polyimide, a dry film, or a resin material, such as ABF. The photosensitive polyimide and the dry film may be exposed and developed to form a circuit pattern, and the resin material may be etched by plasma to form the circuit pattern.

In some embodiments, when the first shielding layer 20 and the second shielding layer 30 are both dry films, the difficulty of removing the first shielding layer 20 and the second shielding layer 30 is different because the thickness of the first shielding layer 20 is greater than that of the second shielding layer 30. In some embodiments, the first shielding layer 20 may be removed by ultrasonic oscillation in a special organic stripping solution, and the processing time is longer than 8 min; the second shielding layer 30 can be removed by NaOH solution, and the processing time is less than 2 min.

Step S102: referring to fig. 2, a first insulating layer 22 is patterned on the first shielding layer 20, and a second insulating layer 32 is patterned on the second shielding layer 30.

In the present embodiment, the first shielding layer 20, which does not need to form a wiring layer, is exposed to convert the exposed portion of the first shielding layer 20 into the first insulating layer 22, and the first insulating layer 22 finally remains in the formed wiring layer 100. The first insulating layer 22 includes a first region 22a and a second region 22b, wherein the pattern in the first region 22a is subsequently used to form a thin copper line layer, and the pattern in the second region 22b is subsequently used to form a thick copper line layer.

The second shielding layer 30 is exposed, and the exposed region of the second shielding layer 30 at least includes a portion corresponding to the first region 22a, so that the metal layer 10 corresponding to the first region 22a is conveniently removed in a subsequent process, thereby facilitating adjustment of the thickness of the circuit layer formed in the first region 22a and the second region 22 b.

Step S103: referring to fig. 3, the unpatterned first shielding layer 20 is removed to expose a portion of the first surface 12, and the unpatterned second shielding layer 30 is removed to expose a portion of the second surface 14.

In the present embodiment, the unpatterned first shielding layer 20 and the unpatterned second shielding layer 30 are removed by development. After the first shielding layer 20 is removed, a portion of the first surface 12 is exposed for forming a circuit layer. The first insulating layer 22 covers a portion of the first surface 12, and the second insulating layer 32 covers a portion of the second surface 14.

Step S104: referring to fig. 4, a first circuit layer 50 is formed on the first surface 12, and a copper plating layer 57 is formed on the second surface 14, wherein the first circuit layer 50 includes a first sub-circuit 52 and a second sub-circuit 55.

In the present embodiment, the metal layer 10 is subjected to a plating process, thereby forming the first wiring layer 50 on the exposed first surface 12. The first wiring layer 50 formed in the first region 22a is a first sub-wiring 52, and the first wiring layer 50 formed in the second region 22b is a second sub-wiring 55, that is, the first wiring layer 50 includes a first sub-wiring 52 and a second sub-wiring 55, and the first sub-wiring 52 and the second sub-wiring 55 are spaced apart from each other by the first insulating layer 22.

The copper plating layer 57 is formed on the exposed second surface 14 simultaneously with the electroplating process.

Step S105: referring to fig. 5, the second insulating layer 32 is removed to expose the second surface 14 corresponding to the first region 22 a; and removing the copper plating layer 57 and the metal layer 10 corresponding to the first sub-circuit 52.

In the present embodiment, the copper plating layer 57 and the metal layer 10 corresponding to the first sub-wiring 52 are removed by etching. The metal layer 10 corresponding to the first sub-circuit 52 is removed, so that the current flowing through the first sub-circuit 52 in the subsequent electroplating process can be blocked, and a circuit layer is continuously formed on the surface of the first sub-circuit 52.

In some embodiments, to ensure that the metal layer 10 corresponding to the first sub-circuit 52 is sufficiently removed, the etching strength is increased to remove a portion of the first sub-circuit 52.

Step S106: referring to fig. 6, a second circuit layer 60 is formed on the surface of the second sub-circuit 55.

In the present embodiment, the second circuit layer 60 is formed by electroplating. The second sub-wiring 55 is plated by passing a current through the metal layer 10 corresponding to the second sub-wiring 55, so that the second wiring layer 60 is formed on the surface of the second sub-wiring 55.

The first sub-circuit 52 of the first circuit layer 50 forms a thin copper area I, and the second sub-circuit 55 of the first circuit layer 50 and the second circuit layer 60 formed on the surface of the second sub-circuit 55 form a thick copper area II. In some embodiments, the thickness of the circuit layer in the thin copper region I is 12 μm to 20 μm, and the thickness of the circuit layer in the thick copper region II is 40 μm to 60 μm; the line layer is formed by an additive method, and the line width perpendicular to the stacking direction L is easier to control than the line width formed by a subtractive method and can be smaller than 30 μm.

Step S107: referring to fig. 7, a first solder mask layer 72 is covered on a surface of the first circuit layer 50 away from the metal layer 10, and the first solder mask layer 72 further covers the second circuit layer 60 and the first insulating layer 22.

Step S108: referring to fig. 8, the metal layer 10 is removed; a second solder mask layer 75 covers the surface of the first circuit layer 50 away from the first solder mask layer 72, and the second solder mask layer 75 also covers the first insulating layer 22.

The metal layer 10 may be removed by etching to expose the surface of the first circuit layer 50.

In some embodiments, the step of removing the copper plating layer 57 precedes the step of overlaying the second solder mask layer 75.

Step S109: referring to fig. 9, the waste area 85 except the product area 82 is removed to obtain the circuit layer 100.

The thin copper area I and the thick copper area II are located in the product area 82, and unnecessary first insulating layer 22, first solder mask layer 72, and second solder mask layer 75 are removed to obtain the circuit layer 100.

In some embodiments, the step of removing the waste zone 85 may also be omitted.

Referring to fig. 1 and fig. 8 to 16, a method for manufacturing a circuit layer 100 according to another embodiment of the present application includes steps S201 to S210.

Step S201: referring to fig. 1 again, a metal layer 10 is provided, the metal layer 10 includes a first surface 12 and a second surface 14 disposed opposite to each other, a first shielding layer 20 is laminated on the first surface 12, and a second shielding layer 30 is laminated on the second surface 14.

That is, the step S201 may be the same as the step S101, and is not described herein again.

Step S202: referring to fig. 10, a first insulating layer 22 is patterned on the first shielding layer 20, and a second insulating layer 32 is patterned on the second shielding layer 30.

In this embodiment, the second shielding layer 30 without being patterned may be a region corresponding to the thin copper region I to be formed later. In other embodiments, the second shielding layer 30 without patterning may further include a region corresponding to the thick copper region II formed later.

Step S203: referring to fig. 11, an anti-plating film 90 covers the surface of the second insulating layer 32, and the anti-plating film 90 also covers the second shielding layer 30 that is not patterned.

The anti-plating film 90 can be made of black opaque material and is attached at low temperature and low pressure.

The plating resist film 90 is used to prevent the formation of the copper plating layer 57 on the second surface 14 of the metal layer 10 during the subsequent plating process, so that the step of removing the copper plating layer 57 can be reduced.

Step S204: referring to fig. 12, the unpatterned first shielding layer 20 is removed to expose a portion of the first surface 12.

Step S205: referring to fig. 13, a first circuit layer 50 is formed on the first surface 12 by electroplating the metal layer 10, wherein the first circuit layer 50 includes a first sub-circuit 52 and a second sub-circuit 55.

Step S206: referring to fig. 14, the plating resist film 90 is removed; and removing the unpatterned second shielding layer 30 and the metal layer 10 corresponding to the unpatterned second shielding layer 30.

Step S207: referring to fig. 15, a second circuit layer 60 is formed by electroplating the second sub-circuit 55.

In the present embodiment, a lead wire (not shown) for plating may be directly connected to the metal layer 10 corresponding to the second sub-wiring 55 for plating.

Step S208: referring to fig. 16, a first solder mask layer 72 is covered on a surface of the first circuit layer 50 away from the metal layer 10, and the first solder mask layer 72 further covers the second circuit layer 60 and the first insulating layer 22.

Step S209: referring to fig. 8 again, the second insulating layer 32 and the metal layer 10 are removed; a second solder mask layer 75 covers the surface of the first circuit layer 50 away from the first solder mask layer 72, and the second solder mask layer 75 also covers the first insulating layer 22.

Step S210: referring to fig. 9 again, the waste region 85 is removed to obtain the circuit layer 100.

Referring to fig. 17 and 18, in some embodiments, in step S102 or step S202, the region exposed to the second shielding layer 30 may further include a portion corresponding to the second region 22 b. In the step of forming the second wiring layer 60, leads for conduction may be selectively connected on the first wiring layer 50 formed in the second region 22b, so that the second region 22b is plated to form the second wiring layer 60. The leads may be additional connections or leads reserved for electrical conduction during etching. In the present embodiment, the plating is performed by a lead connecting the second sub-wiring 55 and the metal layer 10 corresponding to the scrap region 85. The alignment error caused by selective etching when the second shielding layer 30 is shielded can be avoided by electroplating through the connecting lead, the distance d between the thin copper area I and the thick copper area II can be reduced, and the distance d can be smaller than 50 micrometers.

In the present embodiment, since the lead is also connected to the metal layer 10 located in the scrap region 85, a copper plated layer is formed on the surface of the second sub-wiring 55 in the scrap region 85.

Referring to fig. 9, the present application further provides a circuit layer 100, where the circuit layer 100 includes a first insulating layer 22, a circuit layer, a first solder mask layer 72 and a second solder mask layer 75, the circuit layer is embedded in the first insulating layer 22, and the first solder mask layer 72 and the second solder mask layer 75 respectively cover two opposite surfaces of the first insulating layer 22 and also cover two opposite surfaces of the circuit layer. The circuit layer comprises a thin copper area I and a thick copper area II, and the thickness of the circuit layer located in the thin copper area I is smaller than that of the circuit layer located in the thick copper area II.

In some embodiments, the first insulating layer 22 is formed by converting the first shielding layer 20 of a photosensitive type under light conditions.

The distance d between the thin copper area I and the thick copper area II is less than 50 mu m.

According to the manufacturing method of the circuit layer 100, the first circuit layer 50 is manufactured on the surface of the metal layer 10 in different areas through one-time selective patterning treatment, and the second circuit layer 60 is selectively formed on the surface of the first circuit layer 50, so that the circuit manufacturing of local thick copper is realized. The manufacturing method can be formed only by sequential pattern transfer, and deviation between formed circuit layers caused in multiple different pattern transfer processes is avoided; in addition, the manufacturing method has less etching times and is suitable for manufacturing high-precision circuits.

Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.

Claims

1. The manufacturing method of the circuit board is characterized by comprising the following steps of:

providing a metal layer, wherein the metal layer comprises a first surface;

removing the residual metal layer; and

2. The method of manufacturing a circuit board according to claim 1, wherein the metal layer further includes a second surface disposed opposite to the first surface; before the step of forming the first circuit layer on the first surface, the method further comprises the steps of laminating a second shielding layer on the second surface, and patterning the second shielding layer to form a second insulating layer.

3. The method of claim 2, wherein a thickness of the first shielding layer is greater than a thickness of the second shielding layer along a stacking direction of the first shielding layer, the metal layer, and the second shielding layer.

4. The method of manufacturing a circuit board according to claim 2, wherein before the step of forming the first wiring layer, the method of manufacturing further comprises: removing the unpatterned second shielding layer to expose part of the second surface; in the step of forming the first wiring layer, a copper plating layer is also formed on the exposed second surface.

5. The method for manufacturing a circuit board according to claim 4, further comprising removing the metal layer corresponding to the first sub-circuit before the step of forming the second circuit layer; in the step of forming the second circuit layer, the second sub-circuit is electroplated by passing a current through a metal layer corresponding to the second sub-circuit, so that the second circuit layer is formed on the surface of the second sub-circuit.

6. The method for manufacturing a circuit board according to claim 4, further comprising removing the metal layers corresponding to the first sub-circuit and the second sub-circuit before the step of forming the second circuit layer; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to electroplate the second sub-circuit to form the second circuit layer.

7. The method of claim 4, further comprising a step of removing the copper plating layer before the step of forming the second solder mask layer.

8. The method of manufacturing a circuit board according to claim 2, wherein before the step of forming the first wiring layer, the method of manufacturing further comprises: and covering an anti-plating film on the surface of the second insulating layer, which is far away from the metal layer, wherein the anti-plating film also covers the second shielding layer which is not patterned.

9. The method for manufacturing a circuit board according to claim 8, further comprising removing the plating resist and the metal layer corresponding to the first sub-circuit before the step of forming the second circuit layer; in the step of forming the second circuit layer, the second sub-circuit is electroplated by passing a current through a metal layer corresponding to the second sub-circuit, so that the second circuit layer is formed on the surface of the second sub-circuit.

10. The method for manufacturing a circuit board according to claim 8, further comprising removing the plating resist and the metal layer corresponding to the first sub-circuit before the step of forming the second circuit layer; in the step of forming the second circuit layer, a lead is connected to the second sub-circuit to perform electroplating on the second sub-circuit to form the second circuit layer.

11. A circuit board is characterized by comprising a first insulating layer, a circuit layer, a first solder mask layer and a second solder mask layer, wherein the circuit layer is embedded in the first insulating layer, and the first solder mask layer and the second solder mask layer respectively cover two opposite surfaces of the first insulating layer and also cover two opposite surfaces of the circuit layer; the circuit layer comprises a thin copper area and a thick copper area, and the thickness of the circuit layer located in the thin copper area is smaller than that of the circuit layer located in the thick copper area.