CN115086440A - Method and system for mutual conversion of Ethernet data same-group data and secondary group data - Google Patents
Method and system for mutual conversion of Ethernet data same-group data and secondary group data Download PDFInfo
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Abstract
The invention discloses a method and a system for simultaneously transmitting Ethernet data and base group data and mutually converting the Ethernet data and the base group data with secondary group data, wherein the method comprises the steps that a sending end extracts a first synchronous frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, the base group data is subjected to HDB3 decoding, and the synchronous data, the HDLC data after the Ethernet data packet is subjected to HDLC encoding and the decoded base group data are multiplexed according to a frame structure and then encoded and output; and the receiving end extracts a second same-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, taps according to the frame structure, outputs the tapped base group data after being coded by HDB3, and outputs the tapped Ethernet data according to a standard format after being decoded by HDLC. The invention is realized in FGPA chip, has low requirement to peripheral circuit, simple principle and strong practical value.
Description
Technical Field
The invention relates to the technical field of information transmission, in particular to a method and a system for simultaneously transmitting Ethernet data and primary group data and mutually converting the Ethernet data and secondary group data.
Background
Ethernet is the most widely used local area network transmission method at present, and the technology is quite mature. Ethernet has the advantages of low cost, simple network management, easy upgrade, etc. as the preferred solution of broadband access, but has the disadvantage of limited transmission distance. In the face of the abundant E1 (base group, rate is 2048kb/s) and E2 (secondary group, rate is 8448kb/s) interface resources provided by a large number of communication devices such as SDH and PDH, a relatively realistic scheme is to use the existing resources to transmit ethernet data. The existing E1/ethernet protocol converter is based on the transmission capability of the whole E1 when converting data.
The E1, E2 interfaces and the Ethernet interface are used as universal interfaces, the base group data and the Ethernet data are transmitted together and are converted into secondary group data, expansion, compatibility and the like of different services can be facilitated, and the performance of equipment can be greatly improved.
Therefore, it is an urgent need to solve the problem of the art to provide a method and system for simultaneously transmitting ethernet data and primary group data and mutually converting the ethernet data and the secondary group data.
Disclosure of Invention
In view of this, the invention provides a method and a system for simultaneously transmitting Ethernet data and base group data and mutually converting the Ethernet data and the secondary group data.
In order to achieve the purpose, the invention adopts the following technical scheme:
the method for simultaneously transmitting the Ethernet data and the primary group data and mutually converting the Ethernet data and the secondary group data comprises the following steps:
step 1: the transmitting end extracts a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, HDB3 decoding is carried out on the base group data based on the first decoding clock, and the HDLC data obtained after HDLC encoding is carried out on the synchronous data, the Ethernet data packet and the base group data obtained after HDB3 decoding are multiplexed according to a frame structure and then encoded and output, and the primary group data, the first decoding clock, the multiplexing clock and the first encoding clock are converted into secondary group data;
step 2: and the receiving end extracts a second same-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, taps according to the frame structure, outputs the tapped base group data after being coded by HDB3, and outputs the tapped Ethernet data according to a standard format after being decoded by HDLC.
Preferably, step 1 specifically comprises:
step 11: extracting a first synchronous clock, a first decoding clock, a multiplexing clock and a first coding clock which are synchronous from the base group data, and obtaining data multiplexing enabling according to a frame structure, wherein the data multiplexing enabling comprises synchronous data multiplexing enabling, base group data multiplexing enabling, Ethernet data multiplexing enabling and HDLC data multiplexing enabling;
step 12: the HDB3 decoding is carried out on the base group data based on the extracted first decoding clock, and the HDB3 decoded base group data are stored in an E1 FIFO receiving module based on the first common frequency clock;
step 13: storing effective Ethernet data packets into an MII FIFO receiving module through an associated clock of the Ethernet, reading the Ethernet data packets from the MII FIFO receiving module according to a multiplexing clock when the multiplexing enabling of the Ethernet data is effective, and converting the Ethernet data packets into HDLC data;
step 14: reading out decoded base group data from an E1 FIFO module based on a multiplexing clock when the multiplexing enabling of the base group data is effective, reading synchronous data from a synchronous code ROM based on the multiplexing clock when the multiplexing enabling of the synchronous data is effective, reading HDLC data from an HDLC framing module based on the multiplexing clock when the multiplexing enabling of the HDLC data is effective, multiplexing and converting the synchronous data, the decoded base group data and the HDLC data into continuous streams according to corresponding frame structures, carrying out HDB3 coding on the continuous stream data based on a first coding clock, and then sending the continuous stream data to a port, namely, becoming secondary group data.
Preferably, step 2 specifically comprises:
step 21: extracting a synchronous second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from continuous secondary group data;
step 22: after the secondary group data are decoded based on a second decoding clock, extracting group data, Ethernet data and data tapping enable from the secondary group data according to a corresponding frame structure, wherein the data tapping enable comprises the Ethernet data tapping enable and the group data tapping enable, and when the group data tapping enable is effective, the group data are stored into an E1 FIFO module based on a second same-frequency clock;
step 23: reading data in the E1 FIFO module based on the tapping clock, and then carrying out HDB3 coding based on a second coding clock, thereby restoring the data of the base group;
step 24: and when the Ethernet data tapping is enabled to be effective, the Ethernet data is subjected to HDLC deframing, an effective Ethernet data packet is extracted and stored in the MII FIFO module, and the Ethernet data packet is read out through the Ethernet clock and is sent to the port according to the standard format.
Preferably, the first common frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock are extracted from the base group data in a cascade phase locking manner.
Preferably, the second co-frequency clock, the second decoding clock, the tapping clock and the second encoding clock are extracted from the secondary group data in a cascade phase-locking manner.
The system for simultaneously transmitting the Ethernet data and the primary group data and mutually converting the Ethernet data and the secondary group data comprises: converting the primary group data and the Ethernet data into a secondary group data unit and converting the secondary group data into the primary group data and the Ethernet data unit;
converting the primary group data and the Ethernet data into a secondary group data unit: the HDLC data processing device is used for extracting a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, carrying out HDB3 decoding on the base group data based on the first decoding clock, multiplexing the synchronous data, the HDLC data subjected to the HDLC encoding of the Ethernet data packet and the base group data subjected to the HDB3 decoding according to a frame structure, then carrying out encoding output, and converting the multiplexed data into secondary group data;
secondary group data to base group data and ethernet data unit: and extracting a second same-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, tapping according to the frame structure, outputting the tapped base group data after being coded by HDB3, and outputting the tapped Ethernet data according to a standard format after being decoded by HDLC.
Preferably, the unit for converting the primary group data and the ethernet data into the secondary group data includes: the device comprises a first clock level interlocking phase module, a first HDB3 decoding module, an E1 FIFO receiving module, an MII FIFO receiving module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module;
the first clock cascade phase-locking module is used for extracting a first synchronous frequency clock, a first decoding clock, a multiplexing clock and a first coding clock which are synchronous from the base group data and obtaining data multiplexing enabling according to a frame structure, wherein the data multiplexing enabling comprises synchronous data multiplexing enabling, base group data multiplexing enabling, Ethernet data multiplexing enabling and HDLC data multiplexing enabling;
the first HDB3 decoding module is used for carrying out HDB3 decoding on the base group data based on the extracted first decoding clock and storing the base group data subjected to HDB3 decoding into the E1 FIFO receiving module based on the first common frequency clock;
the MII FIFO receiving module is used for storing effective Ethernet data packets detected by the Ethernet associated clock;
the HDLC framing module is used for reading an Ethernet data packet from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enabling is effective, and converting the Ethernet data packet into HDLC data;
the multiplexing module is used for reading out the decoded base group data from the E1 FIFO module based on the multiplexing clock when the multiplexing enabling of the base group data is effective, reading the synchronous data from the synchronous code ROM based on the multiplexing clock when the multiplexing enabling of the synchronous data is effective, reading the HDLC data from the HDLC framing module based on the multiplexing clock when the multiplexing enabling of the HDLC data is effective, and multiplexing and converting the synchronous data, the decoded base group data and the HDLC data into a continuous stream according to a corresponding frame structure;
the first HDB3 encoding module is used for carrying out HDB3 encoding on continuous stream data based on a first encoding clock and then sending the encoded continuous stream data to a port to be converted into secondary group data.
Preferably, the secondary group data-to-base group data and ethernet data unit comprises a second clock cascade phase-locking module, a second HDB3 decoding module, an E1 FIFO module, an MII FIFO module, an HDLC deframing module, a tapping module and a second HDB3 encoding module;
the second clock cascade phase-locking module is used for extracting a second synchronous frequency clock, a second decoding clock, a tapping clock and a second encoding clock from continuous secondary group data;
the second HDB3 decoding module is used for decoding the secondary group data based on a second decoding clock;
the tapping module is used for extracting the primary group data, the Ethernet data and the data tapping enabling from the secondary group data according to the corresponding frame structure, and the data tapping enabling comprises the Ethernet data tapping enabling and the primary group data tapping enabling;
the E1 FIFO module is used for reading and storing the group data based on the second same frequency clock when the group data tapping is enabled to be effective;
the second HDB3 coding module is used for reading data in the E1 FIFO module based on the tapping clock and then carrying out HDB3 coding based on the second coding clock so as to restore the base group data;
the HDLC de-framing module is used for performing HDLC de-framing on the Ethernet data when the Ethernet data tapping is enabled to be effective, and extracting an effective Ethernet data packet;
the MII sending FIFO module is used for storing effective Ethernet data packets, reading the Ethernet data packets through the Ethernet clock, and sending the Ethernet data packets to the port according to the standard format.
Preferably, the first clock-level interlocking phase module extracts the first common-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock from the base group data in a cascade phase-locking manner.
Preferably, the second clock cascade phase-locking module extracts the second same-frequency clock, the second decoding clock, the tapping clock and the second encoding clock from the secondary group data in a cascade phase-locking manner.
Through the technical scheme, compared with the prior art, the invention discloses the method and the system for simultaneously transmitting the Ethernet data and the primary group data and mutually converting the Ethernet data and the secondary group data, wherein the primary group data and the Ethernet data are transmitted together and converted into the secondary group data, so that the expansion, the compatibility and the like of different services are facilitated, and the equipment performance is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for simultaneously transmitting ethernet data and primary group data and mutually converting the ethernet data and the secondary group data according to the present invention.
Fig. 2 is a schematic block diagram of a system for simultaneously transmitting ethernet data and primary group data and mutually converting the ethernet data and the secondary group data according to the present invention.
Fig. 3 is a schematic block diagram of a cascaded phase lock according to the present invention.
Fig. 4 is a schematic diagram of the xor phase detection provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a method for simultaneously transmitting Ethernet data and base group data and mutually converting the Ethernet data and secondary group data, which is realized in an FPGA chip and comprises the following steps of:
step 1: the transmitting end extracts a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, decodes the base group data based on the first decoding clock, multiplexes the base group data after the synchronous data and the Ethernet data packet are subjected to HDLC encoding and HDB3 decoding according to a frame structure, then encodes and outputs the base group data, and converts the base group data into secondary group data; the method specifically comprises the following steps:
step 11: the base group data received by the FPGA are two differential HDB3 data, and in order to have sufficient phase discrimination information, the two data are combined and then subjected to clock cascade phase locking as shown in fig. 3 to obtain a first synchronous clock 2048kHz, a first decoding clock 4096kHz, a multiple connection clock 8448kHz and a first encoding clock 16896 kHz. As shown in fig. 4, the exclusive-or phase detection method is adopted, the accumulator bit width is 32 bits, the loop gain is 100ppm, the frequency words are calculated to be 0X01E81081 and 0X0FBA8826, and the loop gains are calculated to be 0X00000C7E and 0X00006714, respectively.
Step 12: the received two paths of differential HDB3 data are decoded by a first decoding clock 2048kHz and stored into an E1 FIFO receiving module based on a first synchronous frequency clock, wherein the FIFO width is 1 bit, and the FIFO depth is 256.
Step 13: ethernet data received by the FPGA receives an Ethernet packet through a channel associated clock, a lead code (7 0X55 and one 0X5D) of the Ethernet packet is removed, the Ethernet packet is converted into 32-bit parallel data and stored into an MII FIFO receiving module, meanwhile, CRC (cyclic redundancy check) and the frame length are counted according to bytes, the frame length is stored into the head of the FIFO, and the stored data are valid only if the CRC passes. In order to facilitate processing of each ethernet packet into a FIFO individually, since ethernet data is bursty and has a high rate, in order to avoid that the ethernet data coming from behind flushes the front, the receive-side FIFO is 48, with a width of 32 bits and a depth of 512.
The synchronous data multiplexing enable, the base group data multiplexing enable and the Ethernet data multiplexing enable are generated according to the frame structure by using a multiplexing clock 8448 kHz.
The sync data multiplexing enable is used to read a 1-bit data framing from rom memory that holds fixed data 0X1D when it comes.
When the group data multiplexing is enabled, a multiplexing clock is used for reading data framing from the E1 receiving FIFO module.
When the Ethernet data multiplexing is enabled, whether the MII receiving FIFO is not empty is detected, and if the MII receiving FIFO is empty, the serial stream of the HDLC frame identifier 0X7E is sent all the time. If not, the data is read from the MII receive FIFO by the multiplexing clock and converted into a bit stream according to the HDLC protocol. The HDLC protocol specifies "01111110" (0X7E) as a frame identifier, but the transmitted data combination may be the same as the frame identifier, and in order to prevent the receiving end from misjudging as a frame header or a frame end, a "0" bit is automatically inserted between the frame header and the frame end of a frame every time after 5 consecutive "1" bits are transmitted, and the "0" does not perform CRC calculation. The length of Ethernet frame byte stored in the head of the FIFO is used for determining the length of data read from the FIFO and is not transmitted. According to the frame structure, the Ethernet data in one frame of data only occupies 99 bits, and one Ethernet data packet needs to be sent out by a plurality of frames. A 0X7E space is also required between two ethernet packets.
Step 14: the data rate after framing the synchronous data, the group data and the Ethernet data is 8448kbps, because the zero-return code is adopted, the 16896kHz clock is used for carrying out HDB3 coding, and two paths of coded data are sent to a port, namely the conversion of the group data and the Ethernet data into secondary group data is completed.
Step 2: the receiving end extracts a second common-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, taps according to the frame structure, outputs the tapped base group data after being coded by HDB3, and outputs the tapped Ethernet data according to a standard format after being decoded by HDLC, specifically:
step 21: the secondary group data received by the FPGA are two differential HDB3 data, and in order to have sufficient phase discrimination information, the two data are combined and then subjected to clock cascade phase locking as shown in fig. 3 to obtain a second co-frequency clock 8448kHz, a second decoding clock 16896kHz, a tapping clock 2048kHz and a second encoding clock 4096 kHz. As shown in fig. 4, the exclusive-or phase discrimination method is adopted, the bit width of the accumulator is 32 bits, the loop gain is 100ppm, the frequency words are calculated to be 0X07DD4413 and 0X03D02102 respectively, and the loop gains are 0X0000338A and 0X000018FD respectively.
Step 22: and decoding the received HDB3 data by using a second decoding clock 16896kHz, carrying out frame synchronization on the decoded data, and tapping out the basic group data, the Ethernet data and the corresponding data enable according to a frame structure, wherein the data enable comprises the Ethernet data tapping enable and the basic group data tapping enable.
Step 23: when the group data tap is enabled, data is stored into an E1 FIFO with a width of 1 bit and a depth of 256 using an 8448kHz clock. The data are continuously read from the FIFO transmitted by the E1 by a 2048kHz clock, the data become continuous streams, because of adopting the return-to-zero code, the HDB3 coding is carried out by a 4096kHz clock, and the two paths of coded data are returned to zero and then sent to the port, thereby restoring the base group data.
Step 24: when the Ethernet data tapping enables to be effective, the Ethernet data is subjected to HDLC deframing by an 8448kHz clock, effective Ethernet data packets are extracted and stored in an MII transmission FIFO module, each Ethernet data packet is independently stored in one FIFO, and in order to avoid data loss, the number of the transmission FIFOs is 4, the width is 32 bits, and the depth is 512. And reading the data by using the Ethernet clock, adding a lead code, and sending the lead code to a port according to a standard format, thereby restoring the Ethernet data.
The above is a specific implementation manner of the invention, which is implemented in the FGPA chip, and has low requirement on peripheral circuits, simple principle and strong practical value.
The embodiment of the invention discloses a system for simultaneously transmitting Ethernet data and primary group data and mutually converting the Ethernet data and the secondary group data, as shown in figure 2, comprising: converting the primary group data and the Ethernet data into a secondary group data unit and converting the secondary group data into the primary group data and the Ethernet data unit;
converting the primary group data and the Ethernet data into a secondary group data unit: the HDLC data processing device is used for extracting a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, carrying out HDB3 decoding on the base group data based on the first decoding clock, multiplexing the synchronous data, the HDLC data subjected to the HDLC encoding of the Ethernet data packet and the base group data subjected to the HDB3 decoding according to a frame structure, then carrying out encoding output, and converting the multiplexed data into secondary group data;
secondary group data to base group data and ethernet data unit: and extracting a second common-frequency clock, a second decoding clock, a tapping clock and a second encoding clock according to the secondary group data, tapping according to a frame structure, outputting the tapped base group data after being encoded by HDB3, and outputting the tapped Ethernet data according to a standard format after being decoded by HDLC.
The unit for converting the primary group data and the Ethernet data into the secondary group data comprises: the device comprises a first clock level interlocking phase module, a first HDB3 decoding module, an E1 FIFO receiving module, an MII FIFO receiving module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module;
the first clock cascade phase-locking module is used for extracting a first synchronous frequency clock, a first decoding clock, a multiplexing clock and a first coding clock which are synchronous from the base group data and obtaining data multiplexing enabling according to a frame structure, wherein the data multiplexing enabling comprises synchronous data multiplexing enabling, base group data multiplexing enabling, Ethernet data multiplexing enabling and HDLC data multiplexing enabling;
the first HDB3 decoding module is used for carrying out HDB3 decoding on the base group data based on the extracted first decoding clock and storing the base group data subjected to HDB3 decoding into the E1 FIFO receiving module based on the first common frequency clock;
the MII FIFO receiving module is used for storing effective Ethernet data packets detected by the Ethernet associated clock;
the HDLC framing module is used for reading an Ethernet data packet from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enabling is effective, and converting the Ethernet data packet into HDLC data;
the multiplexing module is used for reading out the decoded base group data from the E1 FIFO module based on the multiplexing clock when the multiplexing enabling of the base group data is effective, reading the synchronous data from the synchronous code ROM based on the multiplexing clock when the multiplexing enabling of the synchronous data is effective, reading the HDLC data from the HDLC framing module based on the multiplexing clock when the multiplexing enabling of the HDLC data is effective, and multiplexing and converting the synchronous data, the decoded base group data and the HDLC data into a continuous stream according to the corresponding frame structure;
the first HDB3 encoding module is used for carrying out HDB3 encoding on continuous stream data based on a first encoding clock and then sending the encoded continuous stream data to a port to be converted into secondary group data. The secondary group data-to-base group data and Ethernet data unit comprises a second clock cascade phase locking module, a second HDB3 decoding module, an E1 FIFO module, an MII FIFO module, an HDLC frame decoding module, a tapping module and a second HDB3 coding module;
the second clock cascade phase-locking module is used for extracting a second synchronous frequency clock, a second decoding clock, a tapping clock and a second encoding clock from continuous secondary group data;
the second HDB3 decoding module is used for decoding the secondary group data based on a second decoding clock;
the tapping module is used for extracting the primary group data, the Ethernet data and the data tapping enabling from the secondary group data according to the corresponding frame structure, and the data tapping enabling comprises the Ethernet data tapping enabling and the primary group data tapping enabling;
the E1 FIFO module is used for reading and storing the group data based on the second co-frequency clock when the group data tapping is enabled to be effective;
the second HDB3 coding module is used for reading data in the E1 FIFO module based on the tapping clock and then carrying out HDB3 coding based on the second coding clock so as to restore the base group data;
the HDLC de-framing module is used for performing HDLC de-framing on the Ethernet data when the Ethernet data tapping is enabled to be effective, and extracting an effective Ethernet data packet;
the MII sending FIFO module is used for storing effective Ethernet data packets, reading the Ethernet data packets through the Ethernet clock, and sending the Ethernet data packets to the port according to the standard format.
In the HDB3 coding/decoding module, the HDB3 code is an improved version of AMI code, and eliminates the status of connecting 0. The coding principle can be briefly stated as that when the number of the continuous '0' in the original code exceeds 3, the 4 th '0' code is replaced by a damaged pulse code V code, the polarity of the V code is the same as that of the previous non-0 'code, the adjacent V codes need to be ensured to be alternated in polarity, when the number of the non-0' codes between the two adjacent V codes is an even number, the first '0' code behind the previous non-0 'code of the current V code is changed into a B code, and the polarity of the B code is opposite to that of the previous non-0' code. The HDB3 encodes the return-to-zero output.
The first clock-level interlocking phase module and the second clock-level cascading phase-locking module have the same principle, as shown in fig. 3, a plurality of cascading clocks are generated through one phase-locked loop, fixed frequency words and gain K0 of the plurality of regenerative clocks are respectively calculated, and phase accumulation of the plurality of regenerative clocks is controlled in the same manner according to phase detection output.
And the HDLC framing and unframing module is used for converting the HDLC into bit streams according to an HDLC protocol during framing. The HDLC protocol specifies that a complete frame message starts with a flag word and ends with the flag word, 01111110(0X7E) as the flag word, but the transmitted data combination may be the same as the flag word, and in order to prevent the receiving end from misjudging as the frame head or frame end, a "0" bit is automatically inserted between the frame head and frame end of a frame every time after 5 consecutive "1" bits are transmitted, and this "O" does not perform the CRC calculation. When the frame is deframed, after the frame header is received, every time 5 '1' bits are continuously received, one '0' bit is automatically deleted so as to restore the original form of the information.
And the multiplexing and tapping module is used for multiplexing and tapping according to the frame structure, synchronous data in each frame occupy 1 bit, and after the synchronous data rate is determined, the bit number of the base group data and the Ethernet data in one frame of data can be determined, so that the frame structure is determined. And determining a proper frame structure, framing and unframing the synchronous data, the base group data and the Ethernet data according to the frame structure, wherein the frame structure is 1S +32E +99IP, S represents a frame synchronization sequence, E represents the base group data, and IP represents the Ethernet data.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The method for simultaneously transmitting the Ethernet data and the primary group data and mutually converting the Ethernet data and the secondary group data is characterized by comprising the following steps of:
step 1: the transmitting end extracts a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, HDB3 decoding is carried out on the base group data based on the first decoding clock, and the HDLC data obtained after HDLC encoding is carried out on the synchronous data, the Ethernet data packet and the base group data obtained after HDB3 decoding are multiplexed according to a frame structure and then encoded and output, and the primary group data, the first decoding clock, the multiplexing clock and the first encoding clock are converted into secondary group data;
step 2: and the receiving end extracts a second common-frequency clock, a second decoding clock, a tapping clock and a second encoding clock according to the secondary group data, taps according to a frame structure, outputs the tapped base group data after being encoded by HDB3, and outputs the tapped Ethernet data according to a standard format after being decoded by HDLC.
2. The method for simultaneously transmitting the ethernet data and the primary group data and mutually converting the ethernet data and the secondary group data according to claim 1, wherein the step 1 specifically comprises:
step 11: extracting a first synchronous clock, a first decoding clock, a multiplexing clock and a first coding clock which are synchronous from the base group data, and obtaining data multiplexing enabling according to a frame structure, wherein the data multiplexing enabling comprises synchronous data multiplexing enabling, base group data multiplexing enabling, Ethernet data multiplexing enabling and HDLC data multiplexing enabling;
step 12: the HDB3 decoding is carried out on the base group data based on the extracted first decoding clock, and the HDB3 decoded base group data are stored in an E1 FIFO receiving module based on the first common frequency clock;
step 13: storing effective Ethernet data packets into an MII FIFO receiving module through an associated clock of the Ethernet, reading the Ethernet data packets from the MII FIFO receiving module according to a multiplexing clock when the multiplexing enabling of the Ethernet data is effective, and converting the Ethernet data packets into HDLC data;
step 14: reading out decoded base group data from an E1 FIFO module based on a multiplexing clock when the multiplexing enabling of the base group data is effective, reading synchronous data from a synchronous code ROM based on the multiplexing clock when the multiplexing enabling of the synchronous data is effective, reading HDLC data from an HDLC framing module based on the multiplexing clock when the multiplexing enabling of the HDLC data is effective, multiplexing and converting the synchronous data, the decoded base group data and the HDLC data into continuous streams according to corresponding frame structures, carrying out HDB3 coding on the continuous stream data based on a first coding clock, and then sending the continuous stream data to a port, namely, becoming secondary group data.
3. The method for simultaneously transmitting ethernet data and primary group data and mutually converting secondary group data according to claim 2, wherein step 2 specifically comprises:
step 21: extracting a synchronous second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from continuous secondary group data;
step 22: after the secondary group data are decoded based on a second decoding clock, extracting group data, Ethernet data and data tapping enable from the secondary group data according to a corresponding frame structure, wherein the data tapping enable comprises the Ethernet data tapping enable and the group data tapping enable, and when the group data tapping enable is effective, the group data are stored into an E1 FIFO module based on a second same-frequency clock;
step 23: reading data in the E1 FIFO module based on the tapping clock, and then carrying out HDB3 coding based on a second coding clock, thereby restoring the data of the base group;
step 24: and when the Ethernet data tapping is enabled to be effective, the Ethernet data is subjected to HDLC deframing, an effective Ethernet data packet is extracted and stored in the MII FIFO module, and the Ethernet data packet is read out through the Ethernet clock and is sent to the port according to the standard format.
4. The method of claim 2, wherein the first clock, the first decode clock, the multiplexing clock, and the first encode clock are extracted from the base group data by cascaded phase-locking.
5. The method according to claim 3, wherein the second co-frequency clock, the second decoding clock, the tap clock and the second encoding clock are extracted from the secondary group data by a cascaded phase-locked method.
6. The system that ethernet data and basic group data were passed with each other and were interconverted with secondary group data, its characterized in that includes: converting the primary group data and the Ethernet data into a secondary group data unit and converting the secondary group data into the primary group data and the Ethernet data unit;
converting the primary group data and the Ethernet data into a secondary group data unit: the HDLC data processing device is used for extracting a first common frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock according to the base group data, carrying out HDB3 decoding on the base group data based on the first decoding clock, multiplexing the synchronous data, the HDLC data subjected to the HDLC encoding of the Ethernet data packet and the base group data subjected to the HDB3 decoding according to a frame structure, then carrying out encoding output, and converting the multiplexed data into secondary group data;
secondary group data to base group data and ethernet data unit: and extracting a second same-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, tapping according to the frame structure, outputting the tapped base group data after being coded by HDB3, and outputting the tapped Ethernet data according to a standard format after being decoded by HDLC.
7. The system of claim 6, wherein the unit for converting the primary group data and the ethernet data into the secondary group data comprises: the device comprises a first clock level interlocking phase module, a first HDB3 decoding module, an E1 FIFO receiving module, an MII FIFO receiving module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module;
the first clock cascade phase-locking module is used for extracting a first synchronous frequency clock, a first decoding clock, a multiplexing clock and a first coding clock which are synchronous from the base group data and obtaining data multiplexing enabling according to a frame structure, wherein the data multiplexing enabling comprises synchronous data multiplexing enabling, base group data multiplexing enabling, Ethernet data multiplexing enabling and HDLC data multiplexing enabling;
the first HDB3 decoding module is used for carrying out HDB3 decoding on the group data based on the extracted first decoding clock, and storing the group data after being decoded by the HDB3 into the E1 FIFO receiving module based on the first synchronous clock;
the MII FIFO receiving module is used for storing effective Ethernet data packets detected by the Ethernet associated clock;
the HDLC framing module is used for reading an Ethernet data packet from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enabling is effective, and converting the Ethernet data packet into HDLC data;
the multiplexing module is used for reading out the decoded base group data from the E1 FIFO module based on the multiplexing clock when the multiplexing enabling of the base group data is effective, reading the synchronous data from the synchronous code ROM based on the multiplexing clock when the multiplexing enabling of the synchronous data is effective, reading the HDLC data from the HDLC framing module based on the multiplexing clock when the multiplexing enabling of the HDLC data is effective, and multiplexing and converting the synchronous data, the decoded base group data and the HDLC data into a continuous stream according to the corresponding frame structure;
the first HDB3 encoding module is used for carrying out HDB3 encoding on continuous stream data based on a first encoding clock and then sending the encoded continuous stream data to a port to be converted into secondary group data.
8. The system of claim 7, wherein the secondary group data-to-group data and ethernet data unit comprises a second clock cascade phase-locking module, a second HDB3 decoding module, an E1 FIFO module, an MII FIFO module, an HDLC de-framing module, a tapping module, and a second HDB3 encoding module;
the second clock cascade phase-locking module is used for extracting a second synchronous frequency clock, a second decoding clock, a tapping clock and a second encoding clock from continuous secondary group data;
the second HDB3 decoding module is used for decoding the secondary group data based on a second decoding clock;
the tapping module is used for extracting the primary group data, the Ethernet data and the data tapping enabling from the secondary group data according to the corresponding frame structure, and the data tapping enabling comprises the Ethernet data tapping enabling and the primary group data tapping enabling;
the E1 FIFO module is used for reading and storing the group data based on the second same frequency clock when the group data tapping is enabled to be effective;
the second HDB3 coding module is used for reading data in the E1 FIFO module based on the tapping clock and then carrying out HDB3 coding based on the second coding clock so as to restore the base group data;
the HDLC de-framing module is used for performing HDLC de-framing on the Ethernet data when the Ethernet data tapping is enabled to be effective, and extracting an effective Ethernet data packet;
the MII sending FIFO module is used for storing effective Ethernet data packets, reading the Ethernet data packets through the Ethernet clock, and sending the Ethernet data packets to the port according to the standard format.
9. The system according to claim 6, wherein the first clock-level interlocking phase module extracts the first on-frequency clock, the first decoding clock, the multiplexing clock, and the first encoding clock from the base group data by means of cascaded phase-locking.
10. The system according to claim 8, wherein the second clock cascade phase-locking module extracts a second co-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the secondary group data by means of cascade phase-locking.
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