CN115086117A - Decision feedback method and decision feedback equalizer - Google Patents
Decision feedback method and decision feedback equalizer Download PDFInfo
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Abstract
The invention discloses a decision feedback method and a decision feedback equalizer, wherein the method comprises the following steps: acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, wherein N is more than or equal to 2; judging the voltage input signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two voltage signals with opposite polarities; when N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals; when N is an odd number, acquiring a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal; outputting each two paths of voltage feedback signals to the same feedback branch, and converting the voltage feedback signals into corresponding current feedback signals through the feedback branch; and compensating the current input signal according to the current feedback signal so as to reduce intersymbol interference of the voltage input signal.
Description
Technical Field
The present invention relates to the field of communication circuit technologies, and in particular, to a decision feedback method and a decision feedback equalizer.
Background
When high-speed serial data is transmitted, due to the influence of non-ideal factors such as skin effect and dielectric loss, high-frequency components of signals are seriously attenuated, so that code elements are distorted, and interference, namely intersymbol interference (ISI), is generated on code element judgment. The faster the data transmission rate, the more significant the impact of ISI. The link needs equalization to overcome channel ISI and to allow recovery of the data at the receiving end with low bit error rate. Although a Continuous Time Linear Equalizer (CTLE) can be used to compensate for the high frequency loss of the channel, it can amplify the high frequency signal and also amplify the noise to reduce the signal-to-noise ratio, and cannot compensate for the gap of the channel frequency response caused by impedance discontinuity. To be able to better eliminate ISI, further equalization with a Decision Feedback Equalizer (DFE) is needed to compensate.
As the data transmission rate is faster and faster, the influence of parasitic parameters of the feedback current branch of the decision feedback equalizer is larger and larger. In order to satisfy the time constraint of the decision feedback equalizer at a high rate, the structure of the existing decision feedback equalizer needs to be optimized to have smaller parasitic parameters, so that the structure of the existing decision feedback equalizer has higher competitiveness at a higher rate than that of the existing decision feedback equalizer.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a decision feedback method and a decision feedback equalizer are provided to solve the problem of how to better reduce circuit parasitic parameters to alleviate clock constraints of the decision feedback equalizer.
In order to solve the technical problems, the invention adopts the technical scheme that:
a decision feedback method comprising the steps of:
acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, wherein N is more than or equal to 2;
judging the voltage input signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two paths of voltage signals with opposite polarities;
when N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals;
when N is an odd number, acquiring a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal;
outputting each two paths of voltage feedback signals to the same feedback branch, and converting the voltage feedback signals into corresponding current feedback signals through the feedback branch;
and compensating the current input signal according to the current feedback signal so as to reduce intersymbol interference of the voltage input signal.
Further, when N is an even number, a first feedback branch and a second feedback branch are provided;
the first feedback branch circuit receives voltage signals in two paths of different paired signals respectively, and the output current of an input current source of the first feedback branch circuit is 2I;
the second feedback branch receives two voltage signals in the same paired signal, and the output current of the input current source of the second feedback branch is I.
Further, when N is an odd number, a third feedback branch is provided, the third feedback branch receives voltage signals in two different paired signals, and the output current of the input current source of the third feedback branch is 2I.
Further, when N is equal to 4, obtaining a first pair signal, a second pair signal and a third pair signal;
obtaining a voltage signal of one polarity from the first paired signals and the second paired signals respectively and outputting the voltage signal to a first feedback branch circuit, and obtaining a voltage signal of the other polarity respectively and outputting the voltage signal to a decoding circuit;
and two paths of voltage signals are obtained from the third pair of signals and output to a second feedback branch, and one polarity of voltage signal is taken and output to a decoding circuit.
Further, N is equal to 5, and a first paired signal, a second paired signal, a third paired signal and a fourth paired signal are obtained;
obtaining a voltage signal of one polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to one of the third feedback branches, and obtaining a voltage signal of the other polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to a decoding circuit;
and voltage signals respectively acquiring one polarity from the third pair of signals and the fourth pair of signals are output to the other third feedback branch, and voltage signals respectively acquiring the other polarity are output to a decoding circuit.
A decision feedback equalizer comprising: the adding module and the slicing module are electrically connected with each other;
the addition module is used for acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, converting a voltage feedback signal output by the slicing module into a current feedback signal through an internal feedback branch circuit, and compensating the current input signal to generate a voltage output signal, wherein N is greater than or equal to 2;
the slicing module is used for acquiring the voltage output signals and comparing and converting the voltage output signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two paths of voltage signals with opposite polarities;
when N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals;
when N is an odd number, acquiring a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal;
and each two paths of voltage feedback signals are output to the same feedback branch and are switched into corresponding current feedback signals through the feedback branch.
Further, the slicing module includes N-1 slicing units, each for outputting a pair of paired signals.
Further, the adding module comprises:
a signal input unit and at least one feedback unit;
the signal input unit is electrically connected with the slicing module and is used for receiving a voltage input signal, converting the voltage input signal into a corresponding current input signal, generating a voltage output signal according to the compensated current input signal and outputting the voltage output signal to the slicing module;
the feedback unit is respectively electrically connected with the signal input unit and the slicing module, and is used for receiving a voltage feedback signal output by the slicing module, converting the voltage feedback signal into a current feedback signal, and compensating the current input signal according to the current feedback signal.
Further, the signal input unit includes: the circuit comprises a first current source, a first transistor, a second transistor, a first resistor and a second resistor;
the first current source is respectively connected with a source electrode of the first transistor and a source electrode of the second transistor, a grid electrode of the first transistor and a grid electrode of the second transistor are connected with the voltage input signal, a drain electrode of the first transistor is respectively connected with an input end of the slicing module and one end of the first resistor, a drain electrode of the second transistor is respectively connected with an input end of the slicing module and one end of the second resistor, and the other end of the first resistor and the other end of the second resistor are both grounded.
Further, the feedback unit includes: a second current source, a third transistor, and a fourth transistor;
the second current source is connected to a source of the third transistor and a source of the fourth transistor, a gate of the third transistor and a gate of the fourth transistor are both connected to an output terminal of the slice module, a drain of the third transistor is connected to a drain of the first transistor and an input terminal of the slice module, and a drain of the fourth transistor is connected to a drain of the second transistor and an input terminal of the slice module.
The invention has the beneficial effects that: by acquiring N-1 pairs of paired signals, when N is an even number, respectively taking a voltage signal with one polarity from N-2 pairs of paired signals, and taking two voltage signals of the remaining pair of signals as feedback signals; when N is an odd number, respectively taking one polarity voltage signal from the N-1 pairs of signals as a feedback signal; each two feedback signals act on the same feedback branch, so that the number of the feedback branches is reduced to N/2 or (N-1)/2, and when N is an even number, the number of the feedback signals is reduced to N; when N is an odd number, the number of feedback signals is reduced to N-1. The circuit structure is simplified, the parasitic parameter of the circuit is reduced, the clock constraint of the decision feedback equalizer is relieved, and the circuit is suitable for input signals of various coding types.
Drawings
FIG. 1 is a circuit schematic of a prior art decision feedback equalizer;
FIG. 2 is an eye diagram and reference voltages for the decision feedback equalizer of FIG. 1;
FIG. 3 is a circuit schematic of another prior art decision feedback equalizer;
FIG. 4 is an eye diagram and reference voltage for the decision feedback equalizer of FIG. 3;
FIG. 5 is a block flow diagram of a decision feedback method in an embodiment of the present invention;
fig. 6 is a circuit schematic diagram of a first decision feedback equalizer according to an embodiment of the present invention;
FIG. 7 is an eye diagram and reference voltages for the decision feedback equalizer of FIG. 6;
fig. 8 is a circuit schematic of a second decision feedback equalizer of an embodiment of the present invention;
FIG. 9 is an eye diagram and reference voltages for the decision feedback equalizer of FIG. 8;
FIG. 10 is a circuit schematic of a third decision feedback equalizer of an embodiment of the present invention;
fig. 11 is a schematic diagram of a fourth decision feedback equalizer of an embodiment of the present invention;
fig. 12 is a functional block diagram of a decision feedback equalizer according to an embodiment of the present invention.
Description of reference numerals:
100. an addition module; 110. a signal input unit; 111. a first current source; 112. a first transistor; 113. a second transistor; 120. a feedback unit; 121. a second current source; 122. a third transistor; 123. a fourth transistor; 200. a slicing module; 210. a slicing unit; 300. a feedback branch; 400. a first feedback branch; 500. a second feedback branch; 600. and a third feedback branch.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, taking 1 tap as an example, a decision feedback equalizer in the prior art inputs 4-level pulse amplitude modulation signals, and outputs 3 pairs of paired signals through 3 slicers, which are total 6 voltage signals, including: comp _ Hp and Comp _ Hn, Comp _ Mp and Comp _ Mn, Comp _ Lp and Comp _ Ln, respectively, the 6 voltage signals are fed back to the 3 feedback branches 300, respectively, and the input current source of each feedback branch 300 is I. Referring to fig. 2, regarding the eye diagram and the voltage definitions of the decision feedback equalizer, the desired voltage values are D0, D1, D2, D3, respectively, and the reference voltages are VTH _ H, VTH _ M, VTH _ L, respectively. Illustratively, the voltage signals with two different polarities in any pair of paired signals are respectively represented by 1 and 0, specifically, the high level of the slicer output is represented by 1, and the low level of the slicer output is represented by 0.
Wherein the value of the voltage of D3 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln are 1, 0, respectively;
the value of the D2 voltage depends on the Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln fed back signals being 0, 1, 0, respectively;
the value of the voltage of D1 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, 0, respectively;
the value of the voltage D0 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, respectively.
Referring to fig. 3, taking 1 tap as an example, another decision feedback equalizer in the prior art inputs 5-level pulse amplitude modulation signals, outputs 4 pairs of paired signals through 4 slicers, and has 8 voltage signals, including: comp _ Hp and Comp _ Hn, Comp _ MHp and Comp _ MHn, Comp _ MLp and Comp _ MLn, Comp _ Lp and Comp _ Ln, respectively, the 8-way voltage signals are fed back to the 4 feedback branches 300, respectively, and the input current source of each feedback branch 300 is I. Referring to fig. 4, regarding the eye diagram and the voltage definitions of the decision feedback equalizer, the desired voltage values are D0, D1, D2, D3, and D4, respectively, and the reference voltages are VTH _ H, VTH _ MH, VTH _ ML, and VTH _ L, respectively.
Wherein the value of the voltage of D4 is 1, 0, 1, 0 depending on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln, respectively;
the value of the voltage of D3 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, 0, respectively;
the value of the voltage of D2 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, 0, respectively;
the value of the voltage of D1 depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, 0, respectively;
the value of the D0 voltage depends on the signals fed back by Comp _ Hp, Comp _ Hn, Comp _ Mp, Comp _ Mn, Comp _ Lp, Comp _ Ln being 0, 1, respectively.
It can be seen that the number of feedback signals and feedback branches needed in the prior art is large, and if decision feedback is performed on a voltage input signal modulated by N-level pulse amplitude, 2 × N (N-1) feedback signals and N-1 feedback branches are needed, so that the circuit is complex, parasitic parameters are large, and the clock constraint problem of the decision feedback equalization circuit is not easily relieved.
Example one
Referring to fig. 5 to 11, a first embodiment of the present invention is:
referring to fig. 5, a method for decision feedback includes the steps of:
s1, acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, wherein N is more than or equal to 2;
s2, judging the voltage input signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two paths of voltage signals with opposite polarities;
s3, when N is an even number, obtaining a voltage signal of one polarity from each of the N-2 pairs of paired signals and obtaining two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals;
s4, when N is an odd number, obtaining a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal;
s5, outputting each two paths of voltage feedback signals to the same feedback branch circuit, and converting the voltage feedback signals into corresponding current feedback signals through the feedback branch circuit;
and S6, compensating the current input signal according to the current feedback signal to reduce the intersymbol interference of the voltage input signal. In this step, the compensated current input signal is converted into a voltage output signal, and the voltage output signal is sliced or compared to generate a voltage feedback signal.
In this embodiment, the principle of the decision equalization feedback method is as follows: converting the voltage input signal of the N-level pulse amplitude modulation into a current input signal, and performing decision comparison on the voltage input signal to obtain N-1 pairs of paired signals containing two voltage signals with opposite polarities, and when N is an even number, respectively taking the voltage signal of one polarity from the N-2 pairs of paired signals and taking two voltage signals of the rest pair of signals as feedback signals; when N is an odd number, respectively taking a voltage signal with one polarity from the N-1 pairs of paired signals as a feedback signal; and each two feedback signals act on the same feedback branch; outputting each two paths of voltage feedback signals to the same feedback branch, and converting the voltage feedback signals into corresponding current feedback signals through the feedback branch; and compensating the current input signal according to the current feedback signal so as to reduce intersymbol interference of the voltage input signal.
It can be understood that the number of feedback branches is reduced to N/2 or (N-1)/2 by the above arrangement, and when N is an even number, the number of feedback signals is reduced to N; when N is an odd number, the number of feedback signals is reduced to N-1. The circuit structure is simplified, the parasitic parameter of the circuit is reduced, the clock constraint of the decision feedback equalizer is relieved, and the circuit is suitable for input signals of various coding types.
Specifically, when N is an even number, the first feedback branch 400 and the second feedback branch 500 are provided; the first feedback branch 400 receives voltage signals of two different pairs of signals, and an input current source of the first feedback branch 400 is 2I; the second feedback branch 500 receives two voltage signals of the same paired signal, and the output current of the input current source of the second feedback branch 500 is I. When N is an odd number, a third feedback branch 600 is provided, the third feedback branch 600 receives voltage signals of two different paired signals, and the output current of the input current source of the third feedback branch 600 is 2I.
Referring to fig. 7 and 9, in the present embodiment, when N is an even number, the desired voltage values are D (N-1), D (N-2),. gtang, D1, D0, and the reference voltages are VTH _ Hx, VTH _ H (x-1).. gth _ H1, VTH _ M, VTH _ L1,. gth _ L (x-1), and VTH _ Lx, respectively; when N is an odd number, the desired voltage values are D (N-1), D (N-2),.. gtoreq, D1, D0, respectively, and the reference voltages are VTH _ Hx, VTH _ H (x-1).. gth _ H1, VTH _ H0, VTH _ L0, VTH _ L1,. gth _ L (x-1), VTH _ Lx, respectively.
Referring to fig. 6, when N is an even number, taking 1 tap as an example, the decision feedback equalizer inputs N-level pwm signals, and outputs N-1 pairs of paired signals through N-1 slicers, which are 2 × N-1 voltage signals, including: comp _ Hxp and Comp _ Hxn, Comp _ Mp and Comp _ Mn, Comp _ Lxp and Comp _ Lxn. According to the decision feedback method in the embodiment, the decision feedback method specifically includes: the output signals are fed back by using VTH _ Hx and VTH _ Lx to determine whether the output signals are D (N-1) and D0 signals, and the current source of the current branch is 2I. Illustratively, if Comp _ Hxp outputs 1, then the signal is D (N-1); if Comp _ Lxn outputs 1, the signal is D0, and if neither case is satisfied, then D (N-1) and D0 are not satisfied, further looking at the other decision results. Judging whether the output signals are D (N-2) and D1 signals by using VTH _ H (x-1) and VTH _ L (x-1), and enabling the current source of the current branch circuit to be 2I; until the last pair of feedback signals Comp _ Mp and Comp _ Mn, whether the output signal is D (N/2) and D (N/2-1) is judged and fed back by VTH _ M, and the output current of the current source of the current branch is I.
Referring to fig. 8, when N is an odd number, taking 1 tap as an example, the decision feedback equalizer inputs N-level pwm signals, and outputs N-1 pairs of paired signals through N-1 slicers, which are 2 × N-1 voltage signals, including: comp _ Hxp and Comp _ Hxn,.., Comp _ MH0p and Comp _ MH0n, Comp _ ML0p and Comp _ ML0n,.., Comp _ Lxp and Comp _ Lxn. According to the decision feedback method in the embodiment, the decision feedback method specifically includes: judging whether the output signals are D (N-1) and D0 signals by using VTH _ Hx and VTH _ Lx, and enabling the current source of the current branch circuit to be 2I; judging whether the output signals are D (N-2) and D1 signals by using VTH _ H (x-1) and VTH _ L (x-1), and enabling the current source of the current branch circuit to be 2I; up to the last pair of feedback signals Comp _ MH0p and Comp _ ML0N, whether the output signal is a D ((N-3)/2), D ((N-1)/2), and D ((N +1)/2) signal is judged and fed back by VTH _ MH0 and VTH _ ML 0. Illustratively, if Comp _ MH0p is 1, then the signal is D ((N + 1)/2); if Comp _ ML0N is 1, then the signal is D ((N-3)/2); if Comp _ MH0p is 0 and Comp _ ML0N is 0 then the signal is D ((N-1)/2) and the output current magnitude of the current source of the current branch is 2I.
It can be understood that, if two feedback signals obtained in the feedback branch are respectively from different paired signals, the output current of the input current source of the feedback circuit is 2I; and if the two feedback signals obtained from the feedback branch circuits are both from the same pair of paired signals, the output current of the input current source of the feedback circuit is I.
Referring to fig. 10, when N is equal to 4, first pair signals Comp _ Hp and Comp _ Hn, second pair signals Comp _ Mp and Comp _ Mn, and third pair signals Comp _ Lp and Comp _ Ln are obtained; obtaining a voltage signal of one polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to the first feedback branch 400, and obtaining a voltage signal of the other polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to the decoding circuit; two paths of voltage signals are obtained from the third pair of signals and output to the second feedback branch 500, and one polarity of voltage signal is output to the decoding circuit. Specifically, the signals Comp _ Hp and Comp _ Ln are output to the first feedback branch 400, and the signals Comp _ Hn and Comp _ Lp are output to the decoding circuit; the signals Comp _ Mp and Comp _ Mn are output to the second feedback branch 500, and the signal Comp _ Mp or Comp _ Mn is output to the decoding circuit.
Referring to fig. 11, N is equal to 5, obtaining first pair signals Comp _ Hp and Comp _ Hn, second pair signals Comp _ MHp and Comp _ MHn, third pair signals Comp _ MLp and Comp _ MLn, and fourth pair signals Comp _ Lp and Comp _ Ln; obtaining a voltage signal of one polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to one of the third feedback branches 600, and obtaining a voltage signal of the other polarity and outputting the voltage signal to a decoding circuit; the voltage signals respectively obtaining one polarity from the third pair of signals and the fourth pair of signals are output to the other third feedback branch 600, and the voltage signals respectively obtaining the other polarity are output to the decoding circuit. Specifically, signals Comp _ Hp and Comp _ Ln are output to the third feedback branch 600; the signals Comp _ Hn and Comp _ Lp are output to the decoding circuit; signals Comp _ MHp and Comp _ MLn are output to the fourth feedback branch; the signals Comp _ MHn and Comp _ MLp are output to the decoding circuit.
It can be understood that in the decision feedback method, the output voltage signal needs to be decoded. In the decision feedback equalizer and the decision feedback method in the prior art, two paths of voltage signals in a pair of output paired signals of each slicer need to be fed back and decoded, and in the decision feedback equalizer and the decision feedback method in the embodiment, one path of polarity voltage signal in the pair of paired signals is used for feedback, and the other path of polarity voltage signal is used for decoding, so that the load of each output of the slicer is not only reduced, the node parasitic is also reduced, and the driving capability of the slicer is equivalently enhanced. The decoding circuit comprises a decoder which converts the input voltage signal into a binary code, namely an NRZ signal, so as to facilitate the processing of other subsequent circuit modules of a receiver.
Example two
Referring to fig. 10 and 12, the present embodiment discloses a decision feedback equalizer, including: an addition module 100 and a slicing module 200 electrically connected to each other; the adding module 100 is configured to obtain a voltage input signal PAM _ N modulated by an N-level pulse amplitude and convert the voltage input signal PAM _ N into a corresponding current input signal, convert a voltage feedback signal output by the slicing module 200 into a current feedback signal through an internal feedback branch, and compensate the current input signal to generate a voltage output signal, where N is greater than or equal to 2. The slicing module 200 is configured to obtain the voltage output signals, compare and convert the voltage output signals to obtain N-1 pairs of paired signals, where each pair of paired signals includes two voltage signals with opposite polarities.
When N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals; when N is an odd number, a voltage signal of one polarity is obtained from each of the N-1 pairs of signals as a voltage feedback signal. And each two paths of voltage feedback signals are output to the same feedback branch and are switched into corresponding current feedback signals through the feedback branch.
The working principle of the decision feedback equalizer in this embodiment is as follows: the adding module 100 is used for obtaining a voltage input signal PAM _ N modulated by N-level pulse amplitude and converting the voltage input signal PAM _ N into a corresponding current input signal, generating a voltage output signal according to the compensated current input signal and outputting the voltage output signal to the slicing module 200, the slicing module 200 compares and converts the voltage input signal to obtain N-1 pairs of paired signals, extracts a feedback signal from the paired signals and outputs the feedback signal to the adding module 100, and the adding module 100 converts the voltage feedback signal into a current feedback signal and combines the current feedback signal with the current input signal to eliminate intersymbol interference. When N is an even number, respectively acquiring a voltage signal with one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals; when N is an odd number, a voltage signal of one polarity is obtained from each of the N-1 pairs of signals as a voltage feedback signal. And each two paths of voltage feedback signals are output to the same feedback branch and are switched into corresponding current feedback signals through the feedback branch.
It can be understood that, the decision feedback equalizer of the present embodiment reduces the number of feedback branches to N/2 or (N-1)/2 on the one hand, and reduces the number of feedback signals to N on the other hand, which is beneficial to simplify the circuit structure, reduce the parasitic parameters of the circuit, and alleviate the clock constraint of the decision feedback equalizer, and is suitable for input signals of various coding types.
Specifically, the slicing module 200 includes N-1 slicing units 210, and each of the slicing units 210 is configured to output a pair of paired signals. Wherein the slicing unit 210 is a slicer.
Specifically, the adding module 100 includes: a single signal input unit 110 and at least one feedback unit 120; the signal input unit 110 is electrically connected to the slicing module 200, and the signal input unit 110 is configured to receive a voltage input signal PAM _ N, convert the voltage input signal PAM _ N into a corresponding current input signal, generate a voltage output signal according to the compensated current input signal, and output the voltage output signal to the slicing module 200; the feedback unit 120 is electrically connected to the signal input unit 110 and the slicing module 200, respectively, and the feedback unit 120 is configured to receive a voltage feedback signal output by the slicing module 200, convert the voltage feedback signal into a current feedback signal, and compensate the current input signal according to the current feedback signal.
It can be understood that the signal input unit 110 obtains a voltage input signal of N-level pulse amplitude modulation, and converts the voltage input signal into a corresponding current input signal, and the signal input unit 110 generates a voltage output signal according to the compensated current output signal and outputs the voltage output signal to the slicing module 200, the slicing module 200 returns a voltage feedback signal to the feedback unit 120, and the feedback unit 120 converts the voltage feedback signal into a current feedback signal and combines the current feedback signal with the voltage feedback signal, thereby eliminating inter-symbol interference of the voltage input signal.
Further, the signal input unit 110 includes: a first current source 111, a first transistor 112, a second transistor 113, a first resistor R1, and a second resistor R2;
the first current source 111 is connected to the source of the first transistor 112 and the source of the second transistor 113, the gate of the first transistor 112 and the gate of the second transistor 113 are connected to the voltage input signal, the drain of the first transistor 112 is connected to the input terminal of the slice module 200 and one end of the first resistor R1, the drain of the second transistor 113 is connected to the input terminal of the slice module 200 and one end of the second resistor R2, and the other end of the first resistor R1 and the other end of the second resistor R2 are both grounded.
It is understood that the voltage input signal is converted into the current input signal, and the voltage feedback signal is converted into the current feedback signal to perform the current compensation on the current output signal, and these currents will form a voltage drop on the first resistor R1 and the second resistor R2, thereby generating the voltage output signal to be output to the switching module 200.
Further, the feedback unit 120 includes: a second current source 121, a third transistor 122, and a fourth transistor 123; the second current source 121 is connected to a source of the third transistor 122 and a source of the fourth transistor 123, a gate of the third transistor 122 and a gate of the fourth transistor 123 are both connected to an output terminal of the slice module 200, a drain of the third transistor 122 is connected to a drain of the first transistor 112 and an input terminal of the slice module 200, and a drain of the fourth transistor 123 is connected to a drain of the second transistor 113 and an input terminal of the slice module 200.
In summary, according to the decision feedback method and the decision feedback equalizer provided by the present invention, by obtaining N-1 pairs of paired signals, when N is an even number, one polarity voltage signal is taken from each of the N-2 pairs of paired signals, and two voltage signals of the remaining pair of signals are taken as feedback signals; when N is an odd number, respectively taking one polarity voltage signal from the N-1 pairs of signals as a feedback signal; each two feedback signals act on the same feedback branch, so that the number of the feedback branches is reduced to N/2 or (N-1)/2, and when N is an even number, the number of the feedback signals is reduced to N; when N is an odd number, the number of feedback signals is reduced to N-1. The circuit structure is simplified, the parasitic parameter of the circuit is reduced, the clock constraint of the decision feedback equalizer is relieved, and the circuit is suitable for input signals of various coding types.
In addition, one path of voltage signal with the polarity is taken from the paired signals for feedback, and the other path of voltage signal with the polarity is used for decoding, so that the load of each output of the slicer is reduced, the node parasitic is also reduced, and the driving capability of the slicer is enhanced.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent modifications made by the contents of the present specification and the drawings, or applied to the related technical fields directly or indirectly, are included in the scope of the present invention.
Claims (10)
1. A method for decision feedback, comprising the steps of:
acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, wherein N is more than or equal to 2;
judging the voltage input signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two paths of voltage signals with opposite polarities;
when N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals;
when N is an odd number, acquiring a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal;
outputting each two paths of voltage feedback signals to the same feedback branch circuit, and converting the voltage feedback signals into corresponding current feedback signals through the feedback branch circuit;
and compensating the current input signal according to the current feedback signal so as to reduce intersymbol interference of the voltage input signal.
2. The decision feedback method of claim 1,
when N is an even number, providing a first feedback branch and a second feedback branch;
the first feedback branch circuit receives voltage signals in two paths of different paired signals respectively, and the output current of an input current source of the first feedback branch circuit is 2I;
the second feedback branch receives two voltage signals in the same paired signal, and the output current of the input current source of the second feedback branch is I.
3. The decision feedback method of claim 1,
and when N is an odd number, providing a third feedback branch, wherein the third feedback branch receives voltage signals in two paths of different paired signals respectively, and the output current of an input current source of the third feedback branch is 2I.
4. The decision feedback method of claim 1,
when N is equal to 4, obtaining a first paired signal, a second paired signal and a third paired signal;
obtaining a voltage signal of one polarity from the first paired signals and the second paired signals respectively and outputting the voltage signal to a first feedback branch circuit, and obtaining a voltage signal of the other polarity respectively and outputting the voltage signal to a decoding circuit;
and two paths of voltage signals are obtained from the third pair of signals and output to a second feedback branch, and one polarity of voltage signal is taken and output to a decoding circuit.
5. The decision feedback method of claim 1,
when N is equal to 5, obtaining a first paired signal, a second paired signal, a third paired signal and a fourth paired signal;
obtaining a voltage signal of one polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to one of the third feedback branches, and obtaining a voltage signal of the other polarity from each of the first pair signal and the second pair signal and outputting the voltage signal to a decoding circuit;
and voltage signals respectively acquiring one polarity from the third pair of signals and the fourth pair of signals are output to the other third feedback branch, and voltage signals respectively acquiring the other polarity are output to a decoding circuit.
6. A decision feedback equalizer, comprising: the adding module and the slicing module are electrically connected with each other;
the addition module is used for acquiring a voltage input signal modulated by N-level pulse amplitude and converting the voltage input signal into a corresponding current input signal, converting a voltage feedback signal output by the slicing module into a current feedback signal through an internal feedback branch circuit, and compensating the current input signal to generate a voltage output signal, wherein N is greater than or equal to 2;
the slicing module is used for acquiring the voltage output signals and comparing and converting the voltage output signals to obtain N-1 pairs of paired signals, wherein each pair of paired signals comprises two paths of voltage signals with opposite polarities;
when N is an even number, respectively acquiring a voltage signal of one polarity from the N-2 pairs of paired signals and acquiring two paths of voltage signals from the rest pairs of paired signals as voltage feedback signals;
when N is an odd number, acquiring a voltage signal with one polarity from the N-1 pairs of signals as a voltage feedback signal;
and each two paths of voltage feedback signals are output to the same feedback branch and are switched into corresponding current feedback signals through the feedback branch.
7. The decision feedback equalizer of claim 6 wherein the slicing module includes N-1 slicing units, each of the slicing units for outputting a pair of paired signals.
8. The decision feedback equalizer of claim 6 wherein the summing module comprises: a signal input unit and at least one feedback unit;
the signal input unit is electrically connected with the slicing module and is used for receiving a voltage input signal, converting the voltage input signal into a corresponding current input signal, generating a voltage output signal according to the compensated current input signal and outputting the voltage output signal to the slicing module;
the feedback unit is respectively electrically connected with the signal input unit and the slicing module, and is used for receiving a voltage feedback signal output by the slicing module, converting the voltage feedback signal into a current feedback signal, and compensating the current input signal according to the current feedback signal.
9. The decision feedback equalizer of claim 8 wherein the signal input unit comprises: the circuit comprises a first current source, a first transistor, a second transistor, a first resistor and a second resistor;
the first current source is respectively connected with a source electrode of the first transistor and a source electrode of the second transistor, a grid electrode of the first transistor and a grid electrode of the second transistor are connected with the voltage input signal, a drain electrode of the first transistor is respectively connected with an input end of the slicing module and one end of the first resistor, a drain electrode of the second transistor is respectively connected with an input end of the slicing module and one end of the second resistor, and the other end of the first resistor and the other end of the second resistor are both grounded.
10. The decision feedback equalizer of claim 9 wherein the feedback unit comprises: a second current source, a third transistor, and a fourth transistor;
the second current source is connected to a source of the third transistor and a source of the fourth transistor, a gate of the third transistor and a gate of the fourth transistor are both connected to an output terminal of the slice module, a drain of the third transistor is connected to a drain of the first transistor and an input terminal of the slice module, and a drain of the fourth transistor is connected to a drain of the second transistor and an input terminal of the slice module.
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