CN115084219A - GaN heterojunction vertical semiconductor device and preparation method - Google Patents
GaN heterojunction vertical semiconductor device and preparation method Download PDFInfo
- Publication number
- CN115084219A CN115084219A CN202210340841.1A CN202210340841A CN115084219A CN 115084219 A CN115084219 A CN 115084219A CN 202210340841 A CN202210340841 A CN 202210340841A CN 115084219 A CN115084219 A CN 115084219A
- Authority
- CN
- China
- Prior art keywords
- groove
- cell
- trench
- conductive
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 129
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 84
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 75
- 230000004888 barrier function Effects 0.000 claims description 44
- 230000001413 cellular effect Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a GaN heterojunction vertical semiconductor device and a preparation method thereof.A cell groove comprises a cell first groove body and a cell second groove body, wherein a groove second conductive polycrystalline silicon body and a groove second insulating oxide layer are arranged in the cell second groove body; the first conductive polycrystalline silicon body of the groove is insulated and isolated from the inner side wall of the first groove body of the cell through a first insulating oxide layer of the groove covering the first groove body of the cell; the bottom of the groove second conductive polycrystalline silicon body is located right below the groove bottom of the first groove body of the unit cell, and the groove second conductive polycrystalline silicon body is insulated and isolated from the groove first conductive polycrystalline silicon body and the first conductive type drift region through a groove second insulating oxide layer. The invention can effectively reduce the switching loss of the device, is compatible with the prior art and has low manufacturing cost.
Description
Technical Field
The invention relates to a conductor device and a preparation method thereof, in particular to a GaN heterojunction vertical semiconductor device and a preparation method thereof.
Background
The GaN HEMT (High Electron Mobility Transistor) device has the characteristics of small on resistance, High switching speed, High breakdown electric field, High saturation current density and the like, and the GaN device mainly uses a GaN HEMT transverse device at present, but the transverse device has the problems of current collapse, buffer layer leakage current, grid leakage current and the like, the High breakdown characteristic of a GaN material cannot be fully utilized, and the application of the High critical breakdown electric field intensity characteristic of the GaN device is severely restricted.
The GaN vertical semiconductor device can withstand voltage through the vertical drift region, and can well solve the problem of current collapse through body electrons and two-dimensional electron gas conduction generated between AlGaN and GaN. The breakdown voltage of the device can be controlled by changing the thickness and the doping concentration of the drift region, the problem of large area of a transverse device can be solved, the area of the device is effectively reduced, and the production cost is reduced. However, the parasitic capacitance (Cgd) from the gate to the back electrode of the conventional GaN vertical semiconductor device is large, and when the parasitic capacitance Cgd is large, the turn-off time of the semiconductor device is prolonged, so that the switching loss of the device is high.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a GaN heterojunction vertical semiconductor device and a preparation method thereof, which can effectively reduce the switching loss of the device, are compatible with the prior art and have low manufacturing cost.
According to the technical scheme provided by the invention, the GaN heterojunction vertical semiconductor device comprises a GaN substrate and a cellular region prepared in the central region of the GaN substrate, wherein the GaN substrate comprises a first conduction type drift region, the cellular region comprises a plurality of cellular units distributed in parallel, the cellular units in the cellular region adopt a groove structure, and cellular grooves of the cellular units are prepared in the first conduction type drift region;
on the cross section of the vertical semiconductor device, the cell groove comprises a cell first groove body and a cell second groove body vertically penetrating through the cell first groove body, the width of the cell second groove body is smaller than that of the cell first groove body, and the groove bottom of the cell second groove body is positioned right below the groove bottom of the cell first groove body;
the second groove body is arranged in the second groove body of the cell, the second groove conductive polycrystalline silicon body is distributed along the length direction of the second groove body of the cell, and the second groove insulating oxide layer surrounds the second groove conductive polycrystalline silicon body of the groove; the first groove conductive polycrystalline silicon body is insulated and isolated from the inner side wall of the first groove body of the unit cell through a first groove insulating oxide layer covering the first groove body of the unit cell; the bottom of the second conductive polycrystalline silicon body of the groove is positioned right below the groove bottom of the first groove body of the cellular, and the second conductive polycrystalline silicon body of the groove is insulated and isolated from the first conductive polycrystalline silicon body of the groove and the first conductive type drift region through a second insulating oxide layer of the groove;
and arranging a front electrode structure above the front surface of the GaN substrate, wherein the front electrode structure comprises source electrode metal and grid electrode metal, the grid electrode metal is electrically connected with the first conductive polycrystalline silicon body of the groove, and the source electrode metal is electrically connected with the second conductive polycrystalline silicon body of the groove.
The GaN substrate comprises a barrier layer arranged on the first conduction type drift region and a first conduction type heavily doped layer adjacent to the first conduction type drift region, and the doping concentration of the first conduction type heavily doped layer is greater than that of the first conduction type drift region; forming the front surface of the GaN substrate by using the corresponding surface of the barrier layer, and forming the back surface of the GaN substrate by using the corresponding surface of the first conductive type heavily doped layer;
the first groove body of the unit cell penetrates through the barrier layer, the groove bottom of the first groove body of the unit cell is positioned below the barrier layer, and the source metal is electrically connected with the barrier layer.
And a second conductive type injection region is arranged below the bottom of the second groove body of the cell, and the second conductive type injection region coats the bottom of the second groove body of the cell.
And the front surface of the GaN substrate is also provided with an insulating medium layer for supporting source metal and grid metal, the source metal is electrically connected with the second conductive polysilicon body of the groove and the barrier layer through a source metal contact hole body arranged in the insulating medium layer, and the grid metal is electrically connected with the first conductive polysilicon body of the groove through a grid metal contact hole body arranged in the insulating medium layer.
The GaN substrate further comprises a back electrode structure arranged on the back surface of the GaN substrate.
The barrier layer is an AlGaN layer, an AlN layer, an InN layer or an InGaN layer.
A method for manufacturing a GaN heterojunction vertical semiconductor device, the method comprising the steps of:
and 5, preparing a required front electrode structure on the front surface of the GaN substrate, wherein the front electrode structure comprises source electrode metal and grid electrode metal, the grid electrode metal is electrically connected with the first conductive polycrystalline silicon body of the groove, and the source electrode metal is electrically connected with the second conductive polycrystalline silicon body of the groove.
The GaN substrate comprises a barrier layer arranged in the first conduction type drift region and a first conduction type heavily doped layer adjacent to the first conduction type drift region, and the doping concentration of the first conduction type heavily doped layer is greater than that of the first conduction type drift region; forming the front surface of the GaN substrate by utilizing the corresponding surface of the first conductive type drift region, and forming the back surface of the GaN substrate by utilizing the corresponding surface of the first conductive type heavily doped layer;
the first groove body of the unit cell penetrates through the barrier layer, the groove bottom of the first groove body of the unit cell is positioned below the barrier layer, and the source metal is in ohmic contact with the barrier layer.
In step 3, after the second trench body of the cell is prepared, required second conductive type impurity ion implantation is performed on the front surface of the GaN substrate to obtain a second conductive type implantation region below the bottom of the second trench body of the cell, wherein the second conductive type implantation region coats the bottom of the second trench body of the cell.
And carrying out a required back electrode process on the back of the GaN substrate to obtain a required back electrode structure.
Of the "first conductivity type" and the "second conductivity type", for an N-type semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type semiconductor device, the first conductivity type and the second conductivity type refer to the opposite type of the N-type semiconductor device.
The invention has the advantages that: the cell trench comprises a cell first trench body and a cell second trench body vertically penetrating through the cell first trench body, a trench second conductive polycrystalline silicon body and a trench second insulating oxide layer wrapping the trench second conductive polycrystalline silicon body in a surrounding mode are arranged in the cell second trench body, a trench first conductive polycrystalline silicon body is filled in the cell first trench body, and the trench first conductive polycrystalline silicon body is distributed on two sides of the trench second conductive polycrystalline silicon body;
the second conductive polysilicon body of the groove plays a role of a field plate, can assist in depletion and improves the voltage endurance capability. The parasitic capacitance Cgd from the gate electrode to the back electrode can be changed into a form that the parasitic capacitance Cgs from the gate electrode to the shielding gate electrode is connected in series with the parasitic capacitance Csd from the shielding gate electrode to the back electrode through the second conductive polysilicon body of the groove, the parasitic capacitance Cgd from the gate electrode to the back electrode after series connection can be reduced, and when the parasitic capacitance Cgd is reduced, the switching loss of the semiconductor device can be effectively reduced.
Drawings
FIGS. 1-7 are cross-sectional views of process steps in accordance with an embodiment of the present invention, wherein
FIG. 1 is a cross-sectional view of a cell reference trench according to the present invention;
FIG. 2 is a cross-sectional view of a first trench body of a cell according to the present invention;
FIG. 3 is a cross-sectional view of the present invention after an insulating oxide has been obtained;
FIG. 4 is a cross-sectional view of a resulting second trench for a cell of the present invention;
FIG. 5 is a cross-sectional view of a second conductive polysilicon body with trenches in accordance with the present invention;
FIG. 6 is a cross-sectional view of the source metal contact hole and the gate metal contact hole of the present invention;
fig. 7 is a cross-sectional view of the present invention after obtaining a front electrode structure.
Description of reference numerals: the structure comprises a 1-N type drift region, a 2-N + heavily doped region, a 3-barrier layer, a 4-base groove, a 5-mask layer, a 6-cell first groove body, a 7-insulating oxidation unit layer, an 8-groove first conductive polycrystalline silicon body, a 9-cell second groove body, a 10-groove second insulating oxidation layer, an 11-groove second conductive polycrystalline silicon body, a 12-groove second conductive polycrystalline silicon body, a 13-insulating dielectric layer, a 14-grid contact connecting column, a 15-source contact first connecting column, a 16-source contact second connecting column, a 17-grid first connecting block, an 18-source first connecting block, a 19-grid second connecting block, a 20-source second connecting block and a 21-groove first insulating oxidation layer.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 7: in order to effectively reduce the switching loss of the device, taking an N-type semiconductor device as an example, the invention comprises a GaN substrate and a cellular region prepared in the central region of the GaN substrate, wherein the GaN substrate comprises an N-type drift region 1, the cellular region comprises a plurality of cellular units distributed in parallel, the cellular units in the cellular region adopt a groove structure, and cellular grooves of the cellular units are prepared in the N-type drift region 1;
on the cross section of the vertical semiconductor device, the cell groove comprises a cell first groove body 6 and a cell second groove body 9 vertically penetrating through the cell first groove body 6, the width of the cell second groove body 9 is smaller than that of the cell first groove body 6, and the groove bottom of the cell second groove body 9 is positioned right below the groove bottom of the cell first groove body 6;
a trench second conductive polysilicon body 12 distributed along the length direction of the cell second trench body 9 and a trench second insulating oxide layer 10 surrounding and wrapping the trench second conductive polysilicon body 12 are arranged in the cell second trench body 9, a trench first conductive polysilicon body 8 is filled in the cell first trench body 6, and the trench first conductive polysilicon body 8 is distributed on two sides of the trench second conductive polysilicon body 12; the trench first conductive polysilicon body 8 is insulated and isolated from the inner side wall of the cell first trench body 6 by a trench first insulating oxide layer 21 covering the cell first trench body 6; the bottom of the trench second conductive polysilicon body 12 is positioned right below the bottom of the first cell trench body 6, and the trench second conductive polysilicon body 12 is insulated and isolated from the trench first conductive polysilicon body 8 and the N-type drift region 1 through a trench second insulating oxide layer 10;
a front electrode structure is arranged above the front surface of the GaN substrate, and the front electrode structure includes a source metal and a gate metal, wherein the gate metal is electrically connected to the first conductive polysilicon body 8 of the trench, and the source metal is electrically connected to the second conductive polysilicon body 12 of the trench.
Specifically, the GaN substrate may specifically adopt an existing commonly used form, and the N-type substrate 1 is included in the GaN substrate, and the specific condition of the GaN substrate is subject to the requirement of satisfying the semiconductor device. Generally, the cell region is located in the central region of the GaN substrate, and the terminal protection region is generally disposed at the outer ring of the cell region, so that the cell region can be protected by the terminal protection region, the withstand voltage of the cell region is improved, and the specific coordination between the cell region and the terminal protection region is the same as that in the prior art, which is well known to those skilled in the art and will not be described herein again.
Generally, a plurality of cells are included in the cell area, and the cells in the cell area are connected in parallel to form a whole. In the embodiment of the present invention, the cells in the cell region adopt a trench structure, that is, for any cell, each cell includes a cell trench, and the cell trench is located in the N-type drift region 1, and certainly, the depth of the cell trench is less than the thickness of the N-type drift region 1.
In the embodiment of the present invention, the cell trench of a cell includes a first cell trench body 6 and a second cell trench body 9 vertically penetrating through the first cell trench body 6, where vertical penetration means that the first cell trench body 6 penetrates through the second cell trench body in the depth direction of the first cell trench body 6, the depth of the second cell trench body 9 in the N-type drift region 1 is greater than the depth of the first cell trench body 6 in the N-type drift region 1, and the bottom of the second cell trench body 9 is located right below the bottom of the first cell trench body 6. The width of the cell second trench 9 is smaller than that of the cell first trench 6, and generally, the cell second trench 9 and the cell first trench 6 are coaxially distributed.
On the cross section of the semiconductor device, a trench second conductive polysilicon body 12 is arranged in the cell second trench body 9, wherein the trench second conductive polysilicon body 12 is distributed in the cell second trench body 9 along the length direction of the cell second trench body 9, the length of the trench second conductive polysilicon body 12 is smaller than the depth of the cell second trench body 9, and the bottom of the trench second conductive polysilicon body 12 is located below the bottom of the cell first trench body 6. The upper end of the trench second conductive polysilicon body 12 corresponds to the notch of the cell second trench body 9, and the trench second insulating oxide layer 10 surrounds the trench second conductive polysilicon body 12, i.e., the trench second insulating oxide layer 10 surrounds the region except the upper end of the trench second conductive polysilicon body 12, so that the lower portion of the trench second conductive polysilicon body 12 in the cell second trench body 9 can be insulated and isolated from the corresponding N-type drift region 1 by the trench second insulating oxide layer 10.
On the cross section of the semiconductor device, a first trench conductive polysilicon body 8 is filled in the first cell trench body 6, wherein the first filled trench conductive polysilicon body 8 is symmetrically distributed on two sides of a second trench conductive polysilicon body 12, and the first trench conductive polysilicon body 8 is insulated and isolated from the second trench conductive polysilicon body 12 through a second trench insulating oxide layer 10. In the first trench cell 6, a first trench insulating oxide layer 21 is disposed on the inner sidewall of the first trench cell 6, so that the first trench conductive polysilicon body 8 is insulated and isolated from the sidewall of the first trench cell 6 by the first trench insulating oxide layer 21. The trench first insulating oxide layer 21 at the bottom in the cell first trench body 6 and the trench second insulating oxide layer 10 are connected to each other. Typically, the trench first insulating oxide layer 21 and the trench second insulating oxide layer 10 are silicon dioxide layers.
In specific implementation, for the connection use of the semiconductor device, a front electrode structure is disposed above the front surface of the GaN substrate, wherein the front electrode structure includes a source metal and a gate metal, the gate metal is electrically connected to the first conductive polysilicon body 8, the source metal is electrically connected to at least the second conductive polysilicon body 12, and the source metal can connect the cells in the cell region into a whole in parallel. Specifically, a source terminal of the semiconductor device can be formed using the source metal, and a gate terminal of the semiconductor device can be formed using the gate metal.
Further, the GaN substrate further comprises a barrier layer 3 arranged on the N-type drift region 1 and an N + heavily doped layer 2 adjacent to the N-type drift region 1, wherein the doping concentration of the N + heavily doped layer 2 is greater than that of the N-type drift region 1; forming the front surface of the GaN substrate by using the corresponding surface of the barrier layer 3, and forming the back surface of the GaN substrate by using the corresponding surface of the N + heavily doped layer 2;
the first cell groove body 6 penetrates through the potential barrier 3, the groove bottom of the first cell groove body 6 is positioned below the barrier layer 3, and the source metal is electrically connected with the barrier layer 3.
In the embodiment of the invention, the barrier layer 3 is arranged on the N-type drift region 1, the thickness direction of the barrier layer 3 is consistent with the direction from the front surface of the GaN substrate to the back surface of the GaN substrate, and the depth of the barrier layer 3 is smaller than the thickness of the N-type drift region 1. After the cell trench is formed in the N-type drift region 1, the cell first trench 6 penetrates the barrier layer 3 in the depth direction, so that the bottom of the cell first trench 6 is located below the barrier layer 3. The barrier layer 3 may be an AlGaN layer, an AlN layer, an InN layer, or an InGaN layer, and the type of the barrier layer 3 may be selected according to actual needs, so as to meet the requirements of semiconductor devices. The barrier layer 3 functions as in the related art, and the source metal is electrically connected to the barrier layer 3.
Generally, for a GaN substrate, the front and back surfaces are two front corresponding surfaces. In specific implementation, the N-type drift region 1 is adjacent to the N + heavily doped layer 2, and the N + heavily doped layer 2 can form the back surface of the GaN substrate. The doping concentration of the N + heavily doped layer 2 is greater than that of the N-type drift region 1, and the thickness of the N + heavily doped layer 2 is less than that of the N-type drift region 1.
When the barrier layer 3 is arranged, 2DEG (two-dimensional electron gas, a GaN and AlGaN heterojunction interface exists) is also formed at the connecting part of the barrier layer 3 and the N-type drift region 1, so that a heterojunction can be obtained, and the two-dimensional electron gas (2DEG) with high mobility and high carrier surface density is formed by generating a polarization electric field at the heterojunction and modulating the distribution of energy bands and charges. When the voltage of the gate terminal is 0V, the 2DEG and the channel near the gate are depleted, and the semiconductor device is in an off state. When the voltage of the grid terminal is larger than the threshold voltage of the semiconductor device, an inversion layer is formed, and at the moment, a conductive channel is formed, so that the semiconductor device is started. Therefore, a horizontal channel can be introduced by the 2DEG existing on the heterojunction interface, the current density of the semiconductor device can be effectively increased, and the on-resistance is reduced.
In addition, the GaN substrate further comprises a back electrode structure arranged on the back surface of the GaN substrate. The back electrode structure can be used for forming a back electrode of the semiconductor device, the whole semiconductor device can be an MOSFET device or an IGBT device according to different back electrode structures, the specific situation of the back electrode structure can be selected according to actual needs so as to meet requirements of the semiconductor device such as use, and the like, and the back electrode structure is not repeated here.
Further, a P-type injection region is disposed below the groove bottom of the cell second trench body 9, and the P-type injection region covers the groove bottom of the cell second trench body 9.
In the embodiment of the present invention, the P-type injection region is disposed below the bottom of the second trench 9, and the formed P-type injection region covers the bottom of the second trench 9, that is, the P-type injection region covers the outer wall of the bottom of the second trench 9, so that the P-type injection region can enhance the withstand voltage of the semiconductor device.
Further, an insulating medium layer 13 for supporting source metal and gate metal is further disposed on the front surface of the GaN substrate, the source metal is electrically connected to the second conductive polysilicon body 12 of the trench and the barrier layer 3 through a source metal contact hole body disposed in the insulating medium layer 13, and the gate metal is electrically connected to the first conductive polysilicon body 8 of the trench through a gate metal contact hole body disposed in the insulating medium layer 13.
In the embodiment of the present invention, the insulating medium layer 13 is supported on the front surface of the GaN substrate, and the insulating medium layer may be a silicon nitride layer, which may be specifically selected according to actual needs. After the insulating medium layer 13 is supported on the GaN substrate, the corresponding notches of the first cell trench 6 and the second cell trench 9 can be closed.
In order to satisfy the corresponding electrical connection between the source metal and the gate metal, a required contact hole needs to be formed in the insulating dielectric layer 13. In fig. 7, the source metal contact hole body includes a source contact first connection pillar 15 filled in the source first contact hole and a source contact second connection pillar 16 filled in the source second contact hole, the source first contact hole and the source second contact hole penetrate through the insulating dielectric layer 13, the source first contact hole corresponds to the trench second conductive polysilicon body 12, and the source second contact hole is generally located between two cell trenches and corresponds to the barrier layer 3 between the two cell trenches. The source electrode contacts the first connecting column 15 and is in ohmic contact with the second conductive polysilicon body 12 of the trench, the source electrode contacts the second connecting column 16 and is in ohmic contact with the barrier layer 3 which is in ohmic contact with the source electrode, and the source electrode contacts the first connecting column 15 and the source electrode contacts the second connecting column 16 and is electrically connected with the source electrode metal, so that the electrical connection between the source electrode metal and the second conductive polysilicon body 12 of the trench and the barrier layer 3 is realized.
Similarly, the gate metal contact hole body includes a gate contact connection column 14 filled in the gate contact hole, on the cross section of the semiconductor device, the gate contact connection column 14 is in one-to-one correspondence with the first conductive polysilicon bodies 8 in the first trench body 6 of the unit cell, the gate contact connection column 14 is in ohmic contact with the first conductive polysilicon bodies 8 in the trench, and the gate contact connection column 14 is electrically connected with the gate metal, so that the electrical connection between the gate metal and the first conductive polysilicon bodies 8 in the trench is realized.
In specific implementation, the gate metal supported on the insulating dielectric layer 13 includes a first gate connecting block 17 and a second gate connecting block 19, wherein the first gate connecting block 17 is electrically connected to one gate contact connection pillar 14, the second gate connecting block 19 is electrically connected to the other gate connection pillar 14, and the first gate connecting block 17 and the second gate connecting block 19 are electrically connected to each other. The source metal supported on the insulating dielectric layer 13 includes a first source connecting block 18 and a second source connecting block 20, wherein the first source connecting block 18 is electrically connected to the first source contact connecting post 15, the second source connecting block 20 is electrically connected to the second source contact connecting post 16, and the first source connecting block 18 and the second source connecting block 20 are electrically connected to each other to form a whole. The specific connection states of the source metal and the gate metal can be satisfied by the corresponding connection cooperation among the gate first connection block 17, the source first connection block 18, the gate second connection block 19 and the source second connection block 20.
In the embodiment of the present invention, the trench first conductive polysilicon body 8 is located at the outer ring of the trench second conductive polysilicon body 12 or symmetrically distributed at two sides of the trench second conductive polysilicon body 12, and the trench second conductive polysilicon body 12 functions as a field plate, so that depletion can be assisted, and voltage withstanding capability can be improved. Through the trench second conductive polysilicon body 12, the parasitic capacitance Cgd from the existing gate electrode to the back electrode can be changed into a form that the parasitic capacitance Cgs from the gate electrode (namely, the trench first conductive polysilicon body 8) to the shield gate electrode (namely, the trench second conductive polysilicon body 12) is connected in series with the parasitic capacitance Csd from the shield gate electrode to the back electrode, the parasitic capacitance Cgd from the gate electrode to the back electrode after series connection can be reduced, and when the parasitic capacitance Cgd is reduced, the switching loss of the semiconductor device can be effectively reduced.
As shown in fig. 1 to 7, the GaN heterojunction vertical semiconductor device can be prepared by the following process steps, specifically, the preparation method comprises the following steps:
specifically, a conventional GaN substrate may be adopted, for example, the GaN substrate includes an N-type drift region 1, an N + heavily doped layer 2, and a barrier layer 3 disposed in the N-type drift region 1, and the specific case of the GaN substrate may refer to the above description, and will not be described herein again.
In order to prepare the first trench 6, in a specific implementation, the mask layer 5 needs to be disposed on the front surface of the GaN substrate, that is, the mask layer 5 is disposed on the N-type drift region 1, and the mask layer 5 may specifically adopt an existing common form. The masking of the N-type drift region 1 is realized by using the mask layer 5, so that a base trench 4 can be obtained in the N-type drift region 1, as shown in fig. 1. The base trench 4 extends vertically downward from the front surface of the GaN substrate, the bottom of the base trench 4 is generally located below the barrier layer 3, and the process conditions and the process for etching the N-type drift layer 1 by using the mask layer 5 are consistent with those of the prior art, which are well known in the art and will not be described herein again.
After obtaining the base trench 4, performing anisotropic and isotropic etching to obtain a first trench body 6 of the unit cell corresponding to the base trench 4 after etching, as shown in fig. 2; the depth of the first cell groove body 6 is greater than that of the base groove 4, the width of the first cell groove body 6 is also greater than that of the base groove 4, the first cell groove body 6 can be formed after the base groove 4 is etched by adopting a common technical means in the technical field, and specific technological conditions and processes can be selected as required so as to meet the requirement for preparing the required first cell groove body 6.
specifically, a thermal oxidation or deposition process may be adopted to dispose the insulating oxidation unit layer 7, where the insulating oxidation unit layer 7 covers the mask layer 5 and also covers the inner side wall and the bottom wall of the first trench body 6 of the unit cell, as shown in fig. 3; the insulating oxidation unit layer 7 is specifically set to be a silicon dioxide layer, and the process and conditions for specifically preparing the insulating oxidation unit layer 7 can be selected according to actual needs.
After the insulating oxidation unit layer 7 is prepared, a polysilicon filling process is performed to fill the first trench of the cell to obtain a first conductive polysilicon substrate of the trench, the first conductive polysilicon substrate of the trench fills the first trench 6 of the cell, and at this time, the first conductive polysilicon substrate of the trench filled in the first trench 6 of the cell is insulated and isolated from the inner side wall and the bottom wall of the first trench 6 of the cell by using the insulating oxidation unit layer 7.
In specific implementation, the insulating oxidation unit layer 7 on the mask layer 5 and the trench first conductive polysilicon substrate may be removed by a conventional technical means in the field, and after the insulating oxidation unit layer 7 on the mask layer 5 is removed, the trench first insulating oxide layer 21 is formed by using the insulating oxidation unit layer 7 in the cell first trench body 6.
specifically, a trench etching process is performed on the GaN substrate after the step 2, that is, the trench first conductive polysilicon substrate in the cell first trench body 6, the trench first insulating oxide layer 21 on the bottom wall of the cell first trench body 6, and the N-type drift region 1 right below the bottom of the cell first trench body 6 are etched, so that the cell second trench body 9 can be prepared, and the conditions and the process of the specific trench etching process can be selected according to actual needs, so that the required cell second trench body 9 can be prepared.
For the prepared second cell groove body 9, the second cell groove body 9 penetrates through the first cell groove body 6, the width of the second cell groove body 9 is smaller than that of the first cell groove body 6, and the groove bottom of the second cell groove body 9 is positioned right below the groove bottom of the first cell groove body 6; after etching the first conductive polysilicon body of the trench in the first trench body 6 of the cell, the desired first conductive polysilicon body 8 of the trench can be obtained in the first trench body 6 of the cell, as shown in fig. 4.
In practice, of course, after the cell second trench 9 is prepared, the required P-type impurity ion implantation is performed on the front surface of the GaN substrate to obtain a P-type implantation region under the bottom of the cell second trench 9, and the P-type implantation region covers the bottom of the cell second trench 9. When P-type impurity ions are implanted, the blocking of the mask layer 5 can be utilized to prepare a desired P-type implantation region only at the bottom of the second trench 9, and during implantation, the concentration of the P-type impurity ions and other implantation conditions can be selected as required, so as to obtain the desired P-type implantation region, which is not specifically described herein.
specifically, by adopting a common technical means in the technical field, the trench second insulating oxide layer 10 is prepared in the cell second trench body 9, the trench second insulating oxide layer 10 is generally a silicon dioxide layer, and the trench second insulating oxide layer 10 covers the inner side wall and the bottom wall of the cell second trench body 9.
After the trench second insulating oxide layer 10 is prepared, a trench second conductive polysilicon substrate 11 is prepared in the cell second trench body 9 by a conventional technical means in the technical field, and the trench second conductive polysilicon substrate 11 is filled in the cell second trench body 9 and covers the mask layer 5, as shown in fig. 5.
After the mask layer 5 and the second conductive polysilicon substrate 11 covering the trench on the mask layer 5 are removed by a conventional technical means in the technical field, the second conductive polysilicon substrate 12 filled in the cell second trench 9 can be obtained.
For the specific relationship among the trench second conductive polysilicon body 12, the trench second insulating oxide layer 10 and the trench first conductive polysilicon body 8, reference may be made to the above description, and details are not repeated here.
And 5, preparing a required front electrode structure on the front surface of the GaN substrate, wherein the front electrode structure comprises source electrode metal and grid electrode metal, the grid electrode metal is electrically connected with the first conductive polycrystalline silicon body 8 of the groove, and the source electrode metal is electrically connected with the second conductive polycrystalline silicon body 12 of the groove.
Specifically, before the front electrode structure is prepared, the insulating medium layer 13 needs to be disposed on the front surface of the GaN substrate, and the process conditions and the process for specifically disposing the insulating medium layer 13 can be selected according to actual needs, which are not described herein again.
After the insulating dielectric layer 13 is prepared, it is necessary to prepare contact holes by using a conventional technical means in the technical field, the contact holes penetrate through the insulating dielectric layer 13, and a gate metal contact hole body and a source metal contact hole body can be respectively formed by using the contact holes, and the specific conditions of the gate metal contact hole body and the source metal contact hole body can refer to the above description, as shown in fig. 6.
After the gate metal contact hole body and the source metal contact hole body are prepared, metal layer deposition is performed on the insulating medium layer 13, so that source metal and gate metal can be prepared, where the gate metal is electrically connected to the trench first conductive polysilicon body 8, the source metal is electrically connected to the trench second conductive polysilicon body 12, the source metal corresponds to the electrical connection between the trench second conductive polysilicon body 12 and the barrier layer 3 through the source metal contact hole, and the electrical connection between the gate metal and the trench first conductive polysilicon body 8 through the gate metal contact hole, as shown in fig. 7, reference may be made to the above description.
In addition, a required back electrode process is carried out on the back surface of the GaN substrate to obtain a required back electrode structure. In particular, the specific conditions and processes of the back electrode process are related to the formed back electrode structure, which is well known in the art and will not be described herein.
Claims (10)
1. A GaN heterojunction vertical semiconductor device comprises a GaN substrate and a cellular region prepared in the central region of the GaN substrate, wherein the GaN substrate comprises a first conduction type drift region, the cellular region comprises a plurality of cellular units distributed in parallel, the cellular units in the cellular region adopt a groove structure, and cellular grooves of the cellular units are prepared in the first conduction type drift region; the method is characterized in that:
on the cross section of the vertical semiconductor device, the cell groove comprises a cell first groove body and a cell second groove body vertically penetrating through the cell first groove body, the width of the cell second groove body is smaller than that of the cell first groove body, and the groove bottom of the cell second groove body is positioned right below the groove bottom of the cell first groove body;
the second groove body is arranged in the second groove body of the cell, the second groove conductive polycrystalline silicon body is distributed along the length direction of the second groove body of the cell, and the second groove insulating oxide layer surrounds the second groove conductive polycrystalline silicon body of the groove; the first groove conductive polycrystalline silicon body is insulated and isolated from the inner side wall of the first groove body of the unit cell through a first groove insulating oxide layer covering the first groove body of the unit cell; the bottom of the second conductive polycrystalline silicon body of the groove is positioned right below the bottom of the first groove body of the cellular, and the second conductive polycrystalline silicon body of the groove is insulated and isolated from the first conductive polycrystalline silicon body of the groove and the first conductive type drift region through a second insulating oxide layer of the groove;
and arranging a front electrode structure above the front surface of the GaN substrate, wherein the front electrode structure comprises source electrode metal and grid electrode metal, the grid electrode metal is electrically connected with the first conductive polycrystalline silicon body of the groove, and the source electrode metal is electrically connected with the second conductive polycrystalline silicon body of the groove.
2. The GaN heterojunction vertical semiconductor device of claim 1, wherein: the GaN substrate further comprises a barrier layer arranged on the first conduction type drift region and a first conduction type heavily doped layer adjacent to the first conduction type drift region, and the doping concentration of the first conduction type heavily doped layer is greater than that of the first conduction type drift region; forming the front surface of the GaN substrate by using the corresponding surface of the barrier layer, and forming the back surface of the GaN substrate by using the corresponding surface of the first conductive type heavily doped layer;
the first groove body of the unit cell penetrates through the barrier layer, the groove bottom of the first groove body of the unit cell is positioned below the barrier layer, and the source metal is electrically connected with the barrier layer.
3. The GaN heterojunction vertical semiconductor device of claim 1, wherein: and a second conductive type injection region is arranged below the bottom of the second groove body of the cell, and the second conductive type injection region coats the bottom of the second groove body of the cell.
4. The GaN heterojunction vertical semiconductor device of claim 2, wherein: and the front surface of the GaN substrate is also provided with an insulating medium layer for supporting source metal and grid metal, the source metal is electrically connected with the second conductive polysilicon body of the groove and the barrier layer through a source metal contact hole body arranged in the insulating medium layer, and the grid metal is electrically connected with the first conductive polysilicon body of the groove through a grid metal contact hole body arranged in the insulating medium layer.
5. The GaN heterojunction vertical semiconductor device of any of claims 1 to 4, wherein: the GaN substrate further comprises a back electrode structure arranged on the back surface of the GaN substrate.
6. The GaN heterojunction vertical semiconductor device of claim 2, wherein: the barrier layer is an AlGaN layer, an AlN layer, an InN layer or an InGaN layer.
7. A preparation method of a GaN heterojunction vertical semiconductor device is characterized by comprising the following steps:
step 1, providing a GaN substrate, and preparing a first cell trench body in a first conduction type drift region of the GaN substrate, wherein the first cell trench body vertically extends downwards from the front surface of the GaN substrate to the first conduction type drift region;
step 2, arranging a first trench insulating oxide layer in the first trench body of the cell, and filling a first trench conductive polysilicon substrate in the first trench body of the cell, wherein the first trench conductive polysilicon substrate is insulated and isolated from the inner side wall and the bottom wall of the first trench body of the cell through the first trench insulating oxide layer;
step 3, selectively masking and etching the GaN substrate to prepare and obtain a required cell second groove body, wherein the cell second groove body penetrates through the cell first groove body, the width of the cell second groove body is smaller than that of the cell second groove body, the groove bottom of the cell second groove body is positioned right below the groove bottom of the cell first groove body, and the cell second groove body penetrates through a groove first conductive polycrystalline silicon substrate in the cell first groove body to obtain a required groove first conductive polycrystalline silicon body in the cell first groove body;
step 4, preparing a second conductive polysilicon body of the groove and a second insulating oxide layer of the groove in the second groove body of the cell, wherein the second conductive polysilicon body of the groove is distributed along the length direction of the second groove of the cell, the second insulating oxide layer of the groove surrounds and wraps the second conductive polysilicon body of the groove, and the second conductive polysilicon body of the groove is insulated and isolated from the first conductive polysilicon body of the groove and the drift region of the first conductive type through the second insulating oxide layer of the groove;
and 5, preparing a required front electrode structure on the front surface of the GaN substrate, wherein the front electrode structure comprises source electrode metal and grid electrode metal, the grid electrode metal is electrically connected with the first conductive polycrystalline silicon body of the groove, and the source electrode metal is electrically connected with the second conductive polycrystalline silicon body of the groove.
8. The method of fabricating a GaN heterojunction vertical semiconductor device of claim 7, wherein: the GaN substrate comprises a barrier layer arranged in the first conduction type drift region and a first conduction type heavily doped layer adjacent to the first conduction type drift region, and the doping concentration of the first conduction type heavily doped layer is greater than that of the first conduction type drift region; forming the front surface of the GaN substrate by utilizing the corresponding surface of the first conductive type drift region, and forming the back surface of the GaN substrate by utilizing the corresponding surface of the first conductive type heavily doped layer;
the first groove body of the unit cell penetrates through the barrier layer, the groove bottom of the first groove body of the unit cell is positioned below the barrier layer, and the source metal is in ohmic contact with the barrier layer.
9. The method of manufacturing a GaN heterojunction vertical semiconductor device according to claim 7 or 8, wherein: in step 3, after the second trench body of the cell is prepared, required second conductive type impurity ion implantation is performed on the front surface of the GaN substrate to obtain a second conductive type implantation region below the bottom of the second trench body of the cell, wherein the second conductive type implantation region coats the bottom of the second trench body of the cell.
10. The method of manufacturing a GaN heterojunction vertical semiconductor device according to claim 7 or 8, wherein: and carrying out a required back electrode process on the back of the GaN substrate to obtain a required back electrode structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210340841.1A CN115084219A (en) | 2022-04-02 | 2022-04-02 | GaN heterojunction vertical semiconductor device and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210340841.1A CN115084219A (en) | 2022-04-02 | 2022-04-02 | GaN heterojunction vertical semiconductor device and preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115084219A true CN115084219A (en) | 2022-09-20 |
Family
ID=83247821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210340841.1A Pending CN115084219A (en) | 2022-04-02 | 2022-04-02 | GaN heterojunction vertical semiconductor device and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115084219A (en) |
-
2022
- 2022-04-02 CN CN202210340841.1A patent/CN115084219A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9941403B2 (en) | Semiconductor device and method for manufacturing a semiconductor device | |
| US20180261666A1 (en) | Vertical power mos-gated device with high dopant concentration n-well below p-well and with floating p-islands | |
| KR101404906B1 (en) | Lateral power devices with self-biasing electrodes | |
| US7868394B2 (en) | Metal-oxide-semiconductor transistor and method of manufacturing the same | |
| US20090057713A1 (en) | Semiconductor device with a semiconductor body | |
| US20120261746A1 (en) | Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact | |
| JP2005510059A (en) | Field effect transistor semiconductor device | |
| CN107342326B (en) | Power semiconductor device capable of reducing on-resistance and manufacturing method thereof | |
| CN104247026A (en) | Silicon carbide semiconductor device and method for manufacturing same | |
| US20220320295A1 (en) | Sic mosfet structures with asymmetric trench oxide | |
| CN107611179A (en) | Reduce shield grid MOSFET structure of gate-source capacitance and preparation method thereof | |
| CN104659090A (en) | LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method | |
| CN107799602A (en) | Shielding grid MOSFET component of terminal area and preparation method thereof can be saved | |
| CN107731926B (en) | MOSFET device with improved voltage withstanding range and preparation method thereof | |
| CN107731908B (en) | Shielding gate MOSFET structure for improving voltage resistance and preparation method thereof | |
| CN115528115A (en) | LDMOS power device and preparation method thereof | |
| CN113809148B (en) | Power element and manufacturing method thereof | |
| CN113097311B (en) | Power semiconductor device with gate oxide optimization structure and manufacturing method | |
| CN113690293B (en) | IGBT device and preparation method thereof | |
| US11664434B2 (en) | Semiconductor power devices having multiple gate trenches and methods of forming such devices | |
| CN114497188A (en) | SGT device of high-reliability upper and lower structure | |
| CN115084219A (en) | GaN heterojunction vertical semiconductor device and preparation method | |
| CN113555414A (en) | Trench type silicon carbide field effect transistor and preparation method thereof | |
| CN104617139A (en) | Ldmos device and manufacturing method thereof | |
| CN114375499A (en) | Vertical field effect transistor and method for producing a vertical field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |