CN115084183A

CN115084183A - Micro light-emitting diode display chip and manufacturing method thereof

Info

Publication number: CN115084183A
Application number: CN202210777014.9A
Authority: CN
Inventors: 胡双元; 庄永漳
Original assignee: Laiyu Optoelectronic Technology Suzhou Co ltd; Gusu Laboratory of Materials
Current assignee: Laiyu Optoelectronic Technology Suzhou Co ltd; Gusu Laboratory of Materials
Priority date: 2022-07-06
Filing date: 2022-07-06
Publication date: 2022-09-20

Abstract

The invention discloses a micro light-emitting diode display chip and a manufacturing method thereof, wherein the micro light-emitting diode display chip comprises: a driving substrate having first and second surfaces opposite to each other; the LED epitaxial layer is bonded on the first surface of the driving substrate; and the stress compensation layer is bonded on the second surface of the driving substrate, and the LED epitaxial layer and the stress compensation layer respectively act on the stress of the driving substrate to be offset. According to the invention, the stress compensation layer is arranged on the other side of the driving substrate opposite to the LED epitaxial layer, so that the stress of the LED epitaxial layer on the driving substrate can be balanced, the warping problem caused by bonding can be completely eliminated, the bonding temperature and the process temperature after bonding are not limited, and the yield, the manufacturability and the device reliability are greatly improved.

Description

Micro light-emitting diode display chip and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor device manufacturing technology, and more particularly to a micro light emitting diode display chip (LED chip or micro chip) and a method for manufacturing the same.

Background

In the vertical structure LED chip manufacturing process, an epitaxial layer grown on a sapphire substrate or other substrates needs to be transferred to another substrate, and the original epitaxial substrate is removed, thereby achieving better performance. The substrate transfer technology is critical and is generally realized by adopting a metal bonding process. The mature high-reliability metal bonding process is generally at 300 ℃ or above, and because the difference between the thermal expansion coefficients of an epitaxial material (generally GaN) and a driving substrate is large, a new wafer formed after bonding can generate large warpage, so that the subsequent process has great problems, the yield is reduced, the production consistency is poor, equipment frequently alarms and the like.

With the further development of micro display application, the pixel size of the micro-processed is required to be smaller and smaller (< 5um), and if the micro-processed chip is bonded with the CMOS driving substrate in a traditional flip chip manner, the alignment precision exceeds the limit of the device, so people generally adopt the steps of bonding the micro-processed epitaxy with the CMOS and then adopting a semiconductor process to complete the chip manufacturing. Because the difference between the thermal expansion coefficients of the GaN epitaxial layer and the bonded CMOS substrate is large (the CMOS substrate is silicon, the thermal expansion coefficient is 2.6E-6/K, and the thermal expansion coefficient of GaN in the horizontal direction is 5.59E-6/K), after bonding and removing the epitaxial substrate, the bonded wafer can generate large warpage, which causes great influence on subsequent process, thus causing yield reduction, poor production consistency, frequent alarm of equipment and the like.

In the prior art, low-melting-point metal is introduced as an intermediate bonding layer to reduce bonding temperature, so that warpage after bonding is reduced, the warpage problem caused by bonding can be relieved to a certain extent, but the warpage problem caused by bonding is still not eliminated. Meanwhile, the reliability of devices with low-melting-point metal is poor, and the temperature of the subsequent production process is limited (generally, the bonding temperature cannot be exceeded)

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a micro light-emitting diode display chip and a manufacturing method thereof, which can overcome the problem of warping caused by bonding in the prior art.

To achieve the above object, an embodiment of the present invention provides a micro light emitting diode display chip, including:

a driving substrate having first and second surfaces opposite to each other;

the LED epitaxial layer is bonded on the first surface of the driving substrate; and

and the stress compensation layer is bonded on the second surface of the driving substrate, and the LED epitaxial layer and the stress compensation layer respectively act on the stress of the driving substrate to be offset.

In one or more embodiments, the thermal expansion coefficient of the stress compensation layer is the same as or close to that of the LED epitaxial layer, the temperature c1 for bonding the LED epitaxial layer and the first surface of the driving substrate is 300-500 ℃, and the temperature c2 for bonding the stress compensation layer and the second surface of the driving substrate is 300-500 ℃.

In one or more embodiments, the stress compensation layer and the LED epitaxial layer are made of the same material.

In one or more embodiments, the stress compensation layer is made of GaN material.

In one or more embodiments, a first metal bonding layer is arranged between the LED epitaxial layer and the driving substrate, a second metal bonding layer is arranged between the stress compensation layer and the driving substrate, and the first metal bonding layer and the second metal bonding layer are made of one or more materials selected from Au, Sn, Cu, Ti, Ni, or alloys thereof.

In one or more embodiments, the LED epitaxial layer forms a plurality of LED light emitting units arranged in an array by an isolation trench or an ion implantation isolation material, the driving substrate includes a driving circuit and a plurality of contacts electrically connected to the driving circuit, each LED light emitting unit corresponds to one contact, and the contacts drive the LED light emitting units.

In one or more embodiments, each of the LED lighting units includes:

the first doped semiconductor layer is formed on the first surface of the driving substrate;

a light emitting layer formed on the first doped semiconductor layer;

a second doped semiconductor layer formed on the light emitting layer,

the passivation layer is formed on the second doped semiconductor layer and provided with a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; and

and the electrode layer is formed on the passivation layer, is electrically connected with the second doped semiconductor layer through the first opening and is electrically connected with the contact through the second opening.

In one or more embodiments, the contact is electrically connected to the second doped semiconductor layer of each LED light emitting cell, and the contact is located between adjacent LED cells.

In one or more embodiments, the method further comprises: a plurality of vias penetrating the LED epitaxial layer and the first metal bonding layer, each via corresponding to one of the contacts, the contacts being exposed at the bottom of the via,

and the electrode layer is electrically connected with the second doped semiconductor layer and the contact through the through hole respectively.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a micro light emitting diode display chip, including:

forming an LED epitaxial layer on a growth substrate;

providing a driving substrate, wherein the driving substrate is provided with a first surface and a second surface which are opposite;

bonding the LED epitaxial layer and the first surface of the driving substrate;

providing a chip accompanying substrate, forming a stress compensation layer on the chip accompanying substrate, bonding the stress compensation layer and the second surface of the driving substrate, and respectively offsetting the stress of the LED epitaxial layer and the stress compensation layer on the driving substrate;

stripping the growth substrate and the wafer substrate;

the LED epitaxial layers are separated to form a plurality of LED light-emitting units which are arranged in an array, and the plurality of LED light-emitting units can be independently driven.

In one or more embodiments, the temperature c1 for bonding the LED epitaxial layers and the first surface of the driving substrate is 300-500 ℃; the temperature c2 for bonding the stress compensation layer and the second surface of the driving substrate is 300-500 ℃.

In one or more embodiments, the LED epitaxial layer and the first surface of the driving substrate are bonded, and then the stress compensation layer and the second surface of the driving substrate are bonded, wherein the temperature c2 is less than or equal to the temperature c 1; or, the stress compensation layer is bonded with the second surface of the driving substrate, and then the LED epitaxial layer is bonded with the first surface of the driving substrate, wherein the temperature c1 is less than or equal to the temperature c 2. In one or more embodiments, the stress compensation layer has a coefficient of thermal expansion that is the same as or close to the coefficient of thermal expansion of the LED epitaxial layers.

In one or more embodiments, the method of bonding the LED epitaxial layers and the first surface of the driving substrate includes:

forming a first bonding layer on the surface of the LED epitaxial layer;

forming a second bonding layer on the first surface of the driving substrate;

and the LED epitaxial layer and the driving substrate are bonded together through the first bonding layer and the second bonding layer, and the materials of the first bonding layer and the second bonding layer are selected from one or more of Au, Sn, Cu, Ti, Ni or alloys thereof.

In one or more embodiments, a method of bonding a stress compensation layer to a second surface of the driver substrate includes:

forming a third bonding layer on the surface of the stress compensation layer;

forming a fourth bonding layer on the second surface of the driving substrate;

and the stress compensation layer and the driving substrate are bonded together through the third bonding layer and the fourth bonding layer, and the third bonding layer and the fourth bonding layer are made of one or more materials selected from Au, Sn, Cu, Ti and Ni or alloys thereof.

In one or more embodiments, the method for separating the LED epitaxial layers to form a plurality of LED light emitting units arranged in an array comprises:

etching and forming an isolation groove between adjacent LED light-emitting units, or

And isolating materials are ion-implanted between the adjacent LED light-emitting units.

In one or more embodiments, the method for partitioning the LED epitaxial layer to form a plurality of LED light emitting units arranged in an array comprises: etching between adjacent LED light-emitting units to form an isolation groove; and thinning the stress compensation layer to balance the stress variation of the LED epitaxial layer.

In one or more embodiments, a method of forming LED epitaxial layers on a growth substrate includes:

forming a first doped semiconductor layer on the first surface of the driving substrate;

forming a light emitting layer on the first doping type semiconductor layer;

and forming a second doping type semiconductor layer on the light emitting layer.

In one or more embodiments, the driving substrate includes a driving circuit and a plurality of contacts electrically connected to the driving circuit, each LED light-emitting unit corresponds to one of the contacts,

the contact is electrically connected with the second doped semiconductor layer of each LED light-emitting unit, and the contact is positioned between the adjacent LED units.

In one or more embodiments, the method further comprises:

etching the LED epitaxial layer to form a plurality of through holes, wherein each through hole corresponds to one contact, and the bottom of each through hole exposes the contact;

forming a passivation layer on the second doped semiconductor layer and the side wall of the through hole, wherein the passivation layer is provided with a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; and

and forming an electrode layer on the passivation layer, wherein the electrode layer is electrically connected with the second doped semiconductor layer through the first opening and is electrically connected with the contact through the second opening.

In one or more embodiments, the LED epitaxial layer and the stress compensation layer are respectively faced to the first surface and the second surface of the driving substrate, so that bonding between the LED epitaxial layer and the stress compensation layer and the driving substrate simultaneously occurs.

Compared with the prior art, the stress compensation layer is arranged on the other side, opposite to the LED epitaxial layer, of the driving substrate, so that the stress of the LED epitaxial layer on the driving substrate can be balanced, the warping problem caused by bonding can be completely eliminated, the bonding temperature and the process temperature after bonding are not limited, and the yield, the manufacturability and the device reliability are greatly improved.

Drawings

FIG. 1 is a schematic diagram of a micro light emitting diode display chip according to embodiment 1 of the present invention;

FIGS. 2a to 2h are schematic diagrams illustrating intermediate structures for fabricating a micro light emitting diode display chip according to embodiment 2 of the present invention;

fig. 3a to fig. 3g are schematic intermediate structures for manufacturing a micro light emitting diode display chip according to embodiment 3 of the present invention.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

In general, terms may be understood based at least in part on contextual usage. For example, the term "one or more" as used herein may be used to describe any element, structure, or feature in the singular or may be used to describe a combination of elements, structures or features in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context.

It should be readily understood that the meaning of "on …", "above …" and "above …" in this application should be interpreted in the broadest sense such that "on …" means not only "directly on something", but also "on something" including the presence of an intermediate component or layer therebetween, and "on something" or "above something" means not only "on something" or "above something", but also the meaning of "on something" or "above something" without an intermediate component or layer therebetween.

The term "layer" as used herein refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a lesser extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or therebetween. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers above, and/or below it. One layer may comprise multiple layers.

Example 1

Referring to fig. 1, an embodiment of the present application provides a micro light emitting diode display chip 100, which includes a driving substrate 10, an LED epitaxial layer 20, and a stress compensation layer 30. Wherein the driving substrate 10 has a first surface 11 and a second surface 12 opposite to each other; the LED epitaxial layer 20 is bonded to the first surface 11 of the driving substrate 10; the stress compensation layer 30 is bonded to the second surface 12 of the driving substrate 10.

In order to avoid deformation of the driving substrate 10, the stresses applied to the driving substrate 10 by the LED epitaxial layers 20 and the stress compensation layers 30 are cancelled out.

In this technical solution, the LED epitaxial layer 20 and the stress compensation layer 30 respectively generate opposite stress actions on two sides of the driving substrate 10, and the stresses are cancelled out, so as to avoid warpage of the driving substrate 10 caused by different thermal expansion coefficients.

In an embodiment, the thermal expansion coefficient of the LED epitaxial layer 20 is greater than the thermal expansion coefficient of the driving substrate 10, and the LED epitaxial layer 20 acts on the first surface 11 of the driving substrate 10 to generate a first acting force for warping the driving substrate 10 toward the LED epitaxial layer 20; the thermal expansion coefficient of the stress compensation layer 30 is greater than that of the driving substrate 10, the stress compensation layer 30 acts on the second surface 12 of the driving substrate 10 to generate a second acting force for warping the driving substrate 10 towards the stress compensation layer 30, and the first acting force and the second acting force have substantially the same magnitude and cancel each other out to prevent the driving substrate 10 from deforming.

In a preferred embodiment, the thermal expansion coefficient and the thickness of the LED epitaxial layer 20 are close to those of the stress compensation layer 30, in other embodiments, the LED epitaxial layer 20 and the stress compensation layer 30 may also be made of materials with different thermal expansion coefficients, but the thickness required for stress compensation needs to be changed to satisfy the balance between the stresses applied to the driving substrate 10 by the LED epitaxial layer 20 and the stress compensation layer 30.

In a specific example, the LED epitaxial layer 20 is made of GaN material and has a thickness of 1um, and the stress compensation layer is made of GaN material and has a thickness of 1um consistent with the LED epitaxial layer 20.

In another specific example, the LED epitaxial layer 20 is made of GaN material and has a thickness of 1um, and the stress compensation layer 30 is made of Ge (CTE ═ 5.9E-6/K) and has a thickness of 0.95um thinner than the LED epitaxial layer 20.

In another specific example, the LED epitaxial layer 20 is made of GaN material and has a thickness of 1um, and the stress compensation layer 30 is made of InSb (CTE ═ 5.37E-6/K) and has a thickness of 1.04um thicker than the LED epitaxial layer 20.

In a preferred embodiment, a metal bonding process is used between the LED epitaxial layers 20 and the driving substrate 10. The bonding layer 40 is an adhesive material formed between the LED epitaxial layer 20 and the driving substrate 10, and in some embodiments, the bonding layer 40 is made of Au, Sn, Cu, Ti, Ni, or an alloy thereof.

In other embodiments, the bonding layer 40 may also be made of a non-metal material, such as Polyimide (PI), Polydimethylsiloxane (PDMS), photoresist, etc.

In one embodiment, the bonding layer 40 includes a first bonding layer 41 and a second bonding layer 42 bonded to the epitaxial layer 20 and the driving substrate 10, respectively, and the first bonding layer 41 and the second bonding layer 42 are bonded under certain temperature and pressure conditions. The materials of the first bonding layer 41 and the second bonding layer 42 may be the same or different.

In the technical scheme, because the driving substrate 10 does not generate warpage deformation under the balance action of the epitaxial function 20 and the stress compensation layer 30, the selection window of the bonding material and the bonding temperature of the bonding layer 40 is larger, for example, the bonding process can be carried out under the high-temperature condition of 300-500 ℃ and is not easy to generate warpage, and the temperature condition also meets the temperature window of the process after bonding, so that the yield is ensured, the difficulty of the subsequent process is reduced, and the product obtained by the bonding method can be applied to a high-temperature environment and has high reliability.

In a preferred embodiment, a metal bonding process is used between the stress compensation layer 30 and the driving substrate 10. The bonding layer 50 is an adhesive material formed between the stress compensation layer 30 and the driving substrate 10, and in some embodiments, the bonding layer 50 is made of Au, Sn, Cu, Ti, Ni, or an alloy thereof.

In other embodiments, the bonding layer 50 may also be made of a non-metal material, such as Polyimide (PI), Polydimethylsiloxane (PDMS), photoresist, etc.

In one embodiment, the bonding layer 50 includes a third bonding layer 51 and a fourth bonding layer 52 bonded to the stress compensation layer 30 and the driving substrate 10, respectively, and the third bonding layer 51 and the fourth bonding layer 52 are bonded under certain temperature and pressure conditions. The materials of the third bonding layer 51 and the fourth bonding layer 52 may be the same or different.

In this technical scheme, since the driving substrate 10 does not undergo warpage deformation under the balance action of the epitaxy function 20 and the stress compensation layer 30, the selection window for the bonding material and the bonding temperature of the bonding layer 50 is larger, and the yield is greatly improved.

In an embodiment, the LED epitaxial layer 20 forms a plurality of LED light emitting units 21 in a convex plate structure arranged in an array through the isolation groove 210, and the isolation groove 210 is formed between adjacent LED light emitting units 21, so that the LED light emitting units 21 are independent from each other.

In another embodiment, the separation of different LED light emitting units 21 can also be realized by ion implantation of isolation materials between the LED light emitting units 21. In some embodiments, the ion implantation region (not shown) may be formed by implanting H +, He +, N +, O +, F +, Mg +, Si +, Ar +, or the like ions in the LED epitaxial layer 20. In some embodiments, the LED epitaxial layers 20 may be implanted with one or more ions to form an ion implanted region. The ion implanted region has physical characteristics of electrical insulation after ion implantation.

The driving substrate 10 includes a driving circuit and a plurality of contacts 13 electrically connected to the driving circuit, each LED light-emitting unit 21 corresponds to one of the contacts 13, and the contacts 13 drive the LED light-emitting units.

Each LED light emitting unit 21 includes a first doped semiconductor layer 213, a light emitting layer 212, a second doped semiconductor layer 211 and a passivation layer 214 sequentially formed on the first surface 11 of the driving substrate 10, wherein the passivation layer 214 is provided with a first opening 2141 exposing the second doped semiconductor layer 211 and a second opening 2142 exposing the contact 13. Each LED light emitting unit 21 further includes an electrode layer 215 formed on the passivation layer 214, and the electrode layer 215 is in contact with the second doped semiconductor layer 211 through a first opening 2141 on the passivation layer 214 and is electrically connected to the contact 13 through a second opening 2142 on the passivation layer 214. The contact 13 is located at a gap between adjacent LED units 21 and electrically connected to the second doped semiconductor layer 211 of one of the LED light emitting units 21 through the electrode layer 215. In some embodiments of the present invention, the second doped semiconductor layer 211 forms a cathode of each LED light emitting cell 21, and thus the contact 13 supplies a driving voltage corresponding to each LED cell 21 from a driving circuit to the second doped semiconductor layer 211 through the electrode layer 215.

In some embodiments, the first doped semiconductor layer 213 may be p-type GaN. In some embodiments, the first doping type semiconductor layer 213 may be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213 may be p-type InGaN. In some embodiments, the first doping type semiconductor layer 213 may also be p-type AlInGaP.

In some embodiments, the second doped semiconductor layer 211 may be an n-type semiconductor layer and form a cathode of each LED light emitting unit. In some embodiments, the second doped semiconductor layer 211 may be n-type GaN. In some embodiments, the second doped semiconductor layer 211 may be n-type InGaN. In some embodiments, the second doped semiconductor layer 211 may also be n-type AlInGaP. The second doped semiconductor layers 211 of different LED light emitting cells are electrically isolated, and thus each LED light emitting cell may have a cathode with a voltage level different from that of other cells.

The light emitting layer 212 is an active region of the LED light emitting unit, and has a multiple quantum well structure, for example, composed of gan/ingan/algan. In some embodiments, the thickness of the first and second doping type semiconductor layers 213 and 211 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness including the first doped semiconductor layer 213, the light emitting layer 212, and the second doped semiconductor layer 211 may be between about 0.4 μm to about 4 μm.

The passivation layer 214 may be used to protect and isolate the LED lighting units, and the passivation layer 214 may comprise polyimide, SU-8 photoresist, or other photo-patternable polymer.

The electrode layer 215 may use a conductive material such as Indium Tin Oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.

The LED epitaxial layer 20 and the bonding layer 40 are also penetratingly formed with a through hole 22 in order to facilitate electrical connection of the electrode layer 215 with the second doping type semiconductor layer 211 and the contact 13, respectively. Each through hole 22 corresponds to one of the contacts 13, the bottom of the through hole 22 exposes the contact 13, and the electrode layer 215 is electrically connected to the second doped semiconductor layer 211 and the contact 13 through the through hole 22.

In this case, each contact 13 is correspondingly connected to the second doped semiconductor layer 211 of one LED light emitting unit 21, so that each LED light emitting unit 21 is independently controlled. The first doping type semiconductor layer 213 extends between the plurality of LED light emitting units 21, implementing a common electrode.

Example 2

According to the method for manufacturing the micro light-emitting diode display chip of the embodiment of the invention, the light-emitting diode structure shown in fig. 1 is manufactured by bonding the LED epitaxial layer and the stress compensation layer with the driving substrate in sequence, and the method specifically includes the following steps.

Step S110: referring to fig. 2a, a growth substrate 60 is provided, and LED epitaxial layers 20 are formed on the growth substrate 60. The LED epitaxial layer 20 includes a second doping type semiconductor layer 211, a light emitting layer 212, and a first doping type semiconductor layer 213 which are sequentially grown on the growth substrate 60.

The growth substrate 60 includes, but is not limited to, one of a mirror or micro/nano patterned sapphire substrate, and may also be a gallium arsenide, indium phosphide, gallium oxide, silicon carbide, silicon, zinc oxide, lithium gallate single crystal substrate, or a refractory metal substrate.

The first doped semiconductor layer 213 may be p-type GaN. In some embodiments, the first doping type semiconductor layer 213 may be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213 may be p-type InGaN. In some embodiments, the first doping type semiconductor layer 213 may also be p-type AlInGaP.

The light emitting layer 212 is used as an active region and has a multiple quantum well structure, which is composed of, for example, gan/ingan/algan material. In some embodiments, the thickness of the semiconductor layer including the first and second doped

semiconductor layers

213 and 211 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the first doping type semiconductor layer 213, the light emitting layer 212, and the second doping type semiconductor layer 211 may be between about 0.4 μm and about 4 μm.

The second doping type semiconductor layer 211 may be an n-type semiconductor layer and form a cathode of each LED light emitting cell. In some embodiments, the second doped semiconductor layer 211 may be n-type GaN. In some embodiments, the second doped semiconductor layer 211 may be n-type InGaN. In some embodiments, the second doped semiconductor layer 211 may also be n-type AlInGaP.

Step 120: referring to fig. 2b, a first bonding layer 41 is formed on the surface of the LED epitaxial layer 20.

The material of the first bonding layer 41 is Au, Sn, Cu, Ti, Ni, or an alloy thereof.

Step 130: referring to fig. 2c, a driving substrate 10 is provided, the driving substrate 10 has a first surface 11 and a second surface 12 opposite to each other, and a second bonding layer 42 is formed on the first surface 11 of the driving substrate 10.

The driving substrate 10 includes a driving circuit (not shown) and a plurality of contacts 13 electrically connected to the driving circuit.

The material of the second bonding layer 42 is Au, Sn, Cu, Ti, Ni or an alloy thereof.

Step 140: referring to fig. 2d, the first bonding layer 41 and the second bonding layer 42 are attached, and metal surface bonding is performed under heating and a certain pressure. The bonding adopts high-temperature bonding, and the bonding temperature is controlled to be 300-500 ℃.

In the process after bonding, in order to ensure the yield, the temperature of other processes needs to be lower than the bonding temperature. In the scheme, high-temperature bonding is adopted in bonding, and the bonding temperature reaches more than 300 ℃, so that other processes have larger temperature selection windows and small temperature limitation in the process procedure after bonding, and the yield, manufacturability and reliability of the device are greatly improved.

Meanwhile, the bonding temperature is not too high, such as more than 500 ℃, which may affect the yield of the device. In some preferred embodiments, the bonding temperature may be 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, etc.

Step 150: referring to fig. 2e, a fourth bonding layer 52 is formed on the second surface 12 of the driving substrate 10.

The fourth bonding layer 52 is made of Au, Sn, Cu, Ti, Ni, or an alloy thereof.

Step 160: referring to fig. 2f, a chip substrate 70 is provided, and the stress compensation layer 30 and the third bonding layer 51 are formed on the chip substrate 70.

The companion substrate 70 substrate may be a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the cosheet substrate 70 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The thermal expansion coefficient and the thickness of the stress compensation layer 30 are close to those of the LED epitaxial layer 20, in other embodiments, the LED epitaxial layer 20 and the stress compensation layer 30 may also be made of materials with different thermal expansion coefficients, but the thickness required for stress compensation needs to be changed to satisfy the balance between the stresses applied to the driving substrate 10 by the LED epitaxial layer 20 and the stress compensation layer 30.

The third bonding layer 51 is made of Au, Sn, Cu, Ti, Ni, or an alloy thereof.

Step 170: referring to fig. 2g, the third bonding layer 51 and the fourth bonding layer 52 are attached, and metal surface bonding is performed under heat and pressure. The bonding adopts high-temperature bonding, the bonding temperature is controlled to be 300-500 ℃, and the bonding temperature in the step is less than or equal to the bonding temperature in the step 140.

Step 180: referring to fig. 2h, the growth substrate 60 and the cosheet substrate 70 are peeled off.

Step 190: referring to fig. 1, a plurality of mesa structures are formed on the LED epitaxial layer 20, and a passivation layer 214 and an electrode layer 215 are formed on the second doped semiconductor layer 211. The plurality of boss structures divide the LED epitaxial layer 20 into a plurality of LED light emitting units 21 arranged in an array, and the plurality of LED light emitting units 21 can be independently driven.

The method for forming the plurality of boss structures on the LED epitaxial layer 20 may be to form the isolation grooves 210 by etching, and the isolation grooves 210 are formed between the adjacent LED light emitting units 21, so that the LED light emitting units 21 are independent from each other.

Because the stress of the LED epitaxial layer is easy to change in the process of etching the isolation groove 210 or other chip processes, the stress change of the front LED epitaxial layer can be matched by reducing the thickness of the stress compensation layer, so that the bonded wafer is ensured not to warp, and the yield of products is improved.

The method of forming the plurality of mesa structures on the LED epitaxial layer 20 may also be by ion implantation of an isolation material. In some embodiments, the ion implantation region (not shown) may be formed by implanting H +, He +, N +, O +, F +, Mg +, Si +, Ar +, or the like ions in the LED epitaxial layer 20. In some embodiments, the LED epitaxial layers 20 may be implanted with one or more ions to form an ion implanted region. The ion implanted region has physical characteristics of electrical insulation after ion implantation.

The electrode layer 215 is in contact with the second doped semiconductor layer 211 through the opening on the passivation layer 214.

In the manufacturing process of the LED chip, the stress of the LED epitaxial layer is changed due to the manufacturing process, and the stress change of the LED epitaxial layer on the front side can be matched by reducing the thickness of the stress compensation layer, so that the bonded wafer is ensured not to warp.

Example 3

According to the method for manufacturing the micro light-emitting diode display chip of the embodiment of the invention, the light-emitting diode structure shown in fig. 1 is manufactured by bonding the LED epitaxial layer and the stress compensation layer with the driving substrate in sequence.

In this embodiment, the driving substrate 10 and the die attach substrate 70 are metal bonded first, and then the driving substrate 10 and the LED epitaxial layer 20 are bonded, except for the sequence of steps, the steps are the same as those in embodiment 2, and are not described again.

Example 4

According to the method for manufacturing the micro light-emitting diode display chip of the embodiment of the invention, the light-emitting diode structure shown in fig. 1 is manufactured by adopting a mode that the LED epitaxial layer and the stress compensation layer are bonded with the driving substrate at the same time, and the method specifically comprises the following steps.

Step S210: referring to fig. 3a, a growth substrate 60 ' is provided, and LED epitaxial layers 20 ' are formed on the growth substrate 60 '. The LED epitaxial layer 20 ' includes a second doping type semiconductor layer 211 ', a light emitting layer 212 ', and a first doping type semiconductor layer 213 ' sequentially grown on a growth substrate 60 '.

The growth substrate 60' includes, but is not limited to, one of a mirror or micro/nano patterned sapphire substrate, and may also be a gallium arsenide, indium phosphide, gallium oxide, silicon carbide, silicon, zinc oxide, lithium gallate single crystal substrate, or a high temperature resistant metal substrate.

The first doping type semiconductor layer 213' may be p-type GaN. In some embodiments, the first doping type semiconductor layer 213' may be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213' may be p-type InGaN. In some embodiments, the first doping type semiconductor layer 213' may also be p-type AlInGaP.

The light emitting layer 212' is used as an active region and has a multiple quantum well structure, which is composed of, for example, gan/ingan/algan material. In some embodiments, the thickness of the semiconductor layer including the first and second doped semiconductor layers 213 'and 211' may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the light emitting layer 212 ', including the first doped semiconductor layer 213 ', and the second doped semiconductor layer 211 ' may be between about 0.4 μm and about 4 μm.

The second doping type semiconductor layer 211' may be an n-type semiconductor layer and form a cathode of each LED light emitting cell. In some embodiments, the second doping type semiconductor layer 211' may be n-type GaN. In some embodiments, the second doped semiconductor layer 211' may be n-type InGaN. In some embodiments, the second doping type semiconductor layer 211' may also be n-type AlInGaP.

Step 220: referring to fig. 3b, a first bonding layer 41 'is formed on the surface of the LED epitaxial layer 20'.

The material of the first bonding layer 41' is Au, Sn, Cu, Ti, Ni or an alloy thereof.

Step 230: referring to fig. 3c, a driving substrate 10 ' is provided, the driving substrate 10 ' has a first surface 11 ' and a second surface 12 ' opposite to each other, and a second bonding layer 42 ' is formed on the first surface 11 ' of the driving substrate 10 '. A fourth bonding layer 52 ' is formed on the second surface 12 ' of the driving substrate 10 '.

The driving substrate 10 'includes a driving circuit (not shown) and a plurality of contacts 13' electrically connected to the driving circuit.

The driving substrate 10' is selected from one of silicon, copper, molybdenum, tungsten, molybdenum-copper alloy, tungsten-copper alloy and aluminum-silicon alloy substrate. In order to manufacture a micro LED display, the driving substrate 10' may also be a display substrate of a CMOS backplane or a TFT glass substrate.

The material of the second bonding layer 42' is Au, Sn, Cu, Ti, Ni or an alloy thereof.

The fourth bonding layer 52' is made of Au, Sn, Cu, Ti, Ni, or an alloy thereof.

Step 240: referring to fig. 3d, a chip substrate 70 'is provided, and the stress compensation layer 30' and the third bonding layer 51 'are formed on the chip substrate 70'.

The substrate 70' may be a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the cosheet substrate 70' may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The thermal expansion coefficient and the thickness of the stress compensation layer 30 ' are close to those of the LED epitaxial layer 20 ', and in other embodiments, the LED epitaxial layer 20 ' and the stress compensation layer 30 ' may also be made of materials with different thermal expansion coefficients, but the thickness required for stress compensation needs to be changed to satisfy the balance between the stresses applied to the driving substrate 10 ' by the LED epitaxial layer 20 ' and the stress compensation layer 30 '.

In a specific example, the LED epitaxial layer 20 ' is made of GaN material and has a thickness of 1um, and the stress compensation layer 30 ' is made of GaN material and has a thickness of 1um, which is consistent with the LED epitaxial layer 20 '.

In another specific example, the LED epitaxial layer 20 ' is made of GaN material and has a thickness of 1um, and the stress compensation layer 30 ' is made of Ge (CTE 5.9E-6/K) and has a thickness of 0.95um thinner than the LED epitaxial layer 20 '.

In another specific example, the LED epitaxial layer 20 ' is made of GaN material and has a thickness of 1um, and the stress compensation layer 30 ' is made of InSb (CTE 5.37E-6/K) and has a thickness of 1.04um thicker than the LED epitaxial layer 20 '.

The third bonding layer 51' is made of Au, Sn, Cu, Ti, Ni or alloy thereof.

Step 250: referring to fig. 3e, the first bonding layer 41 'and the second bonding layer 42' are bonded, the third bonding layer 51 'and the fourth bonding layer 52' are bonded, and bonding between the driving substrate 10 'and the LED epitaxial layer 20' and bonding between the driving substrate 10 'and the stress compensation layer 30' are simultaneously achieved under heating and certain pressure conditions.

In this step, the bonding between the first bonding layer 41 'and the second bonding layer 42' and the bonding between the third bonding layer 51 'and the fourth bonding layer 52' are performed simultaneously, and the bonding temperatures are the same, and are both 300 ℃ to 500 ℃.

In the process after bonding, in order to ensure the yield, the temperature of other processes needs to be lower than the bonding temperature. In the scheme, high-temperature bonding is adopted for bonding, and the bonding temperature reaches more than 300 ℃, so that other processes have larger temperature selection windows and small temperature limitation in the process procedure after bonding, the yield is ensured, the difficulty of the subsequent process is reduced, and the product obtained by the bonding method can be applied to a high-temperature environment and has high reliability.

Step 260: referring to fig. 3f, the growth substrate 60 'and the cosheet substrate 70' are peeled off.

Step 370: referring to fig. 3g, a plurality of mesa structures are formed on the LED epitaxial layer 20 ', and a passivation layer 214' and an electrode layer 215 'are formed on the second doping type semiconductor layer 211'. The plurality of boss structures separate the LED epitaxial layers 20 ' to form a plurality of LED light emitting units 21 ' arranged in an array, and the plurality of LED light emitting units 21 ' can be independently driven.

The method for forming a plurality of boss structures on the LED epitaxial layer 20 ' may be to form the isolation grooves 210 ' by etching, wherein the isolation grooves 210 ' are formed between adjacent LED light emitting units 21 ' so that the LED light emitting units 21 ' are independent from each other.

Because the stress of the LED epitaxial layer is likely to change during the etching of the isolation trench 210 or other chip processes, the stress change of the front LED epitaxial layer can be matched by reducing the thickness of the stress compensation layer, thereby ensuring that the bonded wafer does not warp.

The method of forming the plurality of mesa structures on the LED epitaxial layer 20' may also be by ion implantation of an isolation material. In some embodiments, an ion implantation region (not shown) may be formed by implanting H +, He +, N +, O +, F +, Mg +, Si +, or Ar + ions, etc. in the LED epitaxial layer 20'. In some embodiments, the LED epitaxial layers 20' may be implanted with one or more ions to form an ion implanted region. The ion implanted region has physical characteristics of electrical insulation after ion implantation.

The electrode layer 215 ' contacts the second doped semiconductor layer 211 ' through the opening on the passivation layer 214 '.

The passivation layer 214 'may be used to protect and isolate the LED lighting units, and the passivation layer 214' may comprise polyimide, SU-8 photoresist, or other photo-patternable polymer.

The electrode layer 215' may employ a conductive material such as Indium Tin Oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.

In summary, in the LED chip structure of this embodiment, due to the existence of the stress compensation layer on the back of the driving substrate, the bonded wafer is ensured to be always in a stress balance state, the wafer warpage generated by bonding is completely eliminated, the manufacturability and yield of the device are greatly improved, and meanwhile, the original high-reliability bonding mode is not changed, and the reliability of the device is not affected.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A micro light emitting diode display chip, comprising:

a driving substrate having first and second surfaces opposite to each other;

2. The micro light emitting diode display chip of claim 1, wherein the stress compensation layer has a thermal expansion coefficient the same as or close to that of the LED epitaxial layer, the temperature c1 for bonding the LED epitaxial layer to the first surface of the driving substrate is 300 ℃ to 500 ℃, and the temperature c2 for bonding the stress compensation layer to the second surface of the driving substrate is 300 ℃ to 500 ℃.

3. The micro light-emitting diode display chip of claim 2, wherein the stress compensation layer and the LED epitaxial layer are made of the same material.

4. The micro light-emitting diode display chip of claim 3, wherein the stress compensation layer is made of GaN material.

5. The micro light emitting diode display chip of claim 1, wherein the LED epitaxial layers and the driving substrate have a first metal bonding layer therebetween,

a second metal bonding layer is arranged between the stress compensation layer and the driving substrate,

the first metal bonding layer and the second metal bonding layer are made of one or more materials selected from Au, Sn, Cu, Ti, Ni or alloys thereof.

6. The micro light emitting diode display chip of claim 5, wherein the LED epitaxial layer forms a plurality of LED light emitting cells arranged in an array by an isolation trench or ion implantation of an isolation material,

the driving substrate comprises a driving circuit and a plurality of contacts electrically connected with the driving circuit, each LED light-emitting unit corresponds to one contact, and the contacts drive the LED light-emitting units.

7. The micro light emitting diode display chip of claim 6, wherein the contacts are located between adjacent ones of the LED light emitting cells, each of the LED light emitting cells comprising:

the first doped semiconductor layer is positioned on the first surface of the driving substrate;

a light emitting layer formed on the first doped semiconductor layer;

a second doped semiconductor layer formed on the light emitting layer;

the first doped semiconductor layers of the adjacent LED light-emitting units are connected with each other;

and the electrode layer is formed on the passivation layer, is electrically connected with the second doped semiconductor layer through the first opening and is electrically connected with the contact through the second opening, so that the contact is electrically connected with the second doped semiconductor layer of the corresponding LED light-emitting unit.

8. The micro light-emitting diode display chip of claim 7, further comprising: the through holes penetrate through the LED epitaxial layer and the first metal bonding layer, each through hole corresponds to one contact, and the contacts are exposed at the bottoms of the through holes.

9. A manufacturing method of a micro light-emitting diode display chip is characterized by comprising the following steps:

providing an LED epitaxial layer, wherein the LED epitaxial layer is formed on a growth substrate;

bonding an LED epitaxial layer and the first surface of the driving substrate, wherein a first metal bonding layer is arranged between the LED epitaxial layer and the driving substrate;

providing a chip accompanying substrate, forming a stress compensation layer on the chip accompanying substrate, bonding the stress compensation layer with the second surface of the driving substrate, and arranging a second metal bonding layer between the stress compensation layer and the driving substrate;

the LED epitaxial layer and the stress compensation layer respectively act on the stress of the driving substrate to be offset;

stripping the growth substrate and the wafer substrate;

10. The method for manufacturing the micro light-emitting diode display chip according to claim 9, wherein the bonding temperature c1 of the LED epitaxial layer and the first surface of the driving substrate is 300 ℃ -500 ℃;

the temperature c2 for bonding the stress compensation layer and the second surface of the driving substrate is 300-500 ℃.

11. The method of claim 10, wherein bonding the LED epitaxial layer to the first surface of the driving substrate is performed before bonding the stress compensation layer to the second surface of the driving substrate, wherein the temperature c2 is less than or equal to c 1; or, the stress compensation layer is bonded with the second surface of the driving substrate, and then the LED epitaxial layer is bonded with the first surface of the driving substrate, wherein the temperature c1 is less than or equal to the temperature c 2.

12. The method of claim 9, wherein the stress compensation layer has a thermal expansion coefficient that is the same as or close to the thermal expansion coefficient of the LED epitaxial layer.

13. The method of claim 9, wherein the bonding of the LED epitaxial layer to the first surface of the driving substrate comprises:

forming a first bonding layer on the surface of the LED epitaxial layer;

forming a second bonding layer on the first surface of the driving substrate;

the LED epitaxial layer and the driving substrate are bonded together through the first bonding layer and the second bonding layer, and the materials of the first bonding layer and the second bonding layer are selected from one or more of Au, Sn, Cu, Ti, Ni or alloys thereof.

14. The method of claim 9, wherein the step of bonding the stress compensation layer to the second surface of the driving substrate comprises:

forming a third bonding layer on the surface of the stress compensation layer;

forming a fourth bonding layer on the second surface of the driving substrate;

15. The method for manufacturing a micro light-emitting diode display chip according to claim 9, wherein the method for partitioning the LED epitaxial layer to form a plurality of LED light-emitting units arranged in an array comprises:

And ion implantation of an isolation material between the adjacent LED light-emitting units.

16. The method for manufacturing a micro light-emitting diode display chip according to claim 9, wherein the method for partitioning the LED epitaxial layer to form a plurality of LED light-emitting units arranged in an array comprises:

etching between adjacent LED light-emitting units to form an isolation groove;

and thinning the stress compensation layer to balance the stress variation of the LED epitaxial layer.

17. The method of claim 9, wherein each of the LED light units comprises:

a light emitting layer formed on the first doped semiconductor layer;

a second doped semiconductor layer formed on the light emitting layer;

18. The method of claim 17, wherein the first doped semiconductor layers of adjacent LED light units are connected to each other,

the contact is electrically connected with the second doped semiconductor layer of the corresponding LED light-emitting unit, and the contact is positioned between the adjacent LED units;

forming a passivation layer on the second doped semiconductor layer, wherein the passivation layer is provided with a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; and

19. The method of claim 9, wherein the LED epitaxial layer and the stress compensation layer are respectively disposed to face the first surface and the second surface of the driving substrate, such that the LED epitaxial layer and the stress compensation layer are simultaneously bonded to the driving substrate.