CN114388673B - Micro light-emitting diode chip and preparation method thereof - Google Patents
Micro light-emitting diode chip and preparation method thereof Download PDFInfo
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- CN114388673B CN114388673B CN202111489498.9A CN202111489498A CN114388673B CN 114388673 B CN114388673 B CN 114388673B CN 202111489498 A CN202111489498 A CN 202111489498A CN 114388673 B CN114388673 B CN 114388673B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000003466 welding Methods 0.000 claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 229910000679 solder Inorganic materials 0.000 claims description 35
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 17
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 306
- 239000004065 semiconductor Substances 0.000 description 56
- 238000002161 passivation Methods 0.000 description 29
- 229910052594 sapphire Inorganic materials 0.000 description 13
- 239000010980 sapphire Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 229910045601 alloy Inorganic materials 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
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- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present disclosure provides a micro light emitting diode chip and a preparation method thereof, which belong to the technical field of photoelectron manufacturing. The micro light emitting diode chip includes: the LED lamp comprises a substrate, a light-emitting structure, a first welding spot block, a second welding spot block and a buffer structure; the first welding spot block and the second welding spot block are respectively connected with two electrodes of the light-emitting structure; the first welding spot blocks and the second welding spot blocks are distributed at intervals, the buffer structure is located between the first welding spot blocks and the second welding spot blocks, the buffer structure is partially embedded into the first welding spot blocks, the buffer structure is partially embedded into the second welding spot blocks, and the first welding spot blocks and the second welding spot blocks are insulated from the buffer structure. The embodiment of the disclosure can solve the problem that the area between two welding spot blocks on the chip is deformed due to stress, and ensure the luminous effect of the chip.
Description
Technical Field
The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular, to a micro light emitting diode chip and a method for manufacturing the same.
Background
The Micro light emitting diode (Micro Light Emitting Diode, micro LED) is an ultra-small light emitting diode with a side length of 10-100 μm, has small volume, can be arranged more densely to greatly improve resolution, has self-luminous property, and has the characteristics of high brightness, high contrast, high reactivity and power saving.
In the related art, a micro light emitting diode chip generally includes a substrate, an epitaxial structure, a first electrode, a second electrode, a passivation layer, a first pad and a second pad, wherein the epitaxial structure is laminated on one surface of the substrate, the first electrode and the second electrode are located on the other surface of the epitaxial structure, the first electrode and the second electrode are respectively connected with an n-type layer and a p-type layer in the epitaxial structure, the passivation layer is located on the first electrode and the second electrode, the first pad and the second pad are located on the passivation layer, and the first pad and the second pad are respectively connected with two electrodes.
Because the first welding spot blocks and the second welding spot blocks are arranged on the surface of the passivation layer at intervals, and in the using process of the chip, the two welding spot blocks can receive larger pressure, the area between the two welding spot blocks is promoted to deform, and the luminous effect and the reliability of the chip are further affected.
Disclosure of Invention
The embodiment of the disclosure provides a miniature light-emitting diode chip and a preparation method thereof, which can solve the problem that the area between two welding spot blocks on the chip is deformed due to stress, and ensure the light-emitting effect of the chip. The technical scheme is as follows:
in one aspect, embodiments of the present disclosure provide a micro light emitting diode chip, the micro light emitting diode chip comprising: the LED lamp comprises a substrate, a light-emitting structure, a first welding spot block, a second welding spot block and a buffer structure; the light-emitting structure is positioned on the surface of the substrate, the first welding spot block, the second welding spot block and the buffer structure are positioned on the surface of the light-emitting structure, which is far away from the substrate, and the first welding spot block and the second welding spot block are respectively connected with two electrodes of the light-emitting structure; the first welding spot blocks and the second welding spot blocks are distributed at intervals, the buffer structure is located between the first welding spot blocks and the second welding spot blocks, the buffer structure is partially embedded into the first welding spot blocks and partially embedded into the second welding spot blocks, and the first welding spot blocks and the second welding spot blocks are insulated from the buffer structure.
Optionally, a side surface of the first welding spot block, which is close to the buffer structure, is provided with a first embedded groove, a side surface of the second welding spot block, which is close to the buffer structure, is provided with a second embedded groove, and the buffer structure is located in the first embedded groove and the second embedded groove.
Optionally, gaps are formed between the buffer structure and the groove walls of the first embedded groove and between the buffer structure and the groove walls of the second embedded groove; or, gaps are formed between the buffer structure and the groove walls of the first embedded groove and between the buffer structure and the groove walls of the second embedded groove, and an insulating layer is arranged in the gaps.
Optionally, the buffer structure includes a plurality of buffer bars, and a plurality of buffer bars are parallel to each other at intervals, and a plurality of respective two ends of the buffer bars are respectively embedded into the first welding spot block and the second welding spot block.
Optionally, the buffer structure includes a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially stacked on a surface of the light emitting structure.
Optionally, in the buffer structure, the thickness of the Cr layer is 50 to 150 a, the thickness of the Al layer is 2500 to 3500 a, the thickness of the Ti layer is 300 to 700 a, the thickness of the Ni layer is 6000 to 7000 a, and the thickness of the Sn alloy layer is 85000 to 86000 a.
Optionally, the first solder bump block and the second solder bump block each include a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially laminated on the surface of the light emitting structure.
Optionally, in the first solder joint block, the thickness of the Cr layer is 50 to 150 angstroms, the thickness of the Al layer is 2500 to 3500 angstroms, the thickness of the Ti layer is 300 to 700 angstroms, the thickness of the Ni layer is 1500 to 2500 angstroms, and the thickness of the Sn alloy layer is 89500 to 90500 angstroms; in the second solder joint block, the thickness of the Cr layer is 50-150 angstroms, the thickness of the Al layer is 2500-3500 angstroms, the thickness of the Ti layer is 300-700 angstroms, the thickness of the Ni layer is 1500-2500 angstroms, and the thickness of the Sn alloy layer is 89500-90500 angstroms.
On the other hand, the embodiment of the disclosure also provides a preparation method of the micro light emitting diode chip, which comprises the following steps: providing a substrate; forming a light emitting structure on the substrate; forming a first welding spot block, a second welding spot block and a buffer structure on the surface of the light-emitting structure, which is far away from the substrate, wherein the first welding spot block and the second welding spot block are respectively connected with two electrodes of the light-emitting structure; the first welding spot blocks and the second welding spot blocks are distributed at intervals, the buffer structure is located between the first welding spot blocks and the second welding spot blocks, a first part of the buffer structure is embedded into the first welding spot blocks, a second part of the buffer structure is embedded into the second welding spot blocks, and the first welding spot blocks and the second welding spot blocks are insulated from the buffer structure.
Optionally, forming the buffer structure on the surface of the substrate away from the light emitting structure includes: etching the first welding spot block, forming a plurality of first embedded grooves on the first welding spot block, etching the second welding spot block, forming a plurality of second embedded grooves on the second welding spot block, wherein the first embedded grooves extend to the side surfaces of the first welding spot block opposite to the second welding spot block, the second embedded grooves extend to the side surfaces of the second welding spot block opposite to the first welding spot block, and the first embedded grooves and the second embedded grooves are in one-to-one correspondence; evaporating and forming a metal layer on the surface of the light-emitting structure; etching the metal layer to obtain a plurality of parallel buffer strips, wherein two ends of each buffer strip are respectively embedded into the first embedded groove and the second embedded groove.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least:
in the miniature light emitting diode provided by the embodiment of the disclosure, a light emitting structure is arranged on a substrate, a first welding spot block, a second welding spot block and a buffer structure are arranged on the surface, far away from the substrate, of the light emitting structure, the first welding spot block and the second welding spot block are distributed at intervals, and the buffer structure is arranged between the first welding spot block and the second welding spot block. Therefore, the toughness of the area between the two welding spot blocks on the chip can be increased by adding the buffer structure between the first welding spot block and the second welding spot block so as to buffer the stress received between the two welding spot blocks, and when the two welding spot blocks are subjected to larger pressure, the area between the two welding spot blocks is promoted to deform, so that the problem of stripping of an epitaxial layer is solved, and the luminous effect of the chip is ensured.
And in the first solder joint piece of partial embedding of buffer structure, buffer structure still partly imbeds in the second solder joint piece, can make buffer structure continuous distribution in the region between two solder joint pieces, avoid the condition that the stress appears breaking at the boundary position between buffer structure and the solder joint piece, improve buffer structure and to the dispersion cushioning effect of stress, further avoid the problem that deformation appears in the region between two solder joint pieces, guarantee the luminous effect of chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure;
FIG. 2 is a top view of a miniature LED chip provided in an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a cushioning structure provided by an embodiment of the present disclosure;
fig. 4 is a flowchart of a method for manufacturing a micro light emitting diode chip according to an embodiment of the disclosure;
fig. 5 is a state diagram of a micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 6 is a state diagram of a micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a manufacturing state of a micro light emitting diode chip according to an embodiment of the disclosure.
The various labels in the figures are described below:
10. a substrate; 11. a GaAs substrate;
20. a light emitting structure; 21. a first semiconductor layer; 22. a multiple quantum well layer; 23. a second semiconductor layer; 24. a passivation layer; 25. a first electrode; 26. a second electrode;
31. a first solder joint block; 310. a first embedded groove; 32. a second solder joint block; 320. a second insertion groove;
40. a buffer structure;
50. a groove; 51. a first via; 52. a second via; 53. a protective layer;
61. a Cr layer; 62. an Al layer; 63. a Ti layer; 64. a Ni layer; 65. and a Sn alloy layer.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 1, the micro light emitting diode chip includes: the light emitting device includes a substrate 10, a light emitting structure 20, a first pad 31, a second pad 32, and a buffer structure 40.
As shown in fig. 1, the light emitting structure 20 is located on the surface of the substrate 10, the first solder bump 31, the second solder bump 32 and the buffer structure 40 are located on the surface of the light emitting structure 20 away from the substrate 10, and the first solder bump 31 and the second solder bump 32 are respectively connected with two electrodes of the light emitting structure 20.
Fig. 2 is a top view of a micro light emitting diode chip provided in an embodiment of the present disclosure. As shown in fig. 2, the first welding spot block 31 and the second welding spot block 32 are distributed at intervals, the buffer structure 40 is located between the first welding spot block 31 and the second welding spot block 32, a part of the buffer structure 40 is embedded in the first welding spot block 31, a part of the buffer structure 40 is also embedded in the second welding spot block 32, and the first welding spot block 31 and the second welding spot block 32 are insulated from the buffer structure 40.
In the micro light emitting diode provided in the embodiment of the present disclosure, the light emitting structure 20 is disposed on the substrate 10, the surface of the light emitting structure 20 far away from the substrate 10 is provided with the first solder joint block 31, the second solder joint block 32 and the buffer structure 40, the first solder joint block 31 and the second solder joint block 32 are arranged at intervals, and the buffer structure 40 is disposed between the first solder joint block 31 and the second solder joint block 32. Therefore, by adding the buffer structure 40 between the first welding spot block 31 and the second welding spot block 32, the toughness of the area between the two welding spot blocks on the chip can be increased, so that the stress born between the two welding spot blocks is buffered, and when the two welding spot blocks are subjected to larger pressure, the area between the two welding spot blocks is promoted to deform, so that the problem of stripping of an epitaxial layer is caused, and the luminous effect of the chip is ensured.
And, in the part embedding first solder joint piece 31 of buffer structure 40, buffer structure 40 still has part embedding second solder joint piece 32 in, can make buffer structure 40 continuously distributed in the region between two solder joint pieces, avoid the condition that the stress appears breaking in the boundary position between buffer structure 40 and solder joint piece, improve buffer structure 40 to the dispersion cushioning effect of stress, further avoid the problem that deformation appears in the region between two solder joint pieces, guarantee the luminous effect of chip.
Alternatively, as shown in fig. 1, the light emitting structure 20 includes: a first semiconductor layer 21, a multiple quantum well layer 22, a second semiconductor layer 23, a passivation layer 24, a first electrode 25, and a second electrode 26.
As shown in fig. 1, the first semiconductor layer 21, the multiple quantum well layer 22, and the second semiconductor layer 23 are sequentially stacked on the substrate 10, the second electrode 26 is located on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has a recess 50 exposing the first semiconductor layer 21, and the first electrode 25 is located on the surface of the first semiconductor layer 21 and on the bottom surface of the recess 50.
Wherein the passivation layer 24 covers at least the surfaces of the first semiconductor layer 21, the first electrode 25, the recess 50, the second semiconductor layer 23, and the second electrode 26.
By sequentially stacking the first semiconductor layer 21, the multiple quantum well layer 22, and the second semiconductor layer 23 on the substrate 10, wherein the second electrode 26 is disposed on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has the recess 50 exposing the first semiconductor layer 21, that is, part of the second semiconductor layer 23 and the multiple quantum well layer 22 are removed through the recess 50, so that the first electrode 25 is disposed directly on the surface of the first semiconductor layer 21 through the recess 50, thereby thinning the entire thickness of the epitaxial structure.
As shown in fig. 1, the first pad 31, the second pad 32 and the buffer structure 40 are all located on the surface of the passivation layer 24 away from the substrate 10, the surface of the passivation layer 24 has a first via 51 exposing the first electrode 25, the first pad 31 extends to the first via 51 and is connected to the first electrode 25, the surface of the passivation layer 24 has a second via 52 exposing the second electrode 26, and the second pad 32 extends to the second via 52 and is connected to the second electrode 26.
By covering the first pad 31 on the first via hole 51 and connecting with the first electrode 25, the electrical connection of the first electrode 25 is facilitated; the second pad 32 overlies the second via 52 and is connected to the second electrode 26 to facilitate electrical connection of the second electrode 26.
As shown in fig. 1, the first welding spot block 31 and the second welding spot block 32 are rectangular blocks, so that the area is increased, and the electric conduction is facilitated. And the first pad 31 and the second pad 32 are spaced apart on the surface of the passivation layer 24.
In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
As an example, the first semiconductor layer 21 is a p-type layer, and the first electrode 25 is a p-type electrode. The second semiconductor layer 23 is an n-type layer, and the second electrode 26 is an n-type electrode.
Alternatively, the substrate 10 is a sapphire substrate 10. The transmittance of the sapphire substrate 10 is relatively high, i.e., the substrate 10 is a transparent substrate 10. And the sapphire material is hard and has stable chemical characteristics, so that the red light emitting diode has good light emitting effect and stability.
Optionally, as shown in fig. 1, a bonding layer is further disposed between the light emitting structure 20 and the substrate 10.
Wherein the bonding layer may comprise SiO sequentially laminated on the substrate 10 2 Layer, si 3 N 4 Layer and Al 2 O 3 A layer. By SiO in such a bonding layer 2 The layer and main component are Al 2 O 3 The bonding layer 10 can form the combination of ionic bond and covalent bond, has better bonding force and stronger adhesive force, and can ensure the bonding yield between the inside of the bonding layer and the substrate 10.
Illustratively, al in the bond layer 2 O 3 The thickness of the layer is 50mm to 500nm, si 3 N 4 The thickness of the layer is 50mm to 500nm, siO 2 The thickness of the layer is 500nm to 5000nm.
Alternatively, the first semiconductor layer 21 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
Alternatively, the multiple quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer that are alternately grown, the content of Al in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer being different. Among them, the multiple quantum well layer 22 may include an AlGaInP quantum well layer and an AlGaInP quantum barrier layer of 3 to 8 periods alternately stacked.
As an example, in the presently disclosed embodiment, the multiple quantum well layer 22 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 22 may be 150nm to 200nm.
Alternatively, the second semiconductor layer 23 is an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
Alternatively, the passivation layer 24 may be a DBR (Distributed Bragg Reflection, distributed bragg mirror) layer comprising a plurality of periodically alternating layers of SiO 2 Layer and TiO 2 A layer. And the number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.
Wherein SiO in the DBR layer 2 The thickness of the layer may be 800 to 1000 angstroms, tiO 2 The thickness of the layer may be 400 angstroms to 600 angstroms.
The DBR layer serves to reflect light emitted from the multiple quantum well layer 22 toward the passivation layer 24 to the substrate 10 in addition to the passivation effect, thereby improving the light extraction effect.
Optionally, as shown in fig. 2, a side surface of the first solder joint block 31 near the buffer structure 40 is provided with a first embedded groove 310, a side surface of the second solder joint block 32 near the buffer structure 40 is provided with a second embedded groove 320, and the buffer structure 40 is located in the first embedded groove 310 and the second embedded groove 320.
By embedding the two portions of the buffer structure 40 into the first embedded groove 310 of the first pad block 31 and the second embedded groove 320 of the second pad block 32, respectively. The buffer structure 40 can be continuously distributed in the area between the two welding spot blocks, the condition that the stress is interrupted at the boundary position between the buffer structure 40 and the welding spot blocks is avoided, and the stress dispersing and buffering effect of the buffer structure 40 is improved.
Optionally, the buffer structure 40 has a gap between the groove wall of the first embedded groove 310 and the groove wall of the second embedded groove 320. To avoid the buffer structure 40 being directly connected to the first and second pads 31 and 32, to insulate the first and second pads 31 and 32, and to prevent the first and second pads 31 and 32 from being electrically shorted.
Optionally, gaps are formed between the buffer structure 40 and the walls of the first embedded groove 310 and the second embedded groove 320, and an insulating layer is disposed in the gaps to ensure the insulating effect.
Illustratively, as shown in fig. 2, the buffer structure 40 includes a plurality of buffer bars spaced in parallel, and both ends of each of the plurality of buffer bars are embedded in the first and second pad blocks 31 and 32, respectively.
The first embedded grooves 310 are in one-to-one correspondence with the buffer strips, the second embedded grooves 320 are in one-to-one correspondence with the buffer strips, and two ends of each buffer strip are respectively located in the corresponding first embedded grooves 310 and the corresponding second embedded grooves 320.
Illustratively, as shown in fig. 2, the buffer structure 40 includes four buffer bars that are spaced apart in parallel on the surface of the passivation layer 24. And the first welding spot block 31 is provided with four first embedded grooves 310 corresponding to the buffer strips one by one, the second welding spot block 32 is provided with four second embedded grooves 320 corresponding to the buffer strips one by one, and two ends of the buffer strips are respectively inserted into the corresponding first embedded grooves 310 and second embedded grooves 320.
Wherein the first and second insert grooves 310 and 320 may have a shape corresponding to the end shape of the bumper strip, and the two insert grooves may have a size larger than that of the bumper strip. After the buffer strip is inserted into the embedded groove, a certain gap can be kept between the buffer strip and the two welding spot blocks, so that the purpose of insulation is realized.
Fig. 3 is a schematic diagram of a buffer structure according to an embodiment of the present disclosure. As shown in fig. 3, the buffer structure 40 includes a Cr layer 61, an Al layer 62, a Ti layer 63, a Ni layer 64, and a Sn alloy layer 65 sequentially stacked on the surface of the light emitting structure.
Exemplary of the buffer structure 40 is a Cr layer having a thickness of 50 to 150 angstroms, an Al layer having a thickness of 2500 to 3500 angstroms, a Ti layer having a thickness of 300 to 700 angstroms, a Ni layer having a thickness of 6000 to 7000 angstroms, and a Sn alloy layer having a thickness of 85000 to 86000 angstroms
As an example, in the buffer structure 40, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 6500 angstroms, and the thickness of the Sn alloy layer is 85500 angstroms.
Wherein, the first and second pad pieces 31 and 32 each include a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially laminated on the surface of the light emitting structure 20.
Illustratively, in the first pad 31, the thickness of the Cr layer is 50 to 150 angstroms, the thickness of the Al layer is 2500 to 3500 angstroms, the thickness of the Ti layer is 300 to 700 angstroms, the thickness of the Ni layer is 1500 to 2500 angstroms, and the thickness of the Sn alloy layer is 89500 to 90500 angstroms.
As an example, in the first pad 31, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Sn alloy layer is 90000 angstroms.
Illustratively, in the second pad 32, the thickness of the Cr layer is 50 to 150 angstroms, the thickness of the Al layer is 2500 to 3500 angstroms, the thickness of the Ti layer is 300 to 700 angstroms, the thickness of the Ni layer is 1500 to 2500 angstroms, and the thickness of the Sn alloy layer is 89500 to 90500 angstroms.
As an example, in the second pad 32, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Sn alloy layer is 90000 angstroms.
Since the toughness is greatly affected by Ni metal in the metal layer formed by combining the Cr layer, al layer, ti layer, ni layer, and Sn alloy layer. Compared with the welding spot blocks, the effective width of the buffer structure 40 between the two welding spot blocks is smaller, so that the thickness of the Ni layer in the buffer structure 40 is increased, the toughness of the buffer structure 40 is consistent with that of the two welding spot blocks, and the deformation resistance of the area between the two welding spot blocks is enhanced.
In the embodiment of the present disclosure, the thickness of the buffer structure 40 is equal to the thickness of the first pad 31 in the direction perpendicular to the substrate 10, and the thickness of the buffer structure 40 is equal to the thickness of the second pad 32.
By reducing the thickness of the Sn alloy layer, the thickness of the buffer structure 40 is made consistent with the thickness of the two solder bumps to avoid affecting the soldering of the chip to other components during subsequent use.
Fig. 4 is a flowchart of a method for manufacturing a micro light emitting diode chip according to an embodiment of the disclosure. The method is used for preparing the miniature light-emitting diode chip shown in fig. 1. As shown in fig. 4, the preparation method includes:
s11: a substrate 10 is provided.
S12: a light emitting structure 20 is formed on the substrate 10.
S13: the first pad 31, the second pad 32, and the buffer structure 40 are formed on the surface of the light emitting structure 20 away from the substrate 10.
Wherein, the first welding spot block 31 and the second welding spot block 32 are respectively connected with two electrodes of the light emitting structure 20; the first welding spot block 31 and the second welding spot block 32 are distributed at intervals, the buffer structure 40 is located between the first welding spot block 31 and the second welding spot block 32, a first part of the buffer structure 40 is embedded in the first welding spot block 31, a second part of the buffer structure 40 is embedded in the second welding spot block 32, and the first welding spot block 31 and the second welding spot block 32 are insulated from the buffer structure 40.
In the micro light emitting diode prepared by the preparation method, the light emitting structure 20 is arranged on the substrate 10, the first welding spot block 31, the second welding spot block 32 and the buffer structure 40 are arranged on the surface, far away from the substrate 10, of the light emitting structure 20, the first welding spot block 31 and the second welding spot block 32 are arranged at intervals, and the buffer structure 40 is arranged between the first welding spot block 31 and the second welding spot block 32. Therefore, by adding the buffer structure 40 between the first welding spot block 31 and the second welding spot block 32, the toughness of the area between the two welding spot blocks on the chip can be increased, so that the stress born between the two welding spot blocks is buffered, and when the two welding spot blocks are subjected to larger pressure, the area between the two welding spot blocks is promoted to deform, so that the problem of stripping of an epitaxial layer is caused, and the luminous effect of the chip is ensured.
And in addition, the first part in the buffer structure 40 is embedded in the first welding spot block 31, the second part of the buffer structure 40 is embedded in the second welding spot block 32, so that the buffer structure 40 can be continuously distributed in the area between the two welding spot blocks, the condition that the stress is interrupted at the boundary position between the buffer structure 40 and the welding spot blocks is avoided, the stress dispersion buffer effect of the buffer structure 40 is improved, the problem that the deformation occurs in the area between the two welding spot blocks is further avoided, and the luminous effect of the chip is ensured.
Alternatively, the substrate 10 is a sapphire substrate 10. The transmittance of the sapphire substrate 10 is relatively high, i.e., the substrate 10 is a transparent substrate 10. And the sapphire material is hard and has stable chemical characteristics, so that the red light emitting diode has good light emitting effect and stability.
In step S11, the sapphire substrate 10 may be subjected to pretreatment, the sapphire substrate 10 is placed in an MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition) reaction chamber, and the sapphire substrate 10 is subjected to baking treatment for 12 minutes to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate 10 is subjected to the baking treatment for 15 minutes.
Specifically, the baking temperature may be 1000 ℃ to 1200 ℃, and the pressure in the MOCVD reaction chamber during baking may be 100mbar to 200mbar.
Step S11 may further include growing a dry etching mask on the sapphire substrate 10, and patterning the mask by a photolithography process.
The light emitting structure 20 grown in step S12 includes: a first semiconductor layer 21, a multiple quantum well layer 22, a second semiconductor layer 23, a passivation layer 24, a first electrode 25, and a second electrode 26.
As shown in fig. 1, the first semiconductor layer 21, the multiple quantum well layer 22 and the second semiconductor layer 23 are sequentially stacked on the substrate 10, the second electrode 26 is located on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has a groove 50 exposing the first semiconductor layer 21, the first electrode 25 is located on the surface of the first semiconductor layer 21 and is located on the bottom surface of the groove 50, and the passivation layer 24 covers at least the surfaces of the first semiconductor layer 21, the first electrode 25, the groove 50, the second semiconductor layer 23, and the second electrode 26.
The process of growing the light emitting structure 20 may include: as shown in fig. 5, first, the second semiconductor layer 23 is grown on the GaAs substrate 11.
The second semiconductor layer 23 is illustratively an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
As shown in fig. 5, after the second semiconductor layer 23 is grown, a multiple quantum well layer 22 is grown on the second semiconductor layer 23.
The multiple quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer which are alternately grown, and the AlGaInP quantum well layer and the AlGaInP quantum barrier layer have different Al contents. Among them, the multiple quantum well layer 22 may include an AlGaInP quantum well layer and an AlGaInP quantum barrier layer of 3 to 8 periods alternately stacked.
As an example, in the presently disclosed embodiment, the multiple quantum well layer 22 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 22 may be 150nm to 200nm.
As shown in fig. 5, after the multiple quantum well layer 22 is grown, the first semiconductor layer 21 is grown on the multiple quantum well layer 22.
The first semiconductor layer 21 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
In step S12, a GaAs layer and a corrosion-cut layer may be grown before the second semiconductor layer 23 is grown, and an AlInP carrier confinement layer may be grown before the multi-quantum well layer 22 is grown.
A GaP window layer may also be grown after the first semiconductor layer 21 is grown, wherein the GaP window layer has a thickness of 2 μm to 5 μm.
Illustratively, the GaP window layer has a thickness of 3 μm.
After the epitaxial structure including the first semiconductor layer 21, the multiple quantum well layer 22, and the second semiconductor layer 23 is grown, the surface of the epitaxial structure where the first semiconductor layer 21 is located is bonded to the substrate 10 at a bonding temperature of 300 °. After the bonding is completed, the GaAs substrate 11 is removed.
In step S12, after the second semiconductor layer 23 is grown, the recess 50 of the first semiconductor layer 21 is etched on the surface of the second semiconductor layer 23.
As shown in fig. 6, specifically, the method may include: a partial region of the second semiconductor is etched away by dry etching and etched until the first semiconductor layer 21 is exposed. The etching depth is 1 μm to 2 μm, for example, 1.5 μm.
After etching the groove 50, the first electrode 25 may be formed on the first semiconductor layer 21, and the second electrode 26 may be formed on the second semiconductor layer 23.
In step S12, as shown in fig. 6, forming the first electrode 25 and the second electrode 26 may include: the first electrode 25 and the second electrode 26 are respectively processed by negative photoresist stripping.
As shown in fig. 6, the second electrode 26 is located on the surface of the second semiconductor layer 23, and the first electrode 25 is located on the bottom surface of the recess 50.
The first electrode 25 uses gold beryllium as a main component, the second electrode 26 uses gold germanium as a base material for evaporation, the evaporation power is required to be ensured when the gold germanium alloy is evaporated, the evaporation time is prevented from exceeding 5 seconds, the deviation of the alloy components is prevented, and annealing is performed.
In step S12, the passivation layer 24 may be a DBR layer including a plurality of periodically alternately laminated SiO 2 Layer and TiO 2 A layer. And the number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.
Wherein SiO in the DBR layer 2 The thickness of the layer may be 800 to 1000 angstroms, tiO 2 The thickness of the layer may be 400 to 600 angstroms
After forming the passivation layer 24 in step S12, as shown in fig. 7, the preparation method may further include: first and second vias 51 and 52 are formed in a surface of the passivation layer 24 remote from the substrate 10. Forming a first welding spot block 31 on the surface of the passivation layer 24 in a photoetching mode, so that the first welding spot block 31 is connected with the first electrode 25 through the first via hole 51; then, a second pad 32 is formed on the surface of the passivation layer 24 by photolithography, so that the second pad 32 is connected to the second electrode 26 through the second via 52.
Wherein each of the first pad 31 and the second pad 32 includes a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially laminated on the surface of the passivation layer 24.
Illustratively, in the first pad 31, the thickness of the Cr layer is 50 to 150 angstroms, the thickness of the Al layer is 2500 to 3500 angstroms, the thickness of the Ti layer is 300 to 700 angstroms, the thickness of the Ni layer is 1500 to 2500 angstroms, and the thickness of the Sn alloy layer is 89500 to 90500 angstroms.
As an example, in the first pad 31, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Sn alloy layer is 90000 angstroms.
Illustratively, in the second pad 32, the thickness of the Cr layer is 50 to 150 angstroms, the thickness of the Al layer is 2500 to 3500 angstroms, the thickness of the Ti layer is 300 to 700 angstroms, the thickness of the Ni layer is 1500 to 2500 angstroms, and the thickness of the Sn alloy layer is 89500 to 90500 angstroms.
As an example, in the second pad 32, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Sn alloy layer is 90000 angstroms.
In step S13, after forming the first pad 31 and the second pad 32, forming the buffer structure on the surface of the substrate away from the light emitting structure may include the following steps:
etching a first welding spot block, forming a plurality of first embedded grooves on the first welding spot block, etching a second welding spot block, and forming a plurality of second embedded grooves on the second welding spot block.
Illustratively, the first embedded groove may be etched from the top of the first pad to the direction in which the light emitting structure is located by photolithography, and may be formed to extend to a side opposite to the second pad.
Illustratively, the second embedded groove may be etched from the top of the second pad to the direction in which the light emitting structure is located by photolithography, and may be formed to extend to a side opposite to the first pad.
As shown in fig. 2, the first embedded groove extends to a side surface of the first welding spot block opposite to the second welding spot block, the second embedded groove extends to a side surface of the second welding spot block opposite to the first welding spot block, and the first embedded groove corresponds to the second embedded groove one by one.
And secondly, evaporating and forming a metal layer on the surface of the light-emitting structure.
The purpose of growing a metal layer on the surface of the light-emitting structure is achieved by adopting metal evaporation table equipment.
Wherein, the metal layer includes Cr layer, al layer, ti layer, ni layer and Sn alloy layer laminated on the surface of the passivation layer in order.
Illustratively, in the metal layer, the Cr layer has a thickness of 50 to 150 angstroms, the Al layer has a thickness of 2500 to 3500 angstroms, the Ti layer has a thickness of 300 to 700 angstroms, the Ni layer has a thickness of 6000 to 7000 angstroms, and the Sn alloy layer has a thickness of 85000 to 86000 angstroms.
As an example, in the metal layer, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 6500 angstroms, and the thickness of the Sn alloy layer is 85500 angstroms.
And thirdly, etching the metal layer to obtain a plurality of parallel buffer strips, wherein two ends of each buffer strip are respectively embedded into the first embedded groove and the second embedded groove.
As shown in fig. 2, when the metal layer is etched, a photolithography method may be adopted to remove a film layer located between two solder joint blocks in the metal layer, and photolithography is performed between the two solder joint blocks to obtain a plurality of parallel buffer strips.
After forming the first pad 31 and the second pad 32, a protective layer 53 may be formed on the surface of the passivation layer 24, and the protective layer 53 may extend from the surface of the passivation layer 24 to the substrate 10, as shown in fig. 1.
Illustratively, in the disclosed embodiment, the protective layer 53 may be a silicon oxide layer having a thickness of 2000 angstroms.
After the passivation layer 53 is grown on the surface of the passivation layer 24, a through hole exposing the solder bump may be etched on the surface of the passivation layer 53 by using a photolithography technique, so as to facilitate electrical connection.
In step S13, forming the buffer structure 40 may further include: the sapphire substrate 10 was thinned, and the final thickness after thinning was 80 μm.
Finally, the sapphire can be subjected to invisible cutting and splitting, and the loss of brightness can be well reduced by the invisible cutting and splitting. And then testing to obtain the miniature light-emitting diode chip.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.
Claims (7)
1. A micro light emitting diode chip, the micro light emitting diode chip comprising: a substrate (10), a light emitting structure (20), a first solder joint block (31), a second solder joint block (32) and a buffer structure (40);
the light-emitting structure (20) is positioned on the surface of the substrate (10), the first welding spot block (31), the second welding spot block (32) and the buffer structure (40) are positioned on the surface, far away from the substrate (10), of the light-emitting structure (20), and the first welding spot block (31) and the second welding spot block (32) are respectively connected with two electrodes of the light-emitting structure (20);
the first welding spot blocks (31) and the second welding spot blocks (32) are distributed at intervals, the buffer structure (40) is located between the first welding spot blocks (31) and the second welding spot blocks (32), the buffer structure (40) is partially embedded into the first welding spot blocks (31) and is partially embedded into the second welding spot blocks (32), the first welding spot blocks (31) and the second welding spot blocks (32) are insulated from the buffer structure (40), a first embedded groove (310) is formed in one side surface, close to the buffer structure (40), of the first welding spot blocks (31), a second embedded groove (320) is formed in one side surface, close to the buffer structure (40), of the second welding spot blocks (32), the buffer structure (40) is located in the first embedded groove (310) and the second embedded groove (320), the buffer structure (40) comprises a plurality of buffer strips, the two ends of each buffer strip are respectively embedded into the first welding spot blocks (31) and the second welding spot (32).
2. The micro light emitting diode chip according to claim 1, wherein the buffer structure (40) has a gap with both the groove wall of the first embedded groove (310) and the groove wall of the second embedded groove (320); or,
gaps are formed between the buffer structure (40) and the groove walls of the first embedded groove (310) and between the buffer structure and the groove walls of the second embedded groove (320), and an insulating layer is arranged in the gaps.
3. The micro light emitting diode chip according to claim 1, wherein the buffer structure (40) includes a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially stacked on the surface of the light emitting structure (20).
4. A micro light emitting diode chip according to claim 3, wherein in the buffer structure (40), the thickness of the Cr layer is 50 to 150 a, the thickness of the Al layer is 2500 to 3500 a, the thickness of the Ti layer is 300 to 700 a, the thickness of the Ni layer is 6000 to 7000 a, and the thickness of the Sn alloy layer is 85000 to 86000 a.
5. The micro light emitting diode chip according to claim 1, wherein the first pad (31) and the second pad (32) each include a Cr layer, an Al layer, a Ti layer, a Ni layer, and a Sn alloy layer sequentially laminated on the surface of the light emitting structure (20).
6. The micro light emitting diode chip according to claim 5, wherein in the first pad (31), a Cr layer has a thickness of 50 to 150 a, an Al layer has a thickness of 2500 to 3500 a, a Ti layer has a thickness of 300 to 700 a, a Ni layer has a thickness of 1500 to 2500 a, and a Sn alloy layer has a thickness of 89500 to 90500 a;
in the second solder joint block (32), the thickness of the Cr layer is 50-150 angstroms, the thickness of the Al layer is 2500-3500 angstroms, the thickness of the Ti layer is 300-700 angstroms, the thickness of the Ni layer is 1500-2500 angstroms, and the thickness of the Sn alloy layer is 89500-90500 angstroms.
7. The preparation method of the miniature light-emitting diode chip is characterized by comprising the following steps of:
providing a substrate;
forming a light emitting structure on the substrate;
forming a first welding spot block, a second welding spot block and a buffer structure on the surface of the light-emitting structure, which is far away from the substrate, wherein the first welding spot block and the second welding spot block are respectively connected with two electrodes of the light-emitting structure; the first welding spot block is distributed with the second welding spot block interval, the buffer structure is located first welding spot block with between the second welding spot block, the first part of buffer structure is embedded in the first welding spot block, the second part of buffer structure is embedded in the second welding spot block, first welding spot block with the second welding spot block all with buffer structure insulates, the surface that the base plate kept away from the luminous structure forms buffer structure and includes: etching the first welding spot block, forming a plurality of first embedded grooves on the first welding spot block, etching the second welding spot block, forming a plurality of second embedded grooves on the second welding spot block, wherein the first embedded grooves extend to the side surfaces of the first welding spot block opposite to the second welding spot block, the second embedded grooves extend to the side surfaces of the second welding spot block opposite to the first welding spot block, and the first embedded grooves and the second embedded grooves are in one-to-one correspondence; evaporating and forming a metal layer on the surface of the light-emitting structure; etching the metal layer to obtain a plurality of parallel buffer strips, wherein two ends of each buffer strip are respectively embedded into the first embedded groove and the second embedded groove.
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