CN115084145A

CN115084145A - Three-dimensional semiconductor structure and manufacturing method thereof

Info

Publication number: CN115084145A
Application number: CN202210842918.5A
Authority: CN
Inventors: 肖剑锋
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-07-18
Filing date: 2022-07-18
Publication date: 2022-09-20
Also published as: WO2024016889A1

Abstract

The present disclosure provides a three-dimensional semiconductor structure and a method of fabricating the same, the three-dimensional semiconductor structure comprising: a substrate; a stacked structure on the substrate, including a plurality of memory cell arrays stacked in a thickness direction of the substrate, each memory cell array including a plurality of transistors and a plurality of connection pads arrayed in a planar direction of the substrate; the transistor comprises a semiconductor layer extending along the plane direction of a substrate, and a source region, a channel region and a drain region are sequentially arranged on the semiconductor layer along the length direction of the semiconductor layer; the connecting pad is arranged on the lateral side of the semiconductor layer in the width direction and is connected with the semiconductor layer, the connecting pad is electrically connected with the channel region, and the connecting pad is electrically connected with the substrate. The three-dimensional semiconductor structure provided by the disclosure can solve the floating body effect of a transistor and improve the performance of the three-dimensional semiconductor structure.

Description

Three-dimensional semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor integrated circuit technologies, and in particular, to a three-dimensional semiconductor structure and a method for fabricating the same.

Background

As semiconductor technology advances, semiconductor devices are gradually becoming more highly integrated, and at the same time, it is desirable that semiconductor devices have lower manufacturing costs to meet consumer demands for superior performance and low price of semiconductor devices.

For the integration of a typical two-dimensional (planar) semiconductor device, which is mainly determined by the area of memory cells arrayed on a plane, the smaller the area of memory cells, the higher the integration of the semiconductor device. The area of the memory cell is influenced by the level of fine patterning technology, however, expensive process equipment for improving the fineness of the pattern greatly limits the improvement of the integration of the two-dimensional semiconductor device. Accordingly, three-dimensional semiconductor devices having memory cells with a three-dimensional architecture have been proposed.

However, in the conventional three-dimensional semiconductor device, the performance of the semiconductor device is seriously affected due to the floating body effect caused by the floating of the transistor.

Disclosure of Invention

In order to solve at least one of the problems mentioned in the background art, the present disclosure provides a three-dimensional semiconductor structure and a method for fabricating the same, which can solve the floating body effect of a transistor and improve the performance of the three-dimensional semiconductor structure.

In order to achieve the above object, the present disclosure provides the following technical solutions:

in one aspect, the present disclosure provides a three-dimensional semiconductor structure comprising:

a substrate;

a stacked structure on the substrate, including a plurality of memory cell arrays stacked in a thickness direction of the substrate, each memory cell array including a plurality of transistors and a plurality of connection pads arrayed in a planar direction of the substrate; wherein the content of the first and second substances,

the transistor comprises a semiconductor layer extending along the plane direction of the substrate, and a source region, a channel region and a drain region are sequentially arranged on the semiconductor layer along the length direction of the semiconductor layer; the connecting pad is arranged on the lateral side of the semiconductor layer in the width direction and connected with the semiconductor layer, the connecting pad is electrically connected with the channel region, and the connecting pad is electrically connected with the substrate.

In one possible embodiment, the connection pads alternate with the semiconductor layers in the width direction of the semiconductor layers.

In one possible embodiment, the sides of the connection pad opposite to the semiconductor layers on both sides are a first side and a second side, respectively, the first side is connected with the opposite semiconductor layer, and the second side has a gap with the opposite semiconductor layer.

In one possible embodiment, the connection pads are connected to the semiconductor layer on both sides thereof.

In one possible embodiment, a connection pad is provided between each two semiconductor layers, which connection pad is connected to the semiconductor layers on both sides thereof.

In one possible embodiment, the three-dimensional semiconductor structure further includes:

the connecting upright columns are arranged in an array mode along the plane direction of the substrate, connected to the substrate and extending along the thickness direction of the substrate, and connected with the connecting pads in the extending direction.

In one possible embodiment, the connection pad includes a main body portion corresponding to the channel region and a connection portion connected to a side of the main body portion along a length direction of the semiconductor layer, and the connection pillar penetrates the connection portion.

In one possible embodiment, the connection portion corresponds to a source region, or the connection portion corresponds to a drain region.

In one possible embodiment, the connection portion includes a first connection portion corresponding to the source region and a second connection portion corresponding to the drain region, at least one of the first connection portion and the second connection portion being connected to the connection pillar.

In one possible embodiment, the transistor further includes a gate structure covering at least one side surface in a thickness direction of the channel region.

In one possible embodiment, the gate structure covers both side surfaces in the thickness direction of the channel region.

In one possible embodiment, the gate structure extends to a portion of the surface covering the bonding pad.

In one possible embodiment, the three-dimensional semiconductor structure further comprises:

and a plurality of word lines covering the corresponding gate structures and extending in a width direction of the semiconductor layer, and the word lines being stacked in a thickness direction of the substrate.

In a possible embodiment, the thickness of the connection pads is the same as the thickness of the semiconductor layer in the thickness direction of the substrate.

In another aspect, the present disclosure provides a method for fabricating a three-dimensional semiconductor structure, including:

providing a substrate;

forming a stacked structure, wherein the stacked structure is positioned on a substrate; the stacked structure includes a plurality of memory cell arrays stacked in a thickness direction of the substrate, each memory cell array including a plurality of transistors and a plurality of connection pads arrayed in a planar direction of the substrate; wherein the content of the first and second substances,

the transistor comprises a semiconductor layer extending along the plane direction of the substrate, and a source region, a channel region and a drain region are sequentially arranged on the semiconductor layer along the length direction of the semiconductor layer; the connecting pad is arranged on the lateral side of the semiconductor layer in the width direction and is connected with the semiconductor layer, the connecting pad is electrically connected with the substrate, and the connecting pad is electrically connected with the channel region.

The three-dimensional semiconductor structure is characterized in that a plurality of connecting pads are arranged in each layer of storage unit array in a stacked structure, the connecting pads are arranged in the storage unit array in an array mode, each transistor is provided with a corresponding connecting pad connected with the corresponding connecting pad, the connecting pads are electrically connected with a channel region of a semiconductor layer, the connecting pads are electrically connected with a substrate, the connecting pads are used for enabling residual charges in the channel region to flow to the substrate, the floating body effect of the transistors is solved through the grounded substrate discharge, and the performance of the three-dimensional semiconductor structure is improved. For the semiconductor layer extending along the plane direction of the substrate, the connection pad is arranged on the side of the width direction of the semiconductor layer at the same layer, so that the connection pad is convenient to form, the connection pad does not occupy an independent thickness space, and the integration level of the three-dimensional semiconductor structure is improved.

The construction of the present disclosure and other objects and advantages thereof will be more apparent from the following description of the preferred embodiments taken in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced, and it is obvious that the drawings in the following description are some embodiments of the present disclosure. For a person skilled in the art, without inventive effort, further figures can be obtained from these figures.

FIG. 1 is a perspective view of a three-dimensional semiconductor device;

fig. 2 is a schematic structural view of a transistor of the three-dimensional semiconductor device shown in fig. 1;

FIG. 3 is a schematic cross-sectional view of the transistor of FIG. 2 at A-A;

fig. 4 is a perspective view of a three-dimensional semiconductor structure provided by an embodiment of the present disclosure;

FIG. 5 is a perspective view of a memory cell of the three-dimensional semiconductor structure of FIG. 4;

FIG. 6 is a cross-sectional view at B-B of the three-dimensional semiconductor structure of FIG. 4;

FIG. 7 is a cross-sectional view of another three-dimensional semiconductor structure provided in accordance with an embodiment of the present disclosure, taken at B-B of FIG. 4;

FIG. 8 is a cross-sectional view of a third three-dimensional semiconductor structure provided in accordance with an embodiment of the present disclosure, taken at B-B of FIG. 4;

FIG. 9 is a perspective view of a memory cell of another three-dimensional semiconductor structure;

fig. 10 is a flowchart illustrating steps of a method for fabricating a three-dimensional semiconductor structure according to an embodiment of the present disclosure.

Description of reference numerals:

1-a three-dimensional semiconductor structure;

100-a substrate;

200-a stacked structure; 300-word line; 400-bit line; 500-connecting the upright post;

201-memory cell array;

210-a transistor; 220-a connection pad; 220 a-a first side; 220 b-second side; 230-capacitance;

211-a semiconductor layer; 212-a gate structure; 221-a body portion; 222-a connecting portion;

2111-source region; 2112-channel region; 2113-a drain region; 2221-first connection; 2222-a second connecting portion;

10-a three-dimensional semiconductor device;

11-a transistor; 12-word line; 13-bit line; 14-capacitance; 15-contact stud;

a 111-semiconductor column; 111 a-source region; 111 b-channel region; 111 c-drain region; 112-a gate structure; 112 a-a gate dielectric layer; 112 b-gate electrode layer.

Detailed Description

As described in the background art, since the device pattern of the two-dimensional semiconductor device is laid out and extended in the planar direction, the integration degree of the two-dimensional semiconductor device is mainly determined by the area of the memory cells arranged in an array on a plane, and in order to improve the integration degree of the two-dimensional semiconductor device, the area of the memory cells needs to be reduced. However, the area of the memory cell is influenced by the level of the fine pattern forming technology, most of the existing process equipment cannot manufacture a fine device pattern, and the process equipment capable of improving the fineness of the device pattern is rare and expensive, which greatly limits the improvement of the integration degree of the two-dimensional semiconductor device.

Because the integration level of the two-dimensional semiconductor device is limited, in order to improve the integration level of the semiconductor device, improve the performance of the semiconductor device, and enable the semiconductor device to have lower manufacturing cost, a three-dimensional semiconductor device has been proposed. As the name implies, the three-dimensional semiconductor device has the memory cells stacked in the thickness direction of the device, so that more memory cells are arranged in a unit area of the device, and the integration level of the semiconductor device is improved.

Fig. 1 is a perspective view of a three-dimensional semiconductor device. Referring to fig. 1, taking a Dynamic Random Access Memory (DRAM) as an example, a plane formed by an X direction and a Y direction shown in the drawing is a plane direction of the three-dimensional semiconductor device 10, and a Z direction shown in the drawing is a thickness direction of the three-dimensional semiconductor device 10. The transistor 11 of the three-dimensional semiconductor device 10 is stacked on a substrate (not shown in the figure) along a thickness direction (Z direction) thereof, and for one of the transistors 11, the transistor 11 includes a semiconductor pillar 111 and a gate structure 112, the semiconductor pillar 111 extends along a planar direction (for example, an X direction shown in the figure) of the three-dimensional semiconductor device 10, the semiconductor pillar 111 is a source region 111a, a channel region (not shown in the figure) and a drain region 111c in sequence along the extending direction thereof, the gate structure 112 is annularly arranged on an outer periphery of the channel region, and the gate structure 112 may include a gate dielectric layer 112a wrapping an outer sidewall of the channel region and a gate electrode layer 112b laminated outside the gate dielectric layer 112 a.

The three-dimensional semiconductor device 10 further includes word lines 12, bit lines 13, and capacitors 14. The word lines 12 extend in a planar direction of the three-dimensional semiconductor device 10, and may specifically extend in an arrangement direction of the transistors 11 (e.g., a direction perpendicular to an extension direction of the transistors 11), and the word lines 12 wrap the outside of the gate structures 112 of all the transistors 11 in an extension direction thereof. Then, in the stacking direction (Z direction) of the word lines 12, the end portion of the word line 12 in the lower layer is sequentially protruded from the end portion of the word line 12 in the upper layer to form a step portion, the step portion of each word line 12 is used to connect the contact pillar 15 to the word line 12, the contact pillar 15 extends in the thickness direction (Z direction) of the three-dimensional semiconductor device 10, and each word line 12 is electrically connected to a peripheral driver circuit (not shown) through each contact pillar 15. The bit line 13 extends in the thickness direction of the three-dimensional semiconductor device 10, and is connected to one end of the semiconductor pillar 111 of each transistor 11 in the extending direction thereof. The capacitor 14 is connected to the other end of the semiconductor column 111.

However, since the transistors 11 stacked in the thickness direction of the three-dimensional semiconductor device 10 are suspended above the substrate, the transistors 11 may generate a floating body effect. Fig. 2 is a schematic structural view of a transistor of the three-dimensional semiconductor device shown in fig. 1; fig. 3 is a schematic cross-sectional view of the transistor of fig. 2 at a-a. Referring to fig. 2 and 3, the so-called floating body effect is that the transistor 11 is frequently switched during the operation of the three-dimensional semiconductor device 10, a depletion region is formed in the channel region 111b of the semiconductor pillar 111 during the switching of the transistor 11, charges are repeatedly injected into the channel region 111b and discharged from the channel region 111b, and in the past, a part of charges remain in the channel region 111b, and the charges are accumulated in the channel region 111b due to the transistor 11 being suspended above the substrate (an insulating dielectric layer exists between the transistor 11 and the substrate), thereby causing various adverse effects, such as leakage current caused by the parasitic double transistor effect, high current loss, threshold voltage drift, warping effect, and the like.

In view of this, embodiments of the present disclosure provide a three-dimensional semiconductor structure and a method for fabricating the same, in which a connection pad is disposed at a side of a semiconductor layer of a transistor, and a channel region of the semiconductor layer is electrically connected to a substrate through the connection pad, so that charges accumulated in the channel region are released into the substrate and discharged, thereby solving a floating body effect of the transistor and improving performance of the three-dimensional semiconductor structure.

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The present embodiments provide a three-dimensional semiconductor structure, which may be a memory device or a non-memory device. The Memory device may include, for example, a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash Memory, an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Phase Change Random Access Memory (PRAM), or a Magnetoresistive Random Access Memory (MRAM). The non-memory device may be a logic device (e.g., a microprocessor, digital signal processor, or microcontroller) or the like. The following description will be given taking a three-dimensional semiconductor structure as an example of a DRAM.

Fig. 4 is a perspective view of a three-dimensional semiconductor structure provided by an embodiment of the present disclosure. Referring to fig. 4, the three-dimensional semiconductor structure 1 includes a substrate 100 and a stacked structure 200, wherein the stacked structure 200 is disposed on the substrate 100, and the substrate 100 may provide a supporting base for the stacked structure 200. When fabricating the three-dimensional semiconductor structure 1, a stack of layers is typically disposed on the substrate 100, and a pattern is formed in the stack of layers to form a stacked structure 200, where the stacked structure 200 is a desired device pattern to realize the functions of the three-dimensional semiconductor structure 1.

Illustratively, the material forming the substrate 100 may include one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator (SOI), or the material forming the substrate 100 may be other materials known to those skilled in the art.

Note that the planar direction constituted by the X direction and the Y direction shown in fig. 4 is a planar direction of the three-dimensional semiconductor structure 1, and for example, the planar direction may indicate a planar direction of the substrate 100; the Z direction shown in fig. 4 is a thickness direction of the three-dimensional semiconductor structure 1, and for example, the Z direction may indicate a thickness direction of the substrate 100. In the following, this coordinate system is used as a reference for the three-dimensional semiconductor structure 1, and will not be described in detail.

The stacked structure 200 includes a plurality of layers stacked in the thickness direction (Z direction) of the substrate 100, each layer constituting one memory cell array 201, that is, the stacked structure 200 includes a plurality of memory cell arrays 201 stacked in the thickness direction of the substrate 100. The memory cell array 201 of each layer includes a plurality of memory cells arrayed in a planar direction of the substrate 100, and illustratively, the memory cells may be arrayed in an X direction and a Y direction, for example, the X direction is a row direction of the memory cell array, and the Y direction is a column direction of the memory cell array.

In addition, referring to fig. 4, the three-dimensional semiconductor structure 1 further includes a plurality of word lines 300 and a plurality of bit lines 400. The word lines 300 are parallel to each other and extend in a first direction, and the word lines 300 may be disposed at equal intervals; similar to the word lines 300, the bit lines 400 are parallel to each other and extend in the second direction, and the bit lines 400 may be disposed at equal intervals. The bit line 400 and the word line 300 are electrically connected to each memory cell for controlling the operating state of each memory cell. Wherein the first direction and the second direction are staggered, and illustratively, the first direction and the second direction may be perpendicular to each other.

Each memory cell includes a transistor 210 and a capacitor 230, and the capacitor 230 is electrically connected to the transistor 210. The word line 300 and the bit line 400 are both connected to the transistor 210 in each memory cell, the word line 300 is electrically connected to a driver circuit in the periphery of the memory cell array 201, the driver circuit inputs a voltage signal to the word line 300, the transistor 210 is controlled to be turned on or off by the voltage signal on the word line 300, and when the transistor 210 is turned on, data information stored in the capacitor 230 is read by the bit line 400 or the data information is written into the capacitor 230 by the bit line 400 and stored.

With continued reference to fig. 4, with the three-dimensional semiconductor structure 1, in the present embodiment, the transistors 210 in the respective memory cells may be arranged parallel to the planar direction of the substrate 100, so that a plurality of transistors 210 may be arrayed in the planar direction of the substrate 100 in the memory cell array 201 of each layer, and a multilayer memory cell array 201 is stacked in the thickness direction thereof on the substrate 100, that is, the transistors 210 arrayed are stacked in the thickness direction (Z direction) thereof on the substrate 100 in a plurality of layers.

Thus, on the basis that the area of the three-dimensional semiconductor structure 1 in the plane direction is maintained unchanged, the transistors 210 arranged in the original array are stacked in multiple layers in the thickness direction of the three-dimensional semiconductor structure 1, so that the number of the transistors 210 in a unit area is increased, the integration level of the three-dimensional semiconductor structure 1 is increased, the storage density of the three-dimensional semiconductor structure 1 is improved, and further, the performance of the three-dimensional semiconductor structure 1 is improved.

Since the three-dimensional semiconductor structure 1 increases the number of transistors 210 in a unit area, in practical applications, for the case where the requirements for storage capacity and storage read rate are low, the three-dimensional semiconductor structure 1 can reduce the planar size of the three-dimensional semiconductor structure 1 on the basis that the number of transistors 210 designed in the three-dimensional semiconductor structure is equivalent to the number of transistors 210 in the two-dimensional semiconductor structure, so that the three-dimensional semiconductor structure 1 is more miniaturized. For the case of high requirements on storage capacity and storage read rate, the three-dimensional semiconductor structure 1 can maintain the planar size equivalent to that of the two-dimensional semiconductor structure, but the number of transistors 210 therein is much larger than that of the transistors 210 of the two-dimensional semiconductor structure, thereby significantly improving the performance of the three-dimensional semiconductor structure 1.

It is to be understood that fig. 4 exemplarily shows two adjacent memory cells in each layer of the memory cell array 201, and shows two layers of the memory cell array 201 located above the substrate 100 in the three-dimensional semiconductor structure 1. In practical applications, in the three-dimensional semiconductor structure 1, the transistors 210 arranged in each layer of the memory cell array 201 have m rows and n columns (m is a positive integer ≧ 2, and n is a positive integer ≧ 2), for example, and the stacked memory cell arrays 201 may be two layers, three layers, four layers, or even more, which is not limited in this embodiment.

Fig. 5 is a perspective view of a memory cell of the three-dimensional semiconductor structure of fig. 4. Referring to fig. 5, a structure of a memory cell of the three-dimensional semiconductor structure 1 is shown, and taking a memory cell as an example, the transistor 210 may specifically include a semiconductor layer 211 and a gate structure 212.

The semiconductor layer 211 includes a source region 2111, a channel region (not shown in the figure), and a drain region 2113, and the source region 2111, the channel region, and the drain region 2113 are sequentially disposed along a length direction of the semiconductor layer 211, and taking the case where the semiconductor layer 211 extends along an X direction in the figure as an example, the source region 2111, the channel region, and the drain region 2113 may be sequentially disposed along the X direction. The gate structure 212 contacts the channel region of the semiconductor layer 211, and the gate structure 212 is electrically connected to the word line 300, and the word line 300 controls the transistor 210 to be turned on and off through the gate structure 212. Illustratively, the gate structure 212 may be connected to an outer wall surface of the channel region of the semiconductor layer 211, and the word line 300 and a surface of the gate structure 212 facing away from the semiconductor layer 211, that is, the gate structure 212 is disposed between the semiconductor layer 211 and the word line 300.

The gate structure 212 may include, for example, a gate dielectric layer (not shown) which is an insulating layer and a gate electrode layer (not shown) which is a metal layer, the gate dielectric layer covers an outer wall surface of the channel region, the gate electrode layer covers an outer wall surface of the gate dielectric layer, and the word line 300 is connected to the gate electrode layer.

It should be noted that the present embodiment is described by taking the word line 300 controlling the transistor 210 to be turned on and off through the gate structure 212 as an example. In practical applications, the transistor 210 may not be provided with the gate structure 212, but the on and off of the transistor 210 is directly controlled by the word line 300, which is not limited in this embodiment.

For example, when the semiconductor layer 211 is fabricated, taking the initial layer structure as a P-type doped silicon layer as an example, the portions of the layer structure corresponding to the source region 2111 and the drain region 2113 at two sides may be doped N-type, and taking the initial layer structure as an N-type doped silicon layer as an example, the portion of the layer structure corresponding to the middle of the channel region may be doped P-type, so as to form the semiconductor layer 211 having the source region 2111 and the drain region 2113 doped N-type at two sides and the channel region doped P-type at the middle, so that the semiconductor layer 211 has semiconductor properties.

As for the electrical connection of the word line 300 and the bit line 400 to the transistor 210 parallel to the planar direction of the substrate 100, the word line 300 may be connected to the outer wall surface of the gate structure 212, the source region 2111 of the semiconductor layer 211 is connected to the bit line 400, and the drain is connected to the capacitor 230. A voltage signal applied to the word line 300 is applied to the gate structure 212, charges are injected into the channel region through the gate structure 212, the source region 2111 and the drain region 2113 are turned on, the semiconductor layer 211 is made conductive, the transistor 210 is turned on, the bit line 400 and the capacitor 230 are electrically connected, and data stored in the capacitor 230 is read through the bit line 400 or data is written into the capacitor 230 through the bit line 400 and stored.

Referring to fig. 5, as an embodiment, the word line 300 may be parallel to the planar direction of the substrate 100, and the word line 300 is in contact with the surface of the gate structure 212 to electrically connect the word line 300 and the gate structure 212; at this time, the bit line 400 may extend in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, the bit line 400 may be connected to the outer wall surface of the source region 2111 of the semiconductor layer 211, and the capacitor 230 may be connected to the outer wall surface of the drain region 2113. As shown in fig. 4, taking the length direction of the semiconductor layer 211 as the X direction in the figure as an example, the word line 300 may extend along the Y direction in the figure, that is, the first direction in which the word line 300 extends is the Y direction, and the word line 300 is connected to the gate structures 212 of all the transistors 210 in the Y direction.

As another embodiment, in the case where the gate structure 212 covers the sidewall surface of the channel region extending in the Z direction shown in the figure, the word line 300 may also extend in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, and the word line 300 may be connected to the sidewall surfaces of the gate structures 212 of all the transistors 210 in the Z direction. At this time, the bit line 400 may extend in the horizontal direction of the three-dimensional semiconductor structure 1, for example, the bit line 400 extends in the Y direction shown in the figure, and the bit line 400 is connected to the source regions 2111 of all the transistors 210 in the Y direction.

In order to facilitate the arrangement of the bit line 400 and the capacitor 230, for the way that the word line 300 is connected to the channel region in the middle of the semiconductor layer 211 in the length direction, the bit line 400 and the capacitor 230 may be connected to two ends of the semiconductor layer 211 in the length direction, respectively, so that a proper gap is provided between the word line 300 and the bit line 400 and between the word line 300 and the capacitor 230 to avoid mutual interference, and at this time, the capacitor 230 may extend along the horizontal direction of the three-dimensional semiconductor structure 1. The capacitor 230 extending in the horizontal direction occupies a smaller thickness space of the three-dimensional semiconductor structure 1, so that the stacking density of the transistors 210 in the thickness direction of the three-dimensional semiconductor structure 1 can be increased, and the integration level of the three-dimensional semiconductor structure 1 can be improved.

As the transistor 210 is suspended above the substrate 100, as described above, the transistor 210 is prone to a floating body effect, and for this, as shown in fig. 5, in this embodiment, each layer of the memory cell array 201 is provided with a plurality of connection pads 220, the connection pads 220 are also arranged in an array in the memory cell array 201, each transistor 210 has a corresponding connection pad 220 connected thereto, the connection pad 220 is electrically connected to the channel region of the semiconductor layer 211, the connection pad 220 is electrically connected to the substrate 100, the connection pad 220 is used for enabling charges remaining in the channel region to flow to the substrate 100, and the charges are discharged through the grounded substrate 100, so that the floating body effect of the transistor 210 is solved, and the performance of the three-dimensional semiconductor structure 1 is improved.

Specifically, for the semiconductor layer 211 extending in the horizontal direction of the substrate 100, in order to facilitate the arrangement and formation of the connection pad 220, the connection pad 220 may be arranged on the same layer as the semiconductor layer 211, for example, the connection pad 220 may be arranged on the lateral side of the semiconductor layer 211 in the width direction, and the connection pad 220 is connected to the sidewall of the semiconductor layer 211, thereby achieving electrical connection with the channel region of the semiconductor layer 211, and guiding and discharging charges remaining in the channel region to the substrate 100.

By arranging the connection pads 220 and the semiconductor layer 211 in the same layer, the connection pads 220 do not occupy an extra thickness space (Z-direction space) of the three-dimensional semiconductor structure 1, and more layers of the memory cell arrays 201 can be stacked under the condition that the thickness of the three-dimensional semiconductor structure 1 is not changed, so that the integration level of the three-dimensional semiconductor structure 1 can be improved, and the performance of the three-dimensional semiconductor structure 1 can be improved.

As for the formation of the connection pad 220, for example, the connection pad 220 may be formed simultaneously with the semiconductor layer 211, for example, the connection pad 220 and the semiconductor layer 211 are formed as an integral structure, the connection pad 220 may also be a P-type doped silicon layer, when the connection pad 220 and the semiconductor layer 211 are formed, the P-type doped silicon layer may be integrally formed, and then, the portions where the source region 2111 and the drain region 2113 are located may be N-type doped to form the source region 2111 and the drain region 2113 of the semiconductor layer 211, the region between the source region 2111 and the drain region 2113 serves as a channel region, and the region on the side of the channel region serves as the connection pad 220.

The bonding pad 220 should be kept with a relatively uniform P-type doping with a low concentration, so as to avoid forming PN junctions when the source region 2111 and the drain region 2113 of the semiconductor layer 211 have interfaces with the bonding pad 220. For example, when the regions corresponding to the source region 2111 and the drain region 2113 of the semiconductor layer 211 are doped N-type, the surface of the connection pad 220 may be covered so as not to affect the doping property of the connection pad 220.

In addition, the thickness of the connection pad 220 may be the same as that of the semiconductor layer 211, that is, the height of the connection pad 220 is the same as that of the semiconductor layer 211 in the thickness direction (Z direction) of the substrate 100. In this manner, for the connection pad 220 that is an integrally formed structure with the semiconductor layer 211, the formation of the connection pad 220 is facilitated, and for the gate structure 212 and the word line 300 that are formed on the semiconductor layer 211 and the connection pad 220, the formation of the gate structure 212 and the word line 300 is also facilitated.

Fig. 6 is a cross-sectional view at B-B of the three-dimensional semiconductor structure of fig. 4. As shown in fig. 4 and 6, when the connection pads 220 are provided, a single connection pad 220 may be provided for each semiconductor layer 211, that is, the connection pads 220 are provided in one-to-one correspondence with the semiconductor layers 211, and each connection pad 220 is connected to a side wall surface in the width direction of the corresponding semiconductor layer 211. At this time, for each of the semiconductor layers 211 arranged at intervals in the width direction (Y direction) of the semiconductor layer 211, the semiconductor layers 211 and the connection pads 220 are alternately arranged in the width direction (Y direction) of the semiconductor layer 211.

Hereinafter, the two side surfaces of the connection pad 220 in the width direction are respectively defined as a first side surface 220a and a second side surface 220b thereof, that is, the first side surface 220a of the connection pad 220 is opposite to the semiconductor layer 211 located at one side thereof, and the second side surface 220b of the connection pad 220 is opposite to the semiconductor layer 211 located at the other side thereof.

In order to realize the one-to-one connection between the connection pads 220 and the semiconductor layer 211, each connection pad 220 is connected to the sidewall surface of the semiconductor layer 211 on the same side, for example, in the direction shown in fig. 6, the left side of the connection pad 220 is the first side 220a thereof, the right side of the connection pad 220 is the second side 220b thereof, the first side 220a of the connection pad 220 may be connected to the semiconductor layer 211 on the left side thereof, and a gap is formed between the second side 220b of the connection pad 220 and the semiconductor layer 211 on the right side thereof. Of course, the second side 220b of the connection pad 220 may be connected to the semiconductor layer 211 on the right side thereof, and a gap is formed between the first side 220a of the connection pad 220 and the semiconductor layer 211 on the left side thereof, which is not limited in the present embodiment.

Fig. 7 is a cross-sectional view of another three-dimensional semiconductor structure provided in accordance with an embodiment of the present disclosure, corresponding to B-B in fig. 4. Referring to fig. 7, in some embodiments, the semiconductor layers 211 and the connection pads 220 may still be alternately disposed, but the connection pads 220 are not connected to the semiconductor layers 211 in a one-to-one correspondence, and at this time, the width of the connection pads 220 may extend to be connected to both sides of the semiconductor layers 211, that is, the first side 220a and the second side 220b of the connection pads 220 are respectively connected to the corresponding side wall surfaces of both sides of the semiconductor layers 211, and the connection pads 220 may guide and discharge charges remaining in the channel regions 2112 of the semiconductor layers 211 located at both sides thereof to the substrate 100.

Fig. 8 is a cross-sectional view of a third three-dimensional semiconductor structure provided in accordance with an embodiment of the present disclosure, corresponding to the point B-B in fig. 4. Referring to fig. 8, in other embodiments, the connection pads 220 may not be disposed alternately with the semiconductor layers 211, and one connection pad 220 may be disposed between every two semiconductor layers 211, where the connection pad 220 is connected to both sides of the semiconductor layers 211, that is, the first side 220a and the second side 220b of the connection pad 220 are respectively connected to the corresponding side wall surfaces of both sides of the semiconductor layers 211, and the connection pad 220 guides and discharges charges remaining in the channel regions 2112 of the semiconductor layers 211 located at both sides of the connection pad to the substrate 100.

Since the connection pads 220 are disposed on the same layer on the lateral sides of the semiconductor layer 211 in the width direction along the horizontal direction of the three-dimensional semiconductor structure 1, at least the lateral wall surfaces of the channel region 2112 in the width direction of the semiconductor layer 211 are used for being connected to the connection pads 220, and in the case where both lateral wall surfaces of the semiconductor layer 211 in the width direction are connected to the connection pads 220, the lateral wall surfaces of the channel region 2112 in the width direction cannot cover the gate structure 212, and in the case where one lateral wall surface of the semiconductor layer 211 in the width direction is connected to the connection pads 220, the density of the integration is increased, and the gap between the connection pads 220 and the adjacent semiconductor layer 211 is also small, so that the gate structure 212 does not cover the lateral wall surfaces of the channel region 2112 in order to facilitate the formation of the gate structure 212.

The gate structure 212 may cover only the surface of the channel region 2112 of the semiconductor layer 211 in the thickness direction, or the gate structure 212 may extend to cover a portion of the surface of the connection pad 220. It should be noted that, referring to fig. 6, in the case that there is a space between the connection pad 220 and the adjacent semiconductor layer 211, the gate structure 212 may extend to a partial width region covering the connection pad 220, or the gate structure 212 may also extend to the entire width region covering the connection pad 220. Referring to fig. 7, in case that the first side 220a and the second side 220b of the connection pad 220 are respectively connected to the semiconductor layer 211 at both sides, the gate structure 212 can extend only to a partial width region covering the connection pad 220 to isolate the gate structures 212 of the adjacent transistors 210.

Therefore, referring to fig. 5, in the present embodiment, the gate structure 212 may cover a surface of the channel region in the thickness direction, that is, the gate structure 212 covers at least one of a surface of the channel region facing the substrate 100 and a surface of the channel region facing away from the substrate 100. In order to enable the word line 300 to be connected to the gate structures 212 of the transistors 210 spaced along the width direction (Y direction) of the transistors 210, in the present embodiment, the word line 300 may extend along the planar direction of the three-dimensional semiconductor structure 1, specifically, along the width direction (Y direction) of the word line 300, and correspondingly, the bit line 400 may extend along the thickness direction (Z direction) of the three-dimensional semiconductor.

Taking the three-dimensional semiconductor structure 1 shown in fig. 5 as an example, the gate structure 212 covers a side surface of the semiconductor layer 211 facing away from the substrate 100, and accordingly, the word line 300 is disposed on a side surface of the transistor 210 facing away from the substrate 100, and the word line 300 is connected above the gate structure 212. In other embodiments, the gate structure 212 may also cover a side surface of the semiconductor layer 211 facing the substrate 100, and accordingly, the word line 300 is disposed on a side surface of the transistor 210 facing the substrate 100, and the word line 300 is connected below the gate structure 212. Alternatively, the gate structures 212 are disposed on both side surfaces of the semiconductor layer 211 in the thickness direction, and accordingly, two word lines 300 may be disposed corresponding to a row of the transistors 210 spaced apart in the width direction (Y direction) of the transistors 210, one word line 300 being connected above the gate structure 212 facing away from the substrate 100, and the other word line 300 being connected below the gate structure 212 facing toward the substrate 100.

With continued reference to fig. 5, in order to electrically connect the connection pads 220 to the substrate 100, a plurality of connection pillars 500 are further disposed in the three-dimensional semiconductor structure 1 in an array, and as shown in fig. 4, the connection pillars 500 are connected to the substrate 100 at the bottoms thereof, and the connection pillars 500 may extend in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1 and be arranged in an array along the planar direction of the three-dimensional semiconductor structure 1. For example, each of the connection pillars 500 corresponds to each of the connection pads 220 arrayed along the planar direction of the substrate 100, and the connection pillars 500 penetrate through the stacked structure 200, and a corresponding portion of the connection pillar 500 is connected to each of the connection pads 220 in the Z direction to electrically connect each of the connection pads 220 in the Z direction to the substrate 100, so that the residual charges in the channel region of each of the semiconductor layers 211 in the Z direction are guided to the substrate 100 and discharged.

In order to improve the integration of the three-dimensional semiconductor structure 1, in the present embodiment, the connection pillars 500 may not occupy a single planar space, for example, in the planar direction of the three-dimensional semiconductor structure 1, the connection pillars 500 may be located in the planar space where the connection pads 220 are located. At this time, the connecting upright 500 may be disposed through the connecting pad 220, that is, the connecting upright 500 is inserted into the connecting pad 220, and the connecting pad 220 is wrapped around the connecting upright 500, so as to connect the connecting pad 220 and the connecting upright 500.

In contrast, as shown in fig. 5, since the connection pads 220 are connected to the lateral sides of the semiconductor layer 211 in the width direction, in order to reduce the planar space occupied by the connection pads 220 and improve the integration level of the three-dimensional semiconductor structure 1, the connection pads 220 may extend along the length direction of the semiconductor layer 211, and the extension length of the connection pads 220 may be smaller than the length of the semiconductor layer 211, or the connection pads 220 may also extend to two ends thereof flush with two ends of the semiconductor layer 211.

The connection pad 220 may include a main body portion 221 and a connection portion 222, the main body portion 221 is correspondingly located on a lateral side of the channel region, the connection portion 222 is located on a lateral side of the main body portion 221, the main body portion 221 is used for achieving electrical connection with the channel region, the word line 300 covers the main body portion 221, the connection portion 222 is exposed outside the word line 300, the connection portion 222 is used for being connected with the connection stud 500, for example, the connection stud 500 may penetrate through the connection portion 222, so as to achieve guiding of charges remaining in the channel region to the substrate 100.

In fig. 5, the connection pad 220 is extended to have two ends flush with two ends of the semiconductor layer 211, and the connection portions 222 are disposed on two sides of the main body portion 221 of the connection pad 220, for convenience of description, the area of the connection pad 220 corresponding to the source region 2111 of the semiconductor layer 211 is defined as a first connection portion 2221, and the area of the connection pad 220 corresponding to the drain region 2113 of the semiconductor layer 211 is defined as a second connection portion 2222. Since the connection pad 220 has the first connection portion 2221 and the second connection portion 2222 located at both sides of the body portion 221, the connection pad 220 may be electrically connected to the substrate 100 through at least one of the first connection portion 2221 and the second connection portion 2222. For example, one connecting column 500 may be disposed corresponding to each connecting pad 220 in the Z direction, and the connecting column 500 penetrates through the first connecting portion 2221 or the second connecting portion 2222; alternatively, two connecting columns 500 may be disposed corresponding to the connecting pads 220 in the Z direction, and the two connecting columns 500 respectively penetrate through the first connecting portion 2221 and the second connecting portion 2222.

Fig. 9 is a perspective view of a memory cell of another three-dimensional semiconductor structure. Referring to fig. 9, the extending length of the connection pad 220 is shown to be less than the length of the semiconductor layer 211, specifically, the connection pad 220 corresponds to the channel region and the drain region 2113 of the semiconductor layer 211 along the length direction thereof, that is, the connection portion 222 of the connection pad 220 corresponds to the drain region 2113 only, at this time, a connection pillar 500 may be disposed corresponding to the connection pad 220 in the Z direction, and the connection pillar 500 penetrates through the connection portion 222 of the connection pad 220 corresponding to the drain region 2113.

In other embodiments, the connection pad 220 may also correspond to the source region 2111 and the drain region 2113 of the semiconductor layer 211 along the length direction thereof, that is, the connection portion 222 of the connection pad 220 corresponds to only the source region 2111, and at this time, a connection post may be disposed corresponding to the connection pad 220 in the Z direction, and the connection post penetrates through the connection portion 222 of the connection pad 220 corresponding to the source region 2111.

In addition, not shown in fig. 4, the stack structure 200 further includes a plurality of support layers (not shown) and a plurality of release layers (not shown). The support layer and the memory cell array 201 are alternately stacked on the substrate 100 in order in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1; the isolation layers are arrayed along the planar direction of the three-dimensional semiconductor structure 1, and the isolation layers are arranged at intervals along the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, and the isolation layers are located between adjacent transistors 210 and fill the remaining gaps of the stacked structure 200.

It should be noted that the support layer is provided to facilitate stacking of the memory cell array 201 in the thickness direction (Z direction) of the three-dimensional semiconductor structure 1, so as to support the memory cell array 201; on the other hand, adjacent memory cell arrays 201 can be electrically isolated from each other. The isolation layer is disposed to electrically isolate the adjacent transistors 210, thereby preventing the transistors 210 from interfering with each other.

The present embodiment also provides a method for fabricating a three-dimensional semiconductor structure 1, and the method for fabricating the three-dimensional semiconductor structure 1 can be used for fabricating the three-dimensional semiconductor structure 1.

Fig. 10 is a flowchart illustrating steps of a method for fabricating a three-dimensional semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 10, the method for fabricating the three-dimensional semiconductor structure 1 includes:

s100, providing a substrate.

As shown in fig. 4, a substrate 100 is provided, and the material of the substrate 100 may be single crystal silicon, polysilicon, amorphous silicon, silicon germanium compound, silicon-on-insulator, or the like, or the material of the substrate 100 may be other materials known to those skilled in the art.

S200, forming a stacking structure on the substrate; the stacked structure includes a plurality of memory cell arrays stacked in a thickness direction of the substrate, each memory cell array including a plurality of transistors and a plurality of connection pads arrayed in a planar direction of the substrate; wherein the content of the first and second substances,

As shown in fig. 4, when forming the stacked structure 200, a plurality of stacked layers may be sequentially formed on the substrate 100, and taking the three-dimensional semiconductor structure 1 including a stacked four-layer memory cell array 201 as an example, four stacked layers may be sequentially formed on the substrate 100, each stacked layer may include, for example, an insulating layer and a semiconductor material layer that are sequentially stacked, each stacked layer may be formed of, for example, a semiconductor material (e.g., silicon, germanium, or silicon germanium), and each insulating layer may be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride.

The insulating layer may be used as a support layer spaced between the memory cell arrays 201, and the semiconductor material layer is used to form the semiconductor layer 211 of each transistor 210.

As shown in fig. 4, after a plurality of stacked layers are formed, the semiconductor material layers are patterned by a photolithography process to form the semiconductor layer 211 and the connection pads 220 of each transistor 210, wherein each semiconductor material layer is patterned into a plurality of semiconductor layers 211 and a plurality of connection pads 220 arranged in an array along the planar direction of the substrate 100, and each semiconductor layer 211 and each connection pad 220 formed by patterning each semiconductor material layer stacked along the thickness direction of the substrate 100 are arranged at intervals along the thickness direction (Z direction) of the substrate 100.

Illustratively, after the semiconductor material layer is patterned, each pattern formed includes a region corresponding to the semiconductor layer 211 of the transistor 210 and a region corresponding to the connection pad 220, and taking the semiconductor material layer as a P-type doped silicon layer as an example, after the semiconductor material layer is patterned, N-type doping may be performed on the pattern corresponding to the source region 2111 and the drain region 2113 of the semiconductor layer 211 to form the source region 2111 and the drain region 2113 of the semiconductor layer 211, in the region covering the region corresponding to the semiconductor layer 211 of each pattern and the region corresponding to the connection pad 220.

After the semiconductor layer 211 and the connection pad 220 of the transistor 210 are formed, a gate structure 212 connected to each transistor 210 is formed in the stacked structure 200, and the gate structure 212 is connected to at least one of a surface of the semiconductor layer 211 facing the substrate 100 and a surface of the semiconductor layer 211 facing away from the substrate 100, so as to form each transistor 210 in the stacked structure 200. After the transistors 210 are formed, the gaps between the transistors 210 are filled with an insulating material to maintain electrical isolation between the transistors 210.

Thereafter, each word line 300 connected to the gate structure 212 of each transistor 210 is formed, and each bit line 400 and connecting pillar 500 penetrating the stacked structure 200 are formed. Finally, each capacitor 230 is formed in the stacked structure 200, such that the capacitor 230 is connected to the drain region 2113 of the semiconductor layer 211 of each transistor 210.

In the description of the present disclosure, it should be noted that the term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

It will be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the disclosure and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the disclosure.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A three-dimensional semiconductor structure, comprising:

a substrate;

the stacked structure is positioned on the substrate and comprises a plurality of memory cell arrays stacked along the thickness direction of the substrate, and each memory cell array comprises a plurality of transistors and a plurality of connecting pads which are arrayed along the plane direction of the substrate; wherein the content of the first and second substances,

2. The three-dimensional semiconductor structure of claim 1, wherein the connection pads alternate with the semiconductor layer along a width direction of the semiconductor layer.

3. The three-dimensional semiconductor structure according to claim 2, wherein the connection pads and the opposite sides of the semiconductor layer on the two sides thereof are respectively a first side and a second side, the first side is connected with the opposite semiconductor layer, and a gap is formed between the second side and the opposite semiconductor layer.

4. The three-dimensional semiconductor structure of claim 2, wherein the connection pads are connected to the semiconductor layers on both sides thereof.

5. The three-dimensional semiconductor structure of claim 1, wherein one of the connection pads is disposed between every two of the semiconductor layers, and the connection pad is connected to both of the semiconductor layers on both sides thereof.

6. The three-dimensional semiconductor structure of any of claims 1-5, further comprising:

the connecting upright columns are arranged in an array mode along the plane direction of the substrate, the connecting upright columns are connected to the substrate and extend along the thickness direction of the substrate, and the connecting upright columns are connected with the connecting pads in the extending direction of the connecting upright columns.

7. The three-dimensional semiconductor structure of claim 6, wherein the connection pad comprises a main body portion and a connection portion, the main body portion corresponds to the channel region, the connection portion is connected to a side of the main body portion along a length direction of the semiconductor layer, and the connection pillar penetrates through the connection portion.

8. The three-dimensional semiconductor structure of claim 7, wherein the connection portion corresponds to the source region or the connection portion corresponds to the drain region.

9. The three-dimensional semiconductor structure of claim 7, wherein the connection portion comprises a first connection portion corresponding to the source region and a second connection portion corresponding to the drain region, at least one of the first connection portion and the second connection portion being connected to the connection pillar.

10. The three-dimensional semiconductor structure according to any one of claims 1 to 5, wherein the transistor further comprises a gate structure covering at least one side surface in a thickness direction of the channel region.

11. The three-dimensional semiconductor structure of claim 10, wherein the gate structure covers both side surfaces in a thickness direction of the channel region.

12. The three-dimensional semiconductor structure of claim 10, wherein the gate structure extends to cover a portion of the surface of the connection pad.

13. The three-dimensional semiconductor structure of claim 10, further comprising:

a plurality of word lines covering the corresponding gate structures and extending in a width direction of the semiconductor layer, the word lines being stacked in a thickness direction of the substrate.

14. The three-dimensional semiconductor structure according to any of claims 1-5, wherein the thickness of the connection pad is the same as the thickness of the semiconductor layer in the thickness direction of the substrate.

15. A method for fabricating a three-dimensional semiconductor structure, comprising:

providing a substrate;

forming a stacked structure, the stacked structure being located on the substrate; the stacked structure comprises a plurality of memory cell arrays stacked along the thickness direction of the substrate, wherein each memory cell array comprises a plurality of transistors and a plurality of connecting pads which are arrayed along the plane direction of the substrate; wherein the content of the first and second substances,

the transistor comprises a semiconductor layer extending along the plane direction of the substrate, and a source region, a channel region and a drain region are sequentially arranged on the semiconductor layer along the length direction of the semiconductor layer; the connecting pad is arranged on the lateral side of the semiconductor layer in the width direction and connected with the semiconductor layer, the connecting pad is electrically connected with the substrate, and the connecting pad is electrically connected with the channel region.