CN115084110A

CN115084110A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN115084110A
Application number: CN202110273788.3A
Authority: CN
Inventors: 王美丽; 梁轩; 王飞; 王磊; 杨亚锋; 董学; 曹占锋; 王明星; 李付强; 张晨阳; 韩艳玲; 赵欣欣
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-03-12
Filing date: 2021-03-12
Publication date: 2022-09-20

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: the first substrate and the second substrate are oppositely arranged; a chip disposed on the first substrate, the chip including a chip body and a plurality of first terminals disposed on the chip body; a terminal extension layer disposed on the first substrate; and a plurality of second terminals provided on the second substrate. The terminal extension layer and the at least one first terminal are positioned on the same side of the chip main body, the semiconductor device further comprises a plurality of extension wires positioned in the terminal extension layer, and the plurality of extension wires are respectively electrically connected with the plurality of first terminals and used for leading out the plurality of first terminals; the orthographic projection of the plurality of extension wires on the first substrate completely covers the orthographic projection of the first terminals electrically connected with the extension wires on the first substrate. The plurality of first terminals are electrically connected with the plurality of second terminals through the plurality of extension wires respectively, and orthographic projections of the plurality of second terminals on the first substrate are at least partially overlapped with orthographic projections of the plurality of extension wires on the first substrate.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

In the current semiconductor devices such as display devices, it is usually necessary to use a plurality of different integrated circuits (abbreviated as ICs), including but not limited to driver ICs, touch ICs, ROICs, etc., which are connected to the display backplane through COFs or COG, etc., which are difficult to achieve organic integration between the display pixel units and different chips, occupy additional space outside the display backplane, and are difficult to achieve miniaturization and integration of the system. In addition, the size of Pad of the packaged chip pin is larger due to the low precision of the PCB and FPC process and the precision of the subsequent bonding process, thereby reducing the feasibility of chip miniaturization.

The above information disclosed in this section is only for understanding of the background of the inventive concept of the present disclosure, and therefore, the above information may contain information that does not constitute prior art.

Disclosure of Invention

In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same.

In one aspect, there is provided a semiconductor device including: a substrate; a chip disposed on the substrate, the chip including a chip body and a plurality of terminals disposed on the chip body; the semiconductor device comprises a substrate, a terminal extension layer arranged on the substrate, wherein the terminal extension layer comprises a conductive material, the terminal extension layer and at least one terminal are positioned on the same side of the chip main body, the semiconductor device further comprises a plurality of extension wires positioned in the terminal extension layer, and the plurality of extension wires are respectively electrically connected with the plurality of terminals and used for leading out the plurality of terminals; and the orthographic projection of at least one extension wire on the substrate completely covers the orthographic projection of the terminal electrically connected with the extension wire on the substrate.

According to some exemplary embodiments, the semiconductor device further comprises an adhesive layer disposed between the substrate and the chip body for fixing the chip on the substrate; and the chip body includes a first surface facing or contacting the adhesive layer, and at least one terminal is disposed on a surface of the chip body other than the first surface.

According to some exemplary embodiments, the substrate comprises a first substrate surface on which the chip is disposed, the first substrate surface comprising a first substrate edge; and the orthographic projection of at least one extension trace on the substrate is inclined relative to the edge of the first substrate.

According to some exemplary embodiments, the chip body has a second surface remote from the substrate, an orthographic projection of the second surface on the substrate having a regular shape, the orthographic projection of the second surface on the substrate including a first edge; and the first edge is inclined with respect to the first substrate edge.

According to some exemplary embodiments, a first included angle is formed between an extension line of an orthographic projection of the at least one extension trace on the substrate and an extension line of an edge of the first substrate, and the first included angle is greater than 0 ° and smaller than 90 °; and/or a second included angle is formed between the extension line of the first edge and the extension line of the first substrate edge, and the second included angle is larger than 0 degree and smaller than 90 degrees.

According to some exemplary embodiments, the substrate comprises a first substrate surface on which the chip is disposed; the chip body of the chip comprises a second surface, a first side surface and a second side surface, wherein the second surface and the first surface are respectively positioned at opposite sides of the chip body, the first side surface and the second side surface are respectively positioned at side surfaces of the chip body, and each of the first side surface and the second side surface is connected with the first surface and the second surface; and at least one of the first side surface and the second side surface is inclined with respect to the first substrate surface.

According to some exemplary embodiments, at least one extended trace is in direct contact with at least one terminal, and a portion of the at least one extended trace is in direct contact with one of the first side surface and the second side surface.

According to some exemplary embodiments, the semiconductor device further includes a first planarization layer disposed at one side of the chip and covering the terminal; and the terminal extension layer is positioned on one side of the first planarization layer, which is far away from the chip, and one end of the extension wiring is electrically connected with the terminal through a via hole or a groove which penetrates through the first planarization layer.

According to some exemplary embodiments, the semiconductor device further comprises a pad located at a side of the chip body close to the substrate, an orthographic projection of the pad on the substrate at least partially overlapping with an orthographic projection of the chip body on the substrate.

According to some exemplary embodiments, the semiconductor device further includes a first planarizing layer disposed on a side of the chip and covering the terminal, and a second planarizing layer disposed on a side of the first planarizing layer away from the substrate; the semiconductor device further comprises a first wire, wherein the first wire is positioned in the redistribution layer; and the rewiring layer is positioned on one side, far away from the chip, of the second planarization layer, and one end of the first routing wire is electrically connected with the extension routing wire through a via hole or a groove which penetrates through the first planarization layer and the second planarization layer.

According to some exemplary embodiments, the semiconductor device further comprises a functional device electrically connected to at least one terminal of the chip; and the functional device is located in a different layer than the chip.

According to some exemplary embodiments, the semiconductor device includes a plurality of repeating units arranged in an array along a first direction and a second direction on the substrate; each repeating unit includes a plurality of the chips, the plurality of chips located within each repeating unit are arranged on the substrate in an array along the first direction and the second direction, or at least a part of the plurality of chips located within each repeating unit are arranged on the substrate in an array along the first direction and the second direction; and in at least two of the plurality of repeating units, the relative position of at least one chip in one repeating unit in the repeating unit is different from the relative position of the corresponding chip in another repeating unit in the other repeating unit; and/or, in at least two of the plurality of repeating units, the orientation of at least one chip in one repeating unit in the repeating unit is different from the orientation of the corresponding chip in another repeating unit in the other repeating unit.

According to some exemplary embodiments, in at least two of the plurality of repeating units, a length of the extended trace for leading out the at least one terminal of the at least one chip in one repeating unit is not equal to a length of the extended trace for leading out the corresponding terminal of the corresponding chip in another repeating unit; and/or in at least two of the plurality of repeating units, the extending direction of the extended trace for leading out at least one terminal of at least one chip in one repeating unit is different from the extending direction of the extended trace for leading out the corresponding terminal of the corresponding chip in another repeating unit.

According to some exemplary embodiments, for two chips located in the same row along the first direction or the second direction, the chip body of each chip has a second surface far away from the substrate, an orthographic projection of the second surface on the substrate has a regular shape, a line connecting geometric centers of orthographic projections of the second surfaces of the chip bodies of the two chips on the substrate forms a third angle with the first direction or the second direction, and the third angle is greater than 0 ° and smaller than 90 °.

According to some exemplary embodiments, the chip includes a plurality of terminals each located on the second surface of the chip body of the chip; or, the chip comprises a plurality of terminals respectively located on the first side surface and the second side surface of the chip main body of the chip; alternatively, the chip includes a plurality of terminals on the first surface and the second surface of the chip body of the chip, respectively.

According to some exemplary embodiments, the chip comprises a first chip and a second chip, the first chip comprises at least two first terminals, the second chip comprises at least two second terminals; wherein the first chip and the second chip are configured to implement different functions, the first chip comprises at least one of a light emitting chip and a sensing chip, and the second chip comprises at least one of a sensing chip and a control chip; and one end of the at least one expanded wire is electrically connected with the first chip, and the other end of the at least one expanded wire is electrically connected with the second terminal.

According to some exemplary embodiments, the first chip includes a light emitting chip, and the first chip and the second chip are disposed at the same layer.

According to some exemplary embodiments, the first chip includes a light emitting chip, the first chip and the second chip are arranged at different layers; and the semiconductor device further comprises a driving element, wherein the driving element and the first chip are electrically connected through at least one extension wire.

According to some exemplary embodiments, the driving element is a driving chip, an orthographic projection of the driving chip on the substrate at least partially overlaps with an orthographic projection of the first chip on the substrate; and the first chip comprises a main light-emitting surface, and the main light-emitting surface is positioned on one side of the first chip, which is far away from the driving chip.

According to some exemplary embodiments, the driving element is a driving chip, and an orthographic projection of the driving chip on the substrate does not overlap with an orthographic projection of the first chip on the substrate; and the first chip comprises a main light-emitting surface, and the main light-emitting surface is positioned on one side of the first chip close to the driving chip.

According to some exemplary embodiments, the semiconductor device further includes a protection layer located on a side of the first chip away from the second chip, the protection layer covering the at least one terminal expansion layer and exposing the light emitting surface of the first chip.

According to some exemplary embodiments, the driving element includes a driving circuit for driving the first chip, the driving circuit including at least a thin film transistor at a different layer from the first chip and the second chip; and the thin film transistor at least comprises a source electrode and a drain electrode, and the source electrode or the drain electrode is electrically connected with at least one extension wiring through a through hole or a groove.

According to some exemplary embodiments, the first chip and the second chip are arranged in different layers; and the thin film transistor is positioned on one side of the first chip far away from the substrate, and the second chip is positioned on one side of the thin film transistor far away from the substrate.

According to some exemplary embodiments, the chip further comprises a third chip, the first chip, the second chip and the third chip being configured to implement different functions from each other; the semiconductor device includes at least one chip set, each chip set including at least one second chip and at least one third chip; the plurality of chip groups are electrically connected with the plurality of first chips in a one-to-one corresponding mode; alternatively, one chip group is electrically connected to a plurality of first chips.

According to some exemplary embodiments, the first chip includes a sensing chip, a plurality of sensing chips being connected in series; and the second chip comprises a control chip.

According to some exemplary embodiments, the sensing chip comprises at least one of a transducer chip and a piezoelectric sensing chip.

According to some exemplary embodiments, each of the sensing chips includes a first electrode, a second electrode, and a functional film interposed between the first electrode and the second electrode; the first electrodes of the multiple sensing chips are positioned on the same layer, and the second electrodes of the multiple sensing chips are positioned on the same layer; and in two adjacent sensing chips, the first electrode of one sensing chip is electrically connected with the second electrode of the other sensing chip through a through hole or a groove.

According to some exemplary embodiments, each of the sensing chips includes a first electrode, a second electrode, and a functional film interposed between the first electrode and the second electrode; the semiconductor device includes a plurality of sensor chip groups and a plurality of conductive parts, each sensor chip group including at least two sensor chips; the plurality of sensing chip groups are respectively arranged on the plurality of conductive parts, and the plurality of conductive parts are arranged at intervals; and in one sensing chip group, the first electrode of one sensing chip and the second electrode of the other sensing chip in any two adjacent sensing chips are in contact with the same conductive part.

According to some exemplary embodiments, the semiconductor device further includes a second planarization layer covering the plurality of sensor chips and a second terminal extension layer disposed on a side of the second planarization layer away from the substrate, the second terminal extension layer including a plurality of second extension traces; and in two adjacent sensing chip groups, the first electrode of the sensing chip of one sensing chip group is electrically connected with the second electrode of the sensing chip of the other sensing chip group through at least one second extension routing wire and a through hole or a groove penetrating through the second planarization layer.

According to some exemplary embodiments, each of the sensing chips includes a first electrode, a second electrode, and a functional film interposed between the first electrode and the second electrode; the semiconductor device comprises a plurality of sensing chip groups and at least one conductive part, wherein each sensing chip group comprises at least two sensing chips; at least two sensing chip groups are arranged on the same conductive part; and in one sensing chip group, at least two sensing chips are stacked on the conductive part, the first electrode or the second electrode of one sensing chip closest to the conductive part is in contact with the conductive part, and the first electrode of one sensing chip in any two adjacent sensing chips is in contact with the second electrode of the other sensing chip.

According to some exemplary embodiments, the at least one chip further comprises a control chip; the control chip and the plurality of sensing chips are positioned on the same layer; the semiconductor device further comprises a second planarization layer covering the plurality of sensing chips and the control chip and a second terminal extension layer arranged on one side of the second planarization layer, which is far away from the substrate, wherein the second terminal extension layer comprises a plurality of second extension wires; and the first electrode or the second electrode of one sensing chip closest to the control chip is electrically connected with one terminal of the control chip through at least one second extension wire and a via hole or a groove penetrating through the second planarization layer.

According to some exemplary embodiments, the semiconductor device further includes: a plurality of pixels provided on the substrate, the plurality of pixels being arranged in an array in a row direction and a column direction; a gating chip including at least two ports; a plurality of row signal connection lines, one row signal connection line electrically connected to a plurality of pixels located in the same row; a plurality of column signal connection lines, one of which is electrically connected to a plurality of pixels located in the same column; and the first chip is electrically connected with the column signal connecting lines through the gating transistor, wherein the row signal connecting lines are electrically connected with the ports of the gating chip through first extension wires respectively, a plurality of first chips are electrically connected with the second chip through second extension wires, and the first extension wires and the second extension wires are positioned in the at least one terminal extension layer.

According to some exemplary embodiments, there is provided a display device including: a substrate; a plurality of chips disposed on the substrate, wherein each first chip includes at least two terminals, the chip including at least one selected from a light emitting diode chip, a sub-millimeter light emitting diode chip, and a micro light emitting diode chip; a driving circuit for driving the chip, the driving circuit including at least one thin film transistor; the semiconductor device further comprises a plurality of extension wires positioned in the at least one terminal extension layer, and the plurality of extension wires are respectively electrically connected with the plurality of terminals and used for leading out the plurality of terminals; the orthographic projection of at least one extension wire on the substrate covers the orthographic projection of a terminal electrically connected with the extension wire on the substrate; and one end of the at least one extension wire is electrically connected with the thin film transistor of the driving circuit.

In another aspect, there is provided a method of manufacturing a semiconductor device, the method comprising:

placing a chip on a substrate, wherein the chip comprises a chip body and a plurality of terminals disposed on the chip body; and

forming a terminal extension layer on one side of the chip far away from the substrate through a post-alignment process, wherein the terminal extension layer comprises a conductive material,

wherein the forming of the terminal extension layer on the side of the chip away from the substrate by the post-alignment process comprises:

photographing the substrate provided with the chip;

determining coordinates of a plurality of terminals by adopting an image recognition technology, and generating a graphic file of the terminals; forming a conductive material layer on one side of the chip far away from the substrate; and

etching the conductive material layer by a photolithography process according to the pattern file to form a plurality of extended traces in the terminal extension layer,

the plurality of extension wires are respectively electrically connected with the plurality of terminals and used for leading out the plurality of terminals; and

the orthographic projection of at least one extension wire on the substrate completely covers the orthographic projection of a terminal electrically connected with the extension wire on the substrate.

According to some exemplary embodiments, the photographing of the substrate provided with the chip includes:

photographing a first photographing region of a substrate provided with the chip; and

using a position calibration mark arranged on the substrate as an original point, translating the photographing device according to a fixed stepping distance to photograph a second photographing region of the substrate provided with the chip,

the number of times of photographing is related to the distribution density of the chips, and at least one chip is arranged in each photographing area.

According to some exemplary embodiments, the placing the chip on the substrate includes:

forming an adhesive layer on the substrate; and

and transferring the chip onto the adhesive layer by a transfer process so that the chip is fixed on the substrate through the adhesive layer.

According to some exemplary embodiments, the manufacturing method further comprises:

after forming at least one terminal extension layer on the side of the plurality of chips far away from the substrate through the post-alignment process, forming a driving element on the side of the terminal extension layer far away from the substrate,

wherein the driving element comprises a driving chip or a driving circuit having a thin film transistor.

forming a driving element on a substrate before placing a plurality of chips on the substrate,

According to some exemplary embodiments, the forming at least one terminal extension layer on a side of the plurality of chips away from the substrate by a post-alignment process includes:

directly forming a first terminal extension layer on the chip, and forming a first extension wire in the first terminal extension layer through a photoetching process, so that one end of the first extension wire is in contact with the first terminal, and a part of the first extension wire is in contact with the side wall of the chip.

According to some exemplary embodiments, the manufacturing method further comprises: forming a first planarization layer on one side of the chip away from the substrate, wherein the first planarization layer covers the terminal of the chip; and

forming a plurality of vias or recesses in the first planarization layer by a photolithography process, the plurality of vias or recesses respectively exposing at least a portion of terminals of the chip,

and forming a terminal extension layer on one side of the first planarization layer, which is far away from the substrate, and forming an extension wire in the terminal extension layer through a post-alignment process, so that one end of the extension wire is in contact with the terminal through the via hole or the groove.

According to some exemplary embodiments, the forming of the terminal extension layer on the side of the chip away from the substrate by the post-alignment process includes:

forming a terminal extension layer through the post-alignment process;

forming a first planarization layer on one side of the terminal expansion layer away from the substrate;

forming a plurality of vias or recesses in the first planarization layer by a photolithography process, the plurality of vias or recesses exposing at least a portion of the terminal expansion layer; and

forming a rewiring layer on the side of the first planarization layer away from the substrate,

wherein the manufacturing method further comprises:

and using the terminal extension layer as a seed layer, and plating a metal layer in an electrochemical mode to grow a conductive connecting part with the same thickness as that of the first planarization layer in the plurality of through holes or grooves, wherein the conductive connecting part is used for electrically connecting the terminal extension layer and the redistribution layer.

in the post-alignment process, determining the coordinate information of the bad point by adopting an image recognition technology; and

and etching the conductive material layer through the photoetching process based on the coordinate information so as to form at least one extension routing line for repairing the bad point in the terminal extension layer.

In yet another aspect, a semiconductor device is provided, the semiconductor device including: a substrate; a plurality of chips disposed on the substrate, each chip including a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection portions provided to the substrate; a terminal extension layer disposed on the substrate, the terminal extension layer including a conductive material, wherein the plurality of fixed connection portions are disposed adjacent to the plurality of chips, respectively; the semiconductor device also comprises a plurality of extension wires positioned in the terminal extension layer, and the extension wires are used for electrically connecting the plurality of chips; the extension wiring for electrically connecting the two chips at least comprises a first wiring section and a second wiring section, the first wiring section is used for electrically connecting a terminal of one chip and a fixed connecting part adjacent to the chip, and the second wiring section is used for connecting the two fixed connecting parts between the two chips.

According to some exemplary embodiments, the at least one second route segment extends in the first direction; and in two chips electrically connected through an extended trace including a second trace segment extending in a first direction, a relative position of one chip in the first direction is different from a relative position of the other chip in the first direction.

According to some exemplary embodiments, in two chips electrically connected by an extended trace comprising at least one second trace segment, at least one chip is tilted with respect to an extension of said second trace segment.

According to some exemplary embodiments, in two chips electrically connected by an extended trace including at least one second trace segment, an orientation of one chip with respect to an extension of the second trace segment is different from an orientation of the other chip with respect to an extension of the second trace segment.

According to some exemplary embodiments, in two chips electrically connected by an extended trace comprising at least one second trace segment, each chip comprises a plurality of terminals comprising at least a first terminal and a second terminal; the second routing segments included by the extended routing for electrically connecting the first terminals of the two chips and the second routing segments included by the extended routing for electrically connecting the second terminals of the two chips are parallel to each other, and/or the second routing segments included by the extended routing for electrically connecting the first terminals of the two chips and the second routing segments included by the extended routing for electrically connecting the second terminals of the two chips are substantially equal in length.

According to some exemplary embodiments, at least one first trace segment and a second trace segment adjacent to and electrically connected to it have an angle therebetween, the angle being greater than 0 ° and less than 180 °.

According to some exemplary embodiments, in two first routing segments adjacent to and electrically connected with the same second routing segment, an included angle between one first routing segment and the second routing segment adjacent to and electrically connected with it is different from an included angle between the other first routing segment and the second routing segment adjacent to and electrically connected with it.

According to some exemplary embodiments, in two first routing segments electrically connected to the first terminal and the second terminal of the same chip, an included angle between one first routing segment and a second routing segment adjacent to and electrically connected to it is different from an included angle between the other first routing segment and a second routing segment adjacent to and electrically connected to it.

According to some exemplary embodiments, a plurality of the first trace segments are located in the same layer; and the second routing section and the first routing section are positioned in the same layer or different layers.

According to some exemplary embodiments, there is provided a display device including: a substrate; a plurality of pixels provided on the substrate, the plurality of pixels being arranged in an array along a first direction and a second direction; a plurality of chips disposed on the substrate, each chip including a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection portions provided to the substrate; at least one terminal extension layer disposed on the substrate, the terminal extension layer comprising a conductive material, wherein the plurality of fixed connections are disposed adjacent to the plurality of chips, respectively; the semiconductor device also comprises a plurality of extension wires positioned in the at least one terminal extension layer, and the extension wires are used for electrically connecting the plurality of chips; the extended routing for electrically connecting the two chips at least comprises a first routing section and a second routing section, wherein the first routing section is used for electrically connecting a terminal of one chip and a fixed connecting part adjacent to the chip, and the second routing section is used for connecting two fixed connecting parts between the two chips; and at least one chip is tilted with respect to the first direction and the second direction.

According to some exemplary embodiments, the plurality of chips are arranged in an array along a first direction and a second direction; and at least one first trace segment is slanted with respect to the first direction and the second direction.

According to some exemplary embodiments, the second running line segment extends along the first direction or the second direction.

In still another aspect, there is provided a method of manufacturing a semiconductor device, the method comprising:

placing a plurality of chips on a substrate, wherein each chip comprises a chip body and a plurality of terminals disposed on the chip body;

forming a plurality of fixed connection portions on the substrate; and

forming a terminal extension layer on one side of the plurality of chips far away from the substrate through a post-alignment process, wherein the terminal extension layer comprises a conductive material,

wherein the forming of the terminal extension layer on the side of the plurality of chips away from the substrate by the post-alignment process comprises:

photographing the substrate provided with the plurality of chips and the plurality of fixed connection parts;

determining the coordinates of the terminals of each chip by adopting an image recognition technology to generate a graphic file of the terminals;

forming a conductive material layer on one side of the chips far away from the substrate; and

the extension wires are used for being electrically connected with the plurality of chips, the extension wires used for being electrically connected with the two chips at least comprise a first wire section and a second wire section, the first wire section is used for being electrically connected with a terminal of one chip and a fixed connecting part adjacent to the chip, and the second wire section is used for connecting the two fixed connecting parts between the two chips.

According to some exemplary embodiments, the generating of the graphic file of the terminal comprises:

determining the coordinates of the terminals of each chip by adopting an image recognition technology;

reading preset coordinates of each fixed connecting part; and

and generating a terminal graphic file according to the determined coordinates of the terminals of the chips and the read preset coordinates of the fixed connecting parts.

According to some exemplary embodiments, the photographing of the substrate provided with the plurality of chips and the plurality of fixed connection parts includes:

photographing a first photographing region of the substrate provided with the plurality of chips and the plurality of fixed connection parts; and

translating the photographing apparatus by a fixed stepping distance with an integral absolute coordinate calibration mark disposed on the substrate as an origin to photograph a second photographing region of the substrate provided with the plurality of chips and the plurality of fixed connection portions,

According to some exemplary embodiments, there is an overlapping photographed area between at least two photographed areas.

forming an integral absolute coordinate calibration mark and a plurality of position calibration marks on the substrate,

the plurality of position calibration marks are respectively in one-to-one correspondence with the plurality of photographing regions.

In still another aspect, there is provided a semiconductor device including: the first substrate and the second substrate are oppositely arranged; a chip disposed on the first substrate, the chip including a chip body and a plurality of first terminals disposed on the chip body; a terminal extension layer disposed on the first substrate, the terminal extension layer comprising a conductive material; the semiconductor device further comprises a plurality of extension wires positioned in the terminal extension layer, wherein the plurality of extension wires are respectively electrically connected with the plurality of first terminals and used for leading out the plurality of first terminals; the orthographic projection of the plurality of extension wires on the first substrate completely covers the orthographic projection of the first terminals electrically connected with the extension wires on the first substrate; and the plurality of first terminals are electrically connected with the plurality of second terminals through the plurality of extension wires respectively, and orthographic projections of the plurality of second terminals on the first substrate are at least partially overlapped with orthographic projections of the plurality of extension wires on the first substrate.

According to some exemplary embodiments, the semiconductor device further includes a plurality of driving elements disposed on the second substrate, the plurality of second terminals are located on a side of the plurality of driving elements away from the second substrate, and the plurality of second terminals are electrically connected to the plurality of driving elements, respectively.

According to some exemplary embodiments, the chip comprises a plurality of first terminals each located at a side of the chip body of the chip remote from the first substrate; and the semiconductor device further comprises an adhesive layer disposed between the first substrate and the chip body for fixing the at least one chip on the first substrate.

According to some exemplary embodiments, the chip comprises a plurality of first terminals respectively located at two sides of a chip main body of the chip along a direction parallel to a first substrate surface of the first substrate, wherein the first substrate surface of the first substrate is a surface of the first substrate on which the chip is disposed; and the semiconductor device further comprises an adhesive layer disposed between the first substrate and the chip body for fixing the chip on the first substrate.

According to some exemplary embodiments, the chip comprises a plurality of first terminals respectively located at two sides of a chip body of the chip along a direction perpendicular to a first substrate surface of the first substrate, wherein the first substrate surface of the first substrate provides a surface of the chip for the first substrate; and the semiconductor device further includes an adhesive layer disposed between the first substrate and the chip main body, and a first conductive layer disposed between the adhesive layer and the chip, the first conductive layer being electrically connected to at least one first terminal of the chip adjacent to the first substrate.

According to some exemplary embodiments, the first substrate comprises a first substrate surface on which the chips are disposed, the first substrate surface comprising a first substrate edge; and the orthographic projection of at least one extension trace on the first substrate is inclined relative to the edge of the first substrate.

According to some exemplary embodiments, the chip body has a second surface remote from the first substrate, an orthographic projection of the second surface on the first substrate having a regular shape, the orthographic projection of the second surface on the first substrate including a first edge; and the first edge is inclined with respect to the first substrate edge.

placing a chip on a first substrate, wherein the chip comprises a chip body and a plurality of first terminals disposed on the chip body;

forming a terminal extension layer on one side of the chip far away from the first substrate through a post-alignment process, wherein the terminal extension layer comprises a conductive material;

forming a plurality of second terminals on a second substrate; and

the first substrate and the second substrate are sealed so that the plurality of first terminals are electrically connected to the plurality of second terminals, respectively,

wherein the forming of the terminal extension layer on the side of the chip away from the first substrate by the post-alignment process comprises:

photographing the substrate provided with the chip;

determining the coordinates of a first terminal of the chip by adopting an image recognition technology to generate a graphic file of the first terminal;

forming a conductive material layer on one side of the chip far away from the first substrate; and

wherein, the orthographic projection of the plurality of extension wires on the first substrate completely covers the orthographic projection of the first terminal electrically connected with the extension wires on the first substrate; and

the plurality of first terminals are electrically connected with the plurality of second terminals through the plurality of extension wires respectively, and orthographic projections of the plurality of second terminals on the first substrate are at least partially overlapped with orthographic projections of the plurality of extension wires on the first substrate.

According to some exemplary embodiments, the placing the chip on the first substrate includes:

forming an adhesive layer on the first substrate; and

and transferring the chip to the adhesive layer by a transfer process so that the chip is fixed on the first substrate through the adhesive layer.

Drawings

Other objects and advantages of the present disclosure will become apparent from the following description of the disclosure, which is made with reference to the accompanying drawings, and can assist in a comprehensive understanding of the disclosure.

Fig. 1 schematically illustrates a block diagram of a display apparatus according to some exemplary embodiments of the present disclosure.

Fig. 2 is a schematic diagram schematically illustrating an arrangement of a plurality of chips in a display substrate according to an embodiment of the present disclosure.

Fig. 3A to 3C are schematic views each schematically showing a relative positional relationship between a functional unit group and a display region in a display substrate according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram schematically illustrating a registration relationship between a terminal (pad) on a substrate and a terminal (pad) on a chip in a semiconductor device (e.g., a display substrate) according to an embodiment of the present disclosure.

Fig. 5A-5D are schematic diagrams schematically illustrating some steps of a post-alignment process according to an embodiment of the present disclosure.

Fig. 6A and 6B are a schematic cross-sectional view and a schematic top view, respectively, of a microchip according to an embodiment of the disclosure.

Fig. 7A, 7B and 7C are perspective and cross-sectional schematic views, respectively, of a microchip and an extended trace in a terminal extension layer according to an embodiment of the disclosure.

Fig. 8A, 8B and 8C are cross-sectional schematic views of an expansion trace in a microchip and terminal expansion layer, respectively, according to some embodiments of the present disclosure.

Fig. 9 is a schematic diagram illustrating a structure formed by a chip first process according to an embodiment of the present disclosure.

FIG. 10 is a schematic diagram illustrating a structure formed by a chip later process according to an embodiment of the disclosure.

Fig. 11A and 11B are schematic diagrams of exemplary arrangements of chips and display units, respectively, included in a display device according to some embodiments of the present disclosure.

Fig. 12A to 12F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.

Fig. 13A to 13G are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.

Fig. 14 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure, where the display device can be a large-size display device or a tiled display device.

Fig. 15 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure, schematically illustrating an implementation of upward light emission.

Fig. 16 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure.

Fig. 17A to 17I are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.

Fig. 18 schematically illustrates a schematic cross-sectional view of a semiconductor device, in which terminals of a chip are located on two opposing sides of the chip, according to some embodiments of the present disclosure.

Fig. 19A to 19H are schematic cross-sectional views of a structure formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed, in which terminals of a chip are located on upper and lower surfaces of the chip.

Fig. 20A to 20F are schematic cross-sectional views of a structure formed after some steps of a manufacturing method of a display device including a TFT driving circuit according to an exemplary embodiment of the present disclosure are performed, and the manufacturing method is implemented by the above-described chip first process.

Fig. 21 is a partial enlarged view of portion I of fig. 20E.

Fig. 22 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the LED chip and the other chips are located in different layers.

Fig. 23 is a partially enlarged view of a portion II in fig. 22.

Fig. 24 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, in which the LED chips and other chips are located in different layers.

Fig. 25A to 25F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed, in which a driving element of the display device includes a TFT driving circuit, and the manufacturing method is implemented by the above-described chip later process.

Fig. 26A and 26B respectively schematically illustrate schematic cross-sectional views of a via hole of a display device according to an embodiment of the present disclosure.

Fig. 27 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the thin film transistor is a bottom gate type thin film transistor.

Fig. 28A and 28B are schematic block diagrams of acoustic sensors, respectively, according to some embodiments of the present disclosure.

Fig. 28C schematically illustrates an arrangement of acoustic sensors in a display, according to some embodiments of the present disclosure.

Fig. 29 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure, wherein the sensor is a Si-based sensor.

FIG. 30 schematically shows the increase in output voltage versus the number of transducers in series in a sensor according to an embodiment of the disclosure.

Fig. 31 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric sensor including a piezoelectric film.

Fig. 32 is a partially enlarged view of a portion III in fig. 31.

Fig. 33A to 33C are schematic cross-sectional views respectively illustrating structures formed after some steps of a manufacturing method of a sensor-integrated display device according to some embodiments of the present disclosure are performed, in which the sensor is a piezoelectric sensor including a piezoelectric thin film.

Fig. 34 is a schematic cross-sectional view of a sensor integrated display device according to some embodiments of the present disclosure.

Fig. 35A to 35E are schematic cross-sectional views of structures formed after some steps of a method of manufacturing a semiconductor device (e.g., a display device) according to an exemplary embodiment of the present disclosure are performed.

Figure 36A schematically illustrates a top view of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure.

Fig. 36B and 36C each schematically illustrate a top view of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure.

Fig. 37A and 37B are sectional views taken along line AA' in fig. 36B.

Fig. 38 schematically shows a partially enlarged view of the wiring between two chips.

Fig. 39A, 39B, and 39C schematically show shot regions formed in the post-alignment process, respectively.

Fig. 40A to 40C schematically show the arrangement of the driving chip and each pixel of the display device according to the embodiment of the present disclosure, respectively.

Fig. 41 schematically shows the projection relationship of the chip and the pixel.

Fig. 42 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure.

Fig. 43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure.

Fig. 44A and 44B are circuit connection diagrams of a display device including a gate chip according to an embodiment of the present disclosure, respectively.

It is noted that, for the sake of clarity, in the drawings used to describe embodiments of the present disclosure, the dimensions of layers, structures or regions may be exaggerated or reduced, i.e., the drawings are not drawn to scale.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments. It is evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Moreover, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

In the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or description. As such, the sizes and relative sizes of the respective elements are not necessarily limited to those shown in the drawings. While example embodiments may be practiced differently, the specific process sequence may be performed differently than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order reverse to the order described. In addition, like reference numerals denote like elements.

When an element is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar manner, e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent" or "over … …" versus "directly over … …", etc. Further, the term "connected" may refer to physical, electrical, communication, and/or fluid connections. Further, the X, Y, and Z axes are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments.

It is to be understood that an integrated circuit (abbreviated IC) is a way of miniaturizing circuits (including semiconductor devices, passive devices, etc.), for example, devices fabricated on the surface of a semiconductor wafer. For example, an integrated circuit may also be referred to as a microcircuit (microcircuit), a wafer, a chip (chip), or the like. Typically, integrated circuits are fabricated in large batches through multiple steps such as photolithography, on a large semiconductor wafer, and then are diced into individual dies. This die is referred to as a chip, and each chip is a collection of integrated circuits. The semiconductor material used for the wafer is typically a single crystal of electronic grade silicon or other semiconductor such as gallium arsenide.

It should be understood that a die (also referred to as die, or die) is an unpackaged, small integrated circuit made of semiconductor material, and the intended function of the integrated circuit is realized on the small semiconductor chip.

It is understood that in the field of integrated circuits, packaging is the process of assembling the integrated circuit into a chip end product, for example, placing the integrated circuit die on a substrate that serves as a carrier, extracting the pins, and then securing the package as a unit. Specifically, circuit pins on the integrated circuit die are wired to external connections to facilitate connection of other devices. The packaging structure not only plays the roles of mounting, fixing, sealing, protecting the chip, enhancing the electric heating performance and the like, but also is connected to pins of the packaging structure through the connecting points on the chip by leads, and the pins are connected with other devices through the leads on the printed circuit board, thereby realizing the connection of the internal chip and an external circuit.

In this document, the panel-level packaging technique is to attach a semiconductor die to a carrier, pull out the required circuits to a redistribution layer (RDL) at the terminals of the die, and form a package without a package carrier or wire bonding and bumps (Bump), thereby reducing the production cost.

In this context, the digital exposure process refers to a direct-write or maskless lithography process, which can be generally implemented using a digital exposure machine. For example, a wiring layer electrically connecting terminals of the chip may be formed on the substrate using a digital exposure process (i.e., without using a mask). Specifically, a plurality of chips can be transferred onto a substrate by a transfer process with low precision; the positions of all terminals of the chip on the substrate can be read by Mapping, or a chip picture is obtained by optical detection, and then the positions of all terminals are obtained by an algorithm; after the positions of the terminals are obtained, the coordinate information of the terminals is formed into a file which can be identified by a digital exposure machine, and the digital exposure machine can perform an exposure process on the conductive layer according to the file to form a wiring layer which is electrically connected with the terminals of the chip. In the process, the digital exposure process can automatically correct the position offset of each chip transferred to the substrate, for example, the precision of the digital exposure process can reach less than 1 μm, so the process difficulty caused by bonding can be greatly reduced, and the process precision is improved.

Herein, the expression "terminal" means a portion of the chip electrically connected to external leads, traces, electrodes, etc., including, but not limited to, the pad of the chip.

Herein, the "post alignment process" means a process for aligning terminals (e.g., pads) of a chip. For example, in the embodiment of the disclosure, a plurality of chips may be transferred onto a substrate by SMT or bulk transfer, and then parameters such as the position (e.g., coordinate information of each pad), area, and topography of the pad of each chip transferred onto the substrate are determined by an image analysis technique, and extended traces or leads electrically connected to the pads of each chip are formed based on the parameters by a high-precision patterning process such as a photolithography process, so as to achieve bonding of each chip. It should be appreciated that since the post-alignment process includes a high-precision patterning process such as a photolithography process, the precision thereof may be higher than that of the bulk transfer process. For example, the offset precision of the metal extension trace formed by the lithography machine is generally less than 0.6 micrometer, while the precision of the existing bulk transfer equipment is about 5-10 micrometers.

In addition, herein, the "post-alignment process" may be used to repair a defective spot, in addition to identifying a terminal of a chip for automatic wiring. For example, in the post-alignment process, the bad point can be identified and obtained, and the coordinate information of the bad point can be obtained; and then forming an extended trace or lead electrically connected to each defective point through a high-precision patterning process such as a photolithography process based on the coordinate information to repair each defective point.

It should be noted that, in this document, the expression "defective point" includes a terminal having an open circuit in its electrical connection path.

Herein, unless otherwise specifically stated, the expression "position", "relative position" means a position of a component such as a chip, a chip body, or the like in a spatial coordinate system, for example, in an XYZ coordinate system, may be represented by a coordinate value of X, Y, Z axes. The expression "orientation" indicates an angle of a chip, a chip body, or the like with respect to each coordinate axis in a spatial coordinate system, and for example, may be expressed as an angle with respect to the axis X, Y, Z in an XYZ coordinate system.

For example, maskless lithography techniques can be roughly divided into two categories: (1) charged particle maskless lithography, such as electron beam direct writing and ion beam lithography, etc. (2) Optical maskless technologies such as DMD maskless lithography, laser direct writing, interference lithography, diffractive optical element lithography, etc. Specifically, the DMD maskless lithography is a technology derived from the conventional optical lithography, the exposure imaging mode of which is basically similar to that of the conventional projection lithography, except that a digital DMD is used to replace the conventional mask, the main principle is to input the required lithography pattern into a DMD chip through software by a computer, change the rotation angle of the micromirror of the DMD chip according to the distribution of black and white pixels in the image, irradiate the DMD chip with a collimated light source to form a light image consistent with the required pattern, project the light image onto the substrate surface, and realize the preparation of large-area microstructure by controlling the movement of a sample stage. Electron beam lithography (often abbreviated as EBL) is a technique for drawing a custom pattern on a resist-covered surface using an electron beam. The electron beam changes the solubility of the resist and either the exposed or unexposed areas of the resist can be selectively removed by immersing it in a solvent (i.e., developing).

It should also be appreciated that Wire Bonding is a process that uses heat, pressure, or ultrasonic energy to bond metal Bonding wires tightly to substrate pads. For example, in IC packages, wire bonds may be used to connect semiconductor chip pads with I/O bonding wires of a microelectronic package or metal wiring pads on a substrate with metal filaments. The principle of wire bonding is that the oxide layer and pollution on the surface to be welded are damaged by heating, pressurizing or ultrasonic waves, plastic deformation is generated, so that the metal bonding wire is in close contact with the surface to be welded, the attractive force range among atoms is reached, and the atoms between interfaces are diffused to form a welding point.

Herein, the expression "light emitting chip" means a chip configured to emit light of a specific wavelength, for example, the light emitting chip may include a light emitting diode chip including, but not limited to, a MiniLED chip or a micro led chip.

In this context, an inorganic light emitting diode refers to a light emitting element made of an inorganic material, wherein LED means an inorganic light emitting element different from OLED. Specifically, the inorganic Light Emitting element may include a submillimeter Light Emitting Diode (MiniLED) and a Micro Light Emitting Diode (Micro led). The micro light emitting diode (i.e., micro LED) refers to a subminiature light emitting diode with a grain size of less than 100 micrometers, and the subminiature light emitting diode (i.e., MiniLED) refers to a small light emitting diode with a grain size between the micro LED and a conventional LED, for example, the grain size of the MiniLED may be between 100 and 300 micrometers, and the grain size of the micro LED may be between 10 and 100 micrometers.

Herein, SMT or SMT process means surface mount technology, and bulk transfer or mass transfer process is a technology for transferring a large number of micro chips onto a target substrate, for example, a common bulk transfer technology includes the following steps: picking up a microchip from a predetermined position with very high spatial accuracy and orientation; moving the microchips to predetermined positions while maintaining the relative spatial positions and orientations of the microchips; the microchips are then selectively dispensed onto the target substrate at the new location while maintaining the new relative position and orientation.

In this context, PVDF refers to a polyvinylidene fluoride material, which has piezoelectric properties.

Regarding the "chip size", the inventor has found that, after the chip is packaged, the chip size is increased by at least 20% compared to the original die size, and meanwhile, the size of the chip is also increased due to the integration of various functional modules in the chip. In embodiments of the present disclosure, a reduction in chip size may be achieved by disassembling the functionality of the chip and packaging the device (e.g., display substrate) that includes the chip. With the reduction of the chip size, the influence of the defects on the chip yield of each wafer (wafer) can be effectively reduced. Moreover, along with the reduction of the size of the chip, the yield is gradually improved, the equivalent diameter of the single wafer is continuously increased, the number of the chips produced by each wafer is increased, and therefore the cost of the chips can be greatly reduced.

Herein, unless otherwise specifically stated, the expressions "chip", "chip module", "microchip" and the like mean a chip of relatively small size, for example, an unpackaged micron-sized chip. Taking the display substrate as an example, the display substrate may include, but is not limited to, the following chips: the LED light source comprises a sensing chip, a control chip, a logic operation chip, a storage chip, a driving chip, an LED chip and other functional chips, and can also comprise sub-module chips such as a digital-to-analog conversion circuit, an amplifying circuit, a comparator, a counter and the like which are subdivided. It should be understood that the display substrate may include at least one of the chips described above.

In this document, unless otherwise specifically stated, the expression "functional device" may include a device for realizing a specific function, which may include a single chip, a chip set composed of a plurality of chips, or a circuit structure, and the like in various forms, for example, the functional device may include at least one of a thin film transistor and a sensor fabricated by a thin film process.

Herein, unless otherwise specifically stated, the expression "regular shape" denotes a regular pattern including, but not limited to, a rectangle, a rounded rectangle, a diamond, a square, a hexagon, an octagon, a circle, an ellipse, a rectangle, a triangle, and the like.

Some example embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; a chip disposed on the substrate, the chip including a chip body and a plurality of terminals disposed on the chip body; the semiconductor device comprises a substrate, a terminal extension layer arranged on the substrate, wherein the terminal extension layer comprises a conductive material, the terminal extension layer and at least one terminal are positioned on the same side of the chip main body, the semiconductor device further comprises a plurality of extension wires positioned in the terminal extension layer, and the plurality of extension wires are respectively electrically connected with the plurality of terminals and used for leading out the plurality of terminals; and the orthographic projection of at least one extension wire on the substrate completely covers the orthographic projection of the terminal electrically connected with the extension wire on the substrate. In the semiconductor device, the terminal of the chip is led out through the terminal extension layer, so that the bonding of the chip is facilitated.

For example, the semiconductor device includes: a substrate; a plurality of chips disposed on the substrate, each chip including a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection portions provided to the substrate; a terminal extension layer disposed on the substrate, the terminal extension layer including a conductive material, wherein the plurality of fixed connection portions are disposed adjacent to the plurality of chips, respectively; the semiconductor device also comprises a plurality of extension wires positioned in the terminal extension layer, and the extension wires are used for electrically connecting the plurality of chips; the extension wiring for electrically connecting the two chips at least comprises a first wiring section and a second wiring section, the first wiring section is used for electrically connecting a terminal of one chip and a fixed connecting part adjacent to the chip, and the second wiring section is used for connecting the two fixed connecting parts between the two chips. In the semiconductor device, the fixed connecting part is arranged, so that the electric connection among the chips is favorably realized.

For example, the semiconductor device includes: the first substrate and the second substrate are oppositely arranged; a chip disposed on the first substrate, the chip including a chip body and a plurality of first terminals disposed on the chip body; a terminal extension layer disposed on the first substrate, the terminal extension layer comprising a conductive material; the semiconductor device further comprises a plurality of extension wires positioned in the terminal extension layer, wherein the plurality of extension wires are respectively electrically connected with the plurality of first terminals and used for leading out the plurality of first terminals; the orthographic projection of the plurality of extension wires on the first substrate completely covers the orthographic projection of the first terminals electrically connected with the extension wires on the first substrate; and the plurality of first terminals are electrically connected with the plurality of second terminals through the plurality of extension wires respectively, and orthographic projections of the plurality of second terminals on the first substrate are at least partially overlapped with orthographic projections of the plurality of extension wires on the first substrate. In the semiconductor device, the terminal of the chip is led out through the terminal extension layer, so that the bonding between the chip and other components is favorably realized.

In the present specification, exemplary embodiments of the present disclosure will be described mainly by taking a display device such as a display substrate, a display panel, or a display device as an example. Embodiments of the present disclosure are not limited thereto, and may also be applied to other types of semiconductor devices including at least one chip. In this context, types of chips include, but are not limited to, light emitting chips, sensing chips, control chips, and driving chips, such as LED chips, analog circuit chips, digital circuit chips, memory chips, digital-to-analog conversion chips, sensing (acoustic, optical, electrical, etc.) chips, or other functional module chips.

For example, fig. 1 schematically illustrates a block diagram of a display device according to some exemplary embodiments of the present disclosure. Referring to fig. 1, in an embodiment of the present disclosure, a chip having an integrated function for the display apparatus may be split into a plurality of micro chips, each of which may have fewer functions than a chip having an integrated function, i.e., the chip having an integrated function may be split according to functions, and thus, a plurality of micro chips are provided in the display apparatus. It should be understood that each microchip is smaller in size than the chip with integrated functionality, e.g., each microchip may be an unpackaged, micron-scale chip. Accordingly, in this context, the size of the terminals on the microchip is smaller than that of the terminals of a conventional chip, for example, on the order of tens of microns, possibly even less than 10 microns. Thus, the traditional bonding process cannot meet the dimensional accuracy of the terminal on the microchip; furthermore, the precision of the existing bulk transfer process cannot meet the dimensional precision of the terminals on the microchip.

For example, in the display device, a plurality of chips may be provided, each of which may be used to implement one function. For example, the plurality of chips may include LED chips and display-related driving chips, memory chips, digital-to-analog conversion chips, and information processing chips. As shown in fig. 1, a control chip 1, a logic operation chip 2, a memory chip 3, a driver chip 4, and other functional chips 5 may be provided. The driving chip 4 may be electrically connected with the display unit 6.

For example, the display unit 6 may include one of an LCD display (liquid crystal display) unit, an OLED (organic light emitting diode) display unit, or an LED (inorganic light emitting diode) display unit.

Fig. 2 is a schematic diagram schematically illustrating an arrangement of a plurality of chips in a display substrate according to an embodiment of the present disclosure. Fig. 3A to 3C are schematic diagrams respectively schematically illustrating relative positional relationships between a functional unit group and a display region in a display substrate according to an embodiment of the present disclosure.

Referring to fig. 1 to 3C in combination, a plurality of chips having specific functions may be interconnected to form a functional unit group CU. For example, the control chip 1, the logic operation chip 2, the memory chip 3, the driver chip 4, and the other function chips 5 may be interconnected to form one function unit group CU.

For example, the display device may include a display substrate. The display substrate may include a display area AA and a non-display area NA. The display substrate may include a plurality of pixels PX located in the display area AA. For example, the plurality of functional unit groups CU may be arranged on the base substrate of the display substrate periodically or non-periodically. The plurality of functional unit groups CU may be located in the display area AA or may be located in the non-display area NA. Alternatively, some of the plurality of functional unit groups CU may be located in the display area AA, and other of the plurality of functional unit groups CU may be located in the non-display area NA.

For example, referring to fig. 3A, a plurality of functional unit groups CU may be respectively located in a plurality of pixels PX, for example, one functional unit group CU may be disposed in one pixel PX. Referring to fig. 3B, two or more pixels PX may share one functional unit group CU. Referring to fig. 3C, one functional unit group CU may be provided in some pixels PX, and no functional unit group CU may be provided in other pixels PX.

For example, the functional unit group CU may be disposed only in a specific pixel PX to realize an application with a low data amount requirement, for example, an application scenario such as eye tracking.

For example, a plurality of functional unit groups CU may be interconnected as needed to realize data interaction.

That is, a semiconductor device (e.g., a display device) according to an embodiment of the present disclosure includes a plurality of chips provided over a substrate. In the embodiment of the disclosure, through the post-alignment process, the electrical connection inside the chip, among the plurality of chips and between the chip and the display unit can be realized, and the problem of the wiring precision of the microchip is solved.

Fig. 4 is a schematic diagram schematically illustrating a registration relationship between a terminal (pad) on a substrate and a terminal (pad) on a chip in a semiconductor device (e.g., a display substrate) according to an embodiment of the present disclosure. Referring collectively to fig. 1-4, the plurality of chips described above may be transferred to a substrate, such as a substrate base, by a bulk transfer process. The alignment of the terminal p2 on the substrate with the terminal p1 on the chip can be achieved by a bulk transfer process. Limited by the precision of the bulk transfer process, a certain misalignment between terminal p2 on the substrate and terminal p1 on the chip may occur.

It should be noted that, in the embodiments of the present disclosure, the terminals (e.g., p1) on the chip and the terminals (e.g., p2) on the substrate do not need to coincide, and the terminals (e.g., p1) on the chip and the terminals (e.g., p2) on the substrate in at least a part of the regions are not in face-to-face contact. The "a certain misalignment may occur between the terminal p2 on the substrate and the terminal p1 on the chip" described in the above description may be understood as a positional deviation caused by a misalignment between the terminal p1 on the chip and its ideal position that may occur during chip transfer.

For example, the terminals p2 on six pairs of substrates and the terminals p1 on the chip are schematically shown in fig. 4. In fig. 4, a small-sized dashed box indicates a position where the terminal p2 is located, and a large-sized dashed box indicates an ideal position where the terminal p1 is located (i.e., a position where the terminal p1 is located in accurate alignment with the terminal p 2). For convenience of description, the terminals are described as a first pair of terminals, a second pair of terminals, a third pair of terminals, a fourth pair of terminals, a fifth pair of terminals, and a sixth pair of terminals, respectively, from top to bottom and from left to right. In the first pair of terminals, terminal p1 is in its ideal position, in which case terminal p2 is precisely aligned with terminal p 1; in the second pair of terminals, terminal p1 is offset to the left by a distance relative to its ideal position, resulting in terminal p1 being offset to the left by a distance relative to terminal p 2; in the third pair, terminal p1 is offset upwardly a distance from its ideal position, resulting in terminal p1 being offset upwardly a distance from terminal p 2; in the fourth pair of terminals, terminal p1 is offset to the right by a distance relative to its ideal position, resulting in terminal p1 being offset to the right and upward by a distance relative to terminal p 2; in the fifth pair of terminals, terminal p1 is angularly deflected clockwise relative to its ideal position, resulting in terminal p1 being angularly deflected clockwise relative to terminal p 2; in the sixth pair of terminals, terminal p1 is angularly deflected counterclockwise relative to its ideal position, resulting in terminal p1 being angularly deflected counterclockwise relative to terminal p 2. That is, in an actual bulk transfer process, the following may occur: the terminal p1 is precisely aligned with the terminal p2, the terminal p1 is offset a distance in at least one of the first and second directions relative to the terminal p2, and the terminal p1 is offset an angle relative to the terminal p 2.

With continued reference to fig. 4, the semiconductor device may include a plurality of repeating units PU arranged in an array on the substrate along the first direction D1 and the second direction D2. Each of the repeating units PU may include a plurality of the chips, and the plurality of chips located within each of the repeating units PU are arranged on the substrate in an array along the first direction D1 and the second direction D2, or at least a portion of the plurality of chips located within each of the repeating units PU are arranged on the substrate in an array along the first direction and the second direction.

It should be noted that, in the illustrated embodiment, 2 repeating units PU are schematically shown, each repeating unit PU includes 3 chips, however, these numbers should not be considered as limiting the embodiments of the present disclosure.

For example, in at least two of the plurality of repeating units PU, the relative position of at least one chip in one repeating unit PU in the repeating unit is different from the relative position of the corresponding chip in another repeating unit PU in the other repeating unit.

In at least two of the plurality of repeating units PU, an orientation of at least one chip in one repeating unit in the repeating unit is different from an orientation of a corresponding chip in another repeating unit in the other repeating unit.

In at least two of the plurality of repeating units PU, the length of the extended trace used for leading out at least one terminal of at least one chip in one repeating unit is not equal to the length of the extended trace used for leading out the corresponding terminal of the corresponding chip in another repeating unit.

In at least two of the plurality of repeating units PU, an extending direction of the extended trace for leading out at least one terminal of at least one chip in one repeating unit is different from an extending direction of the extended trace for leading out a corresponding terminal of a corresponding chip in another repeating unit.

In the embodiment of the present disclosure, the expression "corresponding chip" may be understood as a chip located at a corresponding position in each repeating unit, for example, in the embodiment shown in fig. 4, a chip located at the leftmost side in one repeating unit located at the upper side and a chip located at the leftmost side in another repeating unit located at the lower side are mutually corresponding chips.

In the embodiment of the present disclosure, an extended trace at a terminal extension layer (i.e., RDL) may be formed by using a post-alignment process to electrically connect the terminal p1 and the terminal p 2. For example, the positions of the terminal p1 and the terminal p2 can be identified by a photographing method, a photolithographic pattern is designed according to the positions of the terminal p1 and the terminal p2, exposure is performed by using a maskless lithography technology, and a plurality of extension traces RL are formed in the terminal extension layer RDL. Based on the designed photoetching pattern, the plurality of extension traces RL are electrically connected with the terminal p1 and the terminal p2 according to the design requirement. In the embodiment of the disclosure, the alignment precision of a massive transfer process does not need to be improved, the electric connection inside the microchip and among the microchips can be realized, and the wiring precision of the microchip is improved.

Fig. 5A-5D are schematic diagrams schematically illustrating some steps of a post-alignment process according to an embodiment of the present disclosure. Referring to fig. 5A, a plurality of chips CP may be formed on the carrier SUB1, for example, the plurality of chips CP may be formed in an array on the carrier SUB1, or the plurality of chips CP may be formed on the carrier SUB1 non-periodically. For example, the "chip CP" herein may be the above-mentioned microchip, including but not limited to the above-mentioned LED chip, control chip 1, logic operation chip 2, memory chip 3, driving chip 4, and other functional chips 5.

Referring to fig. 5B, a plurality of chips CP are transferred onto a substrate SUB2 by a bulk transfer process. For example, the substrate SUB2 may have an adhesive layer AD1 disposed thereon. The adhesive layer AD1 may serve to secure the chip. The adhesive layer AD1 may be full-face or patterned. Then, a plurality of extension traces may be formed through a post-alignment process. Specifically, referring to fig. 5C, a metal layer ML1 and a photoresist layer PR1 may be deposited on the chip CP, and then, a patterned photoresist layer PR1 may be formed through a patterning process. Referring to fig. 5D, the metal layer ML1 is etched to form a patterned metal layer ML1, the patterned metal layer ML1 is the terminal extension layer RDL, and a plurality of patterns formed in the terminal extension layer RDL are formed as a plurality of extension traces RL to electrically connect the respective terminals.

For example, in the embodiment shown in fig. 5C, the patterning process includes, but is not limited to, a digital exposure machine, laser direct writing, EBL, or other submicron exposure techniques.

In the embodiment of the present disclosure, the chip may be transferred onto the substrate by a bulk transfer process with low position accuracy, and then the chip with low position accuracy may be identified and analyzed by a post-alignment process, for example, the terminal p1 of the chip and the terminal p2 of the substrate may be identified and analyzed by photographing and image recognition methods, and the relative positional relationship between the terminals may be determined. Based on the results of the recognition and analysis, an automatic wiring file is generated. In the patterning process shown in fig. 5C, the photoresist layer PR1 may be patterned according to the automatic wiring file. Thus, automatic wiring and high-precision chip bonding can be realized, and integration of the microchip and the display unit can be realized. In addition, the post-alignment process has at least the following advantages: the precision of the post-alignment process depends on the alignment precision of optical exposure, and the alignment precision of the optical exposure is far higher than that of a mass transfer process, so that the post-alignment process is more suitable for bonding of a microchip; and the post-alignment process adopts exposure, development and etching processes, so that the method is more suitable for large-area and high-efficiency batch chip bonding.

For example, the shape and function of the chips on the same substrate may be the same or different. The pins of the terminals p1 of the chip are upward, the number of the pins is more than or equal to 2, and the sizes and the appearances of the terminals p1 can be the same or different. Fig. 6A and 6B are a schematic cross-sectional view and a schematic top view, respectively, of a microchip according to an embodiment of the disclosure. As shown in fig. 6A, a plurality of chips CP are provided on the same substrate SUB2, and the functions of the plurality of chips CP may be different. The shapes of the plurality of chips CP in the cross-sectional view and the top view may be different. For example, referring to fig. 6A, the chip CP may have various shapes such as a rectangle, a trapezoid, and the like in a cross-sectional view. Referring to fig. 6B, the chip CP may have various shapes such as a trapezoid, a rectangle, a diamond, a triangle, a circle, and an ellipse in a top view.

Fig. 7A, 7B and 7C are perspective and cross-sectional schematic views, respectively, of a microchip and an extended trace in a terminal extension layer according to an embodiment of the disclosure. As shown in fig. 7A and 7B, the chip CP has a trapezoidal shape in a cross-sectional view. In other words, at least one side of the chip CP is gentle, i.e., the slope angle of at least one side of the chip CP is less than 90 °, for example, less than 70 °. In this case, the extended trace may be directly led out from the terminal p1 of the chip CP, and as shown in fig. 7B, the extended trace RL led out from the terminal p1 of the chip CP may be formed on a side surface having an angle of inclination smaller than 90 °. For example, a terminal extension layer and at least one rewiring layer may be provided, which are referred to as terminal extension layer RDL1 and rewiring layer RDL2, respectively, for convenience of description, and accordingly, extension traces located in terminal extension layer RDL1 and rewiring layer RDL2 are referred to as extension trace RL1 and first trace RL2, respectively. As shown in fig. 7A, a planarization layer PLN1 may be provided between the terminal extension layer RDL1 and the rewiring layer RDL 2. Extended trace RL1 leads directly from terminal p1 of chip CP. The first routing RL2 is electrically connected with the extended routing RL1 through a via penetrating through the planarization layer PLN 1. In this way, terminals leading out of the chip can be realized, and the electrical connection between the terminals of the chip is facilitated.

As shown in fig. 7C, the chip CP has a substantially rectangular shape in a cross-sectional view. In other words, the side of the chip CP is steep, i.e., the slope angle of the side of the chip CP is substantially equal to 90 ° or close to 90 °, for example, in the range of 70 ° to 90 °. In this case, the extended trace is not suitable to be formed directly on the side of the chip CP, that is, to be led out directly from the terminal p1 of the chip CP. Planarization layer PLN1 may be formed first on the side of chip CP away from the substrate, and the height of planarization layer PLN1 is greater than the height of chip CP, so that planarization layer PLN1 may cover chip CP and its overlying terminal p 1. Then, the extension trace RL1 is formed through a post-alignment process. As shown in fig. 7C, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 provided on the substrate SUB2, a chip CP provided on the adhesive layer AD1, a planarization layer PLN1 provided on a side of the chip CP remote from the substrate, and an extended trace RL1 provided on a side of the planarization layer PLN1 remote from the substrate. The extension trace RL1 may be electrically connected with the terminal p1 through a via penetrating the planarization layer PLN 1. In this way, terminals leading out of the chip can be realized, and the electrical connection between the terminals of the chip is facilitated.

Referring to fig. 32 in combination, in the case where the chip CP has a substantially rectangular shape in a cross-sectional view, a planarization layer may be formed on at least one side of the chip CP to form a side having a smaller slope. In this way, similar to fig. 7A and 7B, the extension traces can be formed on the side of the planarization layer having the smaller slope.

Note that the planarizing layer PLN1 may have a single-layer or multi-layer structure.

Fig. 8A, 8B and 8C are cross-sectional schematic views of an expansion trace in a microchip and terminal expansion layer, respectively, according to some embodiments of the present disclosure. As shown in fig. 8A, in the semiconductor device according to the embodiment of the present disclosure, a plurality of chips CP are provided on a substrate SUB2, and a height difference exists between at least two chips CP. For convenience of description, the two chips having the height difference are referred to as a chip CP1 and a chip CP2, respectively.

As shown in fig. 8A, in the case that the height difference between the chip CP1 and the chip CP2 is smaller than the process limit of the post-alignment exposure process in the vertical direction, the wiring may be implemented by a one-step post-alignment process, that is, a layer of terminal extension layer RDL1 is formed by the one-step post-alignment process, and the terminals of both the chip CP1 and the chip CP2 may be led out by a plurality of extension traces RL1 located in the terminal extension layer RDL 1. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 provided on the substrate SUB2, chips CP1, CP2 provided on the adhesive layer AD1, a planarization layer PLN1 provided on a side of the chips CP1, CP2 away from the substrate, and a terminal extension layer RDL1 provided on a side of the planarization layer PLN1 away from the substrate. A plurality of extension traces RL1 are disposed in the terminal extension layer RDL 1. The height of the planarization layer PLN1 is greater than the height of each of the chips CP1, CP 2. A portion of extended trace RL1 may be electrically connected to terminal p1 of chip CP1 through a via that penetrates planarization layer PLN1, and another portion of extended trace RL1 may be electrically connected to terminal p1 of chip CP2 through a via that penetrates planarization layer PLN 1. In this way, terminals leading out of the chip CP1 and the chip CP2 can be realized, facilitating electrical connection between the respective terminals of the chips. By analogy, the terminals of the chips can be led out, and the electric connection among the terminals of the chips is facilitated.

As shown in fig. 8B, in the case that the height difference between the chip CP1 and the chip CP2 is larger than the process limit of the post-alignment exposure process in the vertical direction, the wiring can be implemented by at least two post-alignment processes, i.e., the post-alignment process and the wiring are performed on the thin chip CP1 first, and then the post-alignment process and the wiring are performed on the chip CP2 with different thickness ranges (e.g., thicker) sequentially. A planarization layer is required to be added between the next post-alignment process and the previous post-alignment process. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 provided on the substrate SUB2, chips CP1, CP2 provided on the adhesive layer AD1, a planarization layer PLN1 provided on a side of the chip CP1 remote from the substrate, a terminal extension layer RDL1 provided on a side of the planarization layer PLN1 remote from the substrate, a planarization layer PLN2 provided on a side of the terminal extension layer RDL1 remote from the substrate, and a heavy wiring layer RDL2 provided on a side of the planarization layer PLN2 remote from the substrate. An extension wiring RL1 is arranged in the terminal extension layer RDL1, and a first wiring RL2 is arranged in the redistribution layer RDL 2. The extended trace RL1 may be electrically connected to the terminal p1 of the chip CP1 through a via penetrating the planarization layer PLN1, and the first trace RL2 may be electrically connected to the terminal p1 of the chip CP2 through a via penetrating the planarization layer PLN 2. In this way, terminals leading out of the chip CP1 and the chip CP2 can be realized, facilitating electrical connection between the respective terminals of the chips.

As shown in fig. 8C, in the case where the height difference between the chip CP1 and the chip CP2 is greater than the process limit of the post-alignment exposure process in the vertical direction, the pad may be prepared first on the substrate, wherein the height difference of the chip-the process limit of the post-alignment exposure process in the vertical direction ≦ the height of the pad ≦ the height of the chip ≦ the height difference of the chip; then, the wiring may be realized by a one-step post-alignment process. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 provided on the substrate SUB2, a pad PS provided on the adhesive layer AD1, a chip CP2, a chip CP1 provided on the pad PS, a planarization layer PLN1 provided on a side of the chips CP1, CP2 away from the substrate, and a terminal extension layer RDL1 provided on a side of the planarization layer PLN1 away from the substrate. A plurality of extension traces RL1 are disposed in the terminal extension layer RDL 1. The height of the planarization layer PLN1 is greater than the height of each of the chips CP1, CP2, i.e., the height of the surface of the planarization layer PLN1 away from the substrate SUB2 is greater than the height of the surface of each of the chips CP1, CP2 away from the substrate SUB 2. The orthographic projection of chip CP1 on the substrate is within the orthographic projection of pad PS on the substrate, and the area of the orthographic projection of chip CP1 on the substrate is less than the area of the orthographic projection of pad PS on the substrate. Thus, the alignment accuracy between the chip CP1 and the pad PS does not need to be high, which is advantageous for placing the chip CP1 on the pad PS. A portion of extended trace RL1 may be electrically connected to terminal p1 of chip CP1 through a via that penetrates planarization layer PLN1, and another portion of extended trace RL1 may be electrically connected to terminal p1 of chip CP2 through a via that penetrates planarization layer PLN 1. In this way, terminals leading out of the chip CP1 and the chip CP2 can be realized, facilitating electrical connection between the respective terminals of the chips.

It should be noted that in the embodiment shown in fig. 8C, the height of the substrate PS may also be slightly larger than the height difference of the chip, for example, the difference between the height of the substrate PS and the height difference of the chip may be smaller than the process limit of the post-alignment exposure process in the vertical direction.

In an embodiment of the present disclosure, the chip may be formed on the substrate using a chip first process or a chip later process. For example, taking the semiconductor device as a display device as an example, the chip may be formed first, and then the driving unit of the display device may be formed, that is, a chip first process; alternatively, the driving unit of the display device may be formed first, and then the chip may be formed, i.e., a chip bonder process.

Referring to fig. 4 to 8C, in an embodiment of the present disclosure, the chip may include a chip body CPM and a plurality of terminals p1, p2 disposed on the chip body CPM. The chip body CPM may include a first surface CPM1, a second surface CPM2, a first side surface CPM3 and a second side surface CPM4, the second surface CPM2 and the first surface CPM1 are respectively located at opposite sides of the chip body, the first side surface CPM3 and the second side surface CPM4 are respectively located at side surfaces of the chip body, each of the first side surface CPM3 and the second side surface CPM4 connects the first surface CPM1 with the second surface CPM2, the first surface CPM1 faces or contacts the adhesive layer AD1, and at least one terminal 63p 92, p2 is disposed on a surface of the chip body other than the first surface CPM1 (e.g., CPM2, CPM3, CPM 4).

As shown in fig. 4 and 6A, the substrate may include a first substrate surface SUBP on which the die is disposed, the first substrate surface SUBP including a first substrate edge SUBP 1.

In an embodiment of the present disclosure, an orthographic projection of at least one extension trace RL on the substrate is inclined with respect to the first substrate edge SUBP 1.

For example, the orthographic projection of the second surface CPM2 on the substrate has a regular shape, as shown in fig. 6B, including, but not limited to, a rectangle, a rounded rectangle, a diamond, a square, a hexagon, an octagon, a circle, an ellipse, a rectangle, a triangle, and the like. As shown in fig. 4, the orthographic projection of the second surface CPM2 on the substrate comprises a first edge CPM 21. The first edge CPM21 is slanted with respect to the first substrate edge SUBP 1.

For example, a first included angle is formed between an extension line of an orthographic projection of the at least one extension trace RL on the substrate and an extension line of the first substrate edge SUBP1, and the first included angle is greater than 0 ° and smaller than 90 °.

For example, a second angle is formed between an extension of the first edge CPM21 and an extension of the first substrate edge SUBP1, and the second angle is greater than 0 ° and smaller than 90 °.

In a conventional semiconductor device and a manufacturing process thereof, the orientation of a chip with respect to a substrate cannot be deflected or can be deflected only by a small angle, for example, the angle of deflection needs to be less than 10 °. In this way, effective bonding of the respective terminals of the chip can be ensured. In embodiments of the present disclosure, the orientation of the chip relative to the substrate may be deflected by an angle that may be between 0 ° and 90 °, for example, may be between 0 ° and 50 °, may be between 1 ° and 60 °, may be greater than 10 ° and less than 90 °, may be about 10 °, about 20 °, about 30 °, about 40 °, about 15 °, about 25 °, about 35 °, about 45 °, about 50 °, about 60 °, about 70 °, about 80 °, and so on. That is, in embodiments of the present disclosure, the chip may be deflected by a large angle relative to the substrate, for example, may be greater than 10 °. In the embodiment of the disclosure, even under the condition that the chip deflects by a large angle relative to the substrate, the extended wiring layer can be formed through the subsequent post-alignment process, so that the effective bonding of the chip is realized, and the formation of bad points is avoided.

Fig. 9 is a schematic diagram illustrating a structure formed by a chip first process according to an embodiment of the present disclosure. FIG. 10 is a schematic diagram illustrating a structure formed by a chip later process according to an embodiment of the disclosure.

As shown in fig. 9, the display device may include a substrate SUB2, an adhesive layer AD1 provided on the substrate SUB2, a chip CP1 provided on the adhesive layer AD1, a terminal extension layer RDL1 provided on a side of the chip CP1 remote from the substrate, a planarization layer PLN1 provided on a side of the terminal extension layer RDL1 remote from the substrate, a redistribution layer RDL2 provided on a side of the planarization layer PLN1 remote from the substrate, a planarization layer PLN2 provided on a side of the redistribution layer RDL2 remote from the substrate, and a redistribution layer RDL3 and a driving unit DRU provided on a side of the planarization layer PLN2 remote from the substrate. The terminal extension layer RDL1 is provided with an extension wiring RL1, the redistribution layer RDL2 is provided with a first wiring RL2, and the redistribution layer RDL3 is provided with a second wiring RL 3. For example, at least a portion of the extension trace RL1 is disposed on a sidewall of the chip CP1 and directly electrically connected to the terminal p1 of the chip CP 1. The first routing RL2 can be electrically connected with the extended routing RL1 through a via penetrating through the planarization layer PLN1, and the second routing RL3 can be electrically connected with the first routing RL2 through a via penetrating through the planarization layer PLN 2. For example, the second trace RL3 and the driving unit DRU may be located at the same layer, and the second trace RL3 may be electrically connected with the driving unit DRU. In this way, it is possible to realize terminals of the lead-out chip CP1 and to realize electrical connection of the chip CP1 with the drive unit DRU. In this embodiment, the chip CP1 is closer to the substrate SUB2 than the driving unit DRU. In actual manufacturing, the chip CP1 may be formed on the substrate SUB2, and then a plurality of terminal extension layers are formed through a post alignment process, and then the driving unit DRU is formed. It should be understood that the precision of the processing technology of the microchip is usually higher than that of the driving unit such as the thin film transistor, and in this embodiment, after the chip is transferred to the substrate, the chip is bonded and integrated by using the post-alignment technology, which is beneficial to avoiding the barrier of the processing technology of the driving unit such as the thin film transistor, so as to realize high-resolution display.

Alternatively, as shown in fig. 10, the display device may include a substrate SUB2, a driving unit DRU provided on a substrate SUB2, a planarizing layer PLN1 provided on a side of the driving unit DRU away from the substrate, a terminal extension layer RDL1 provided on a side of the planarizing layer PLN1 away from the substrate, an adhesive layer AD1 provided on a side of the terminal extension layer RDL1 away from the substrate, a chip CP1 provided on the adhesive layer AD1, and a redistribution layer RDL2 provided on a side of the chip CP1 away from the substrate. An extension wiring RL1 is arranged in the terminal extension layer RDL1, and a first wiring RL2 is arranged in the redistribution layer RDL 2. For example, at least a portion of the first trace RL2 is disposed on a sidewall of the chip CP1 and directly electrically connected to the terminal p1 of the chip CP 1. The first trace RL2 can be electrically connected to the extension trace RL1 through a via penetrating through the adhesive layer AD1, and the extension trace RL1 can be electrically connected to the driving unit DRU through a via penetrating through the planarization layer PLN 1. In this way, the electrical connection of the chip CP1 with the driving unit DRU can be achieved. In this embodiment, the chip CP1 is farther from the substrate SUB2 than the driving unit DRU. In actual manufacturing, the driving unit DRU may be formed on the substrate SUB2 first, and then the terminal extension layer is formed through a post alignment process, and then the chip CP1 is formed. In the embodiment, the driving unit such as the thin film transistor is firstly transferred or prepared on the substrate, and then the chip is transferred to the substrate, so that the influence of the processing process of the driving unit such as the thin film transistor on the performance of the chip is avoided.

In the embodiments of the present disclosure, the driving unit DRU includes, but is not limited to, a Thin Film Transistor (TFT) driving circuit, a MOS driving circuit, a driving chip (IC), and the like. For example, the driving unit or the driving element may be used for providing an electrical signal to the LED chip to control the light emitting brightness thereof. For example, in some examples, the driving unit or the driving element may be a plurality of pixel driving circuits connected to each of the LED chips in a one-to-one correspondence manner, or a plurality of micro chips connected to each of the LED chips in a one-to-one correspondence manner, and may control each of the LED chips to emit different brightness gray scales. It should be noted that, a specific circuit structure of the driving unit or the driving element may be set according to actual needs, and the embodiment of the disclosure is not limited to this.

Hereinafter, some exemplary embodiments of the present disclosure will be further described by taking the semiconductor device as an example of a display device.

Fig. 11A and 11B are schematic diagrams of exemplary arrangements of chips and display units, respectively, included in a display device according to some embodiments of the present disclosure. For example, the chip CP1 may be a driving chip for driving a display unit, and the display unit DU may be an LED chip that can emit light.

Referring to fig. 11A, one pixel may include 3 LED chips, for example, corresponding to R, G, B sub-pixels. One chip CP1 may correspond to one pixel, i.e., one driving chip for driving one pixel. Alternatively, referring to fig. 11B, one chip CP1 may correspond to a plurality of pixels, i.e., one driving chip for driving a plurality of pixels. With such an arrangement, a plurality of pixels can be driven in an active matrix manner (AM manner) with the driving chip.

Referring to fig. 11A, a plurality of light emitting diodes are arranged in an array along a first direction X and a second direction Y. For example, the first direction X is a row direction and the second direction Y is a column direction. Of course, the embodiments of the present disclosure are not limited thereto, and the first direction and the second direction may be any directions as long as the first direction and the second direction intersect. Also, the plurality of LED chips are not limited to be arranged along a straight line, and may also be arranged along a curve, arranged along a ring, or arranged in any manner, which may be determined according to actual requirements, and the embodiment of the present disclosure is not limited thereto.

It should be noted that, in the embodiment of the present disclosure, the chip CP1 is not limited to a driving chip for driving the display unit, and may also include a control chip, a logic operation chip, a memory chip, and other functional chips.

Herein, for convenience of description, a chip for driving or controlling the LED is referred to as a chip CP1, and an LED chip for emitting light is referred to as a CP 3.

The method of manufacturing the display device according to the embodiment of the present disclosure may include at least two process routes according to the size of the chip CP 1.

Fig. 12A to 12F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed. In the case where the size of the chip CP1 is small, the method of manufacturing the display device according to the exemplary embodiment of the present disclosure may include at least the following steps. It should be noted that the case where the size of the chip CP1 is small may include: the size of the chip CP1 is substantially equal to or smaller than the size of the LED chip, or the ratio of the area of the orthographic projection of the chip CP1 on the substrate to the area of the orthographic projection of the LED chip on the substrate is 1.2 or less.

Referring to fig. 12A, an adhesive layer AD1 is coated or adhered on a substrate SUB 2. For example, the substrate SUB2 may be a glass substrate. The material of the adhesive layer AD1 may include a hot melt adhesive, a laser-curable adhesive, or an ultraviolet-curable adhesive, etc.

Referring to fig. 12B, the driving chip CP1 and/or the LED chip CP3 are transferred onto the substrate SUB2 through SMT or bulk transfer process and fixed on the substrate through the adhesive layer AD 1.

For example, the driving chip CP1 and the LED chip CP3 may both be located on the adhesive layer AD1, and the terminals p1 of the driving chip CP1 and the LED chip CP3 may be facing upward, i.e., located on a side of the chip away from the substrate.

For example, the driver chip CP1 may employ a Si-based cmos process, which is not limited in this disclosure.

Referring to fig. 12C, a passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.

For example, the passivation layer PVX1 may comprise a material such as silicon dioxide for insulation and to increase adhesion of the capping layer OC 1. The planarization layer PLN1 may include a resin material for filling up a step between the driver chip CP1 and the LED chip CP3, thereby achieving planarization. Alternatively, in other embodiments, the passivation layer PVX1 may not be prepared.

Alternatively, a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 remote from the substrate. For example, the passivation layer PVX2 may include a material such as silicon nitride, which is used to isolate moisture in the planarization layer PLN1 and prevent moisture in the planarization layer PLN1 from corroding the overlying terminal extension layer.

Referring to fig. 12D, a substrate (which may be referred to as a backplane) on which the chip is formed is photographed, and positions of terminals p1 of respective driver chips CP1 and LED chips CP3 provided on the backplane are determined using an image recognition technique, and a graphic file of openings of terminal areas (i.e., pad areas) is generated according to corresponding logic. Next, a photoresist is coated on the back plate and patterned by a digital direct writing or digital exposure machine according to the above-described pattern file, and then portions of the passivation layer PVX2, the planarization layer PLN1, and the passivation layer PVX2, which are not covered by the pattern of the photoresist, are etched to form a via hole VH3 exposing a portion of the terminal p1 of each of the driving chip CP1 and the LED chip CP 3. Alternatively, portions of the passivation layer PVX2, the planarization layer PLN1, and the passivation layer PVX2 above the terminals may be directly etched with EBL to form the via holes VH3 exposing a portion of the terminals p1 of the respective driving chip CP1 and LED chip CP 3.

Referring to fig. 12E, a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, a graphic file of the terminal extension layer RDL1 is automatically generated according to the connection relationship of the respective terminals and based on the previously determined positions of the terminals p1 of the respective driver chip CP1 and LED chip CP 3. The terminal extension layer RDL1 is patterned with digital exposure or EBL to form a plurality of extension traces RL 1. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

For example, terminal extender RDL1 may include a single film layer structure or a stacked layer structure of multiple film layers. In the case where the terminal extension layer RDL1 includes a single film layer structure, the terminal extension layer RDL1 may include a metal material such as copper (Cu). In the case where the terminal extension layer RDL1 includes a stacked structure of a plurality of film layers, the terminal extension layer RDL1 may include titanium/aluminum/titanium (Ti/Al/Ti), molybdenum aluminum molybdenum (Mo/Al/Mo), or the like.

Alternatively, referring to fig. 12F, after the post-alignment process described above is completed, a redistribution layer RDL2 may be prepared according to the requirements of the line interconnect.

For example, a capping layer PLN2 may be formed on the side of the terminal extension layer RDL1 remote from the substrate. Then, a rewiring layer RDL2 was formed on the side of the cover PLN2 remote from the substrate.

For example, the rewiring layer RDL2 may be prepared by a conventional photolithography process to form the first wirings RL2 for electrically connecting the respective chips in the rewiring layer RDL 2. Embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL2 may also be prepared by a post-alignment process.

For example, capping layer PLN2 may include silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide, and may also include a polymer material for isolating and insulating terminal extension layer RDL1 from redistribution layer RDL 2.

For example, according to the routing requirement, a third layer of wiring, a fourth layer of wiring, and the like can also be prepared, and the embodiments of the present disclosure are not particularly limited herein.

Referring to fig. 12F, a semiconductor device according to some embodiments of the present disclosure may be a display device, which may include: a substrate SUB 2; an adhesive layer AD1 provided on the substrate SUB 2; a plurality of chips CP1, CP3 disposed on a side of the adhesive layer AD1 remote from the substrate, each of which may include at least one terminal p 1; a passivation layer PVX1 disposed on a side of the plurality of chips CP1, CP3 remote from the substrate; a planarization layer PLN1 disposed on a side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on a substrate-remote side of the planarization layer PLN 1; a terminal extension layer RDL1 arranged on the side of the passivation layer PVX2 far away from the substrate; a covering layer PLN2 arranged on the side of the terminal extension layer RDL1 far away from the substrate; and a rewiring layer RDL2 disposed on the side of the cover layer PLN2 remote from the substrate. The plurality of extension tracks RL1 are located in the terminal extension layer RDL1, and the plurality of first tracks RL2 are located in the redistribution layer RDL 2.

For example, the plurality of chips CP1, CP3 may be located at the same layer, i.e., the substrate-facing surfaces of the chips CP1, CP3 may each be in contact with the adhesive layer AD 1. Some terminals p1 in the chips CP1, CP3 may be electrically connected by a plurality of extended traces RL 1. The other terminals p1 in the chips CP1 and CP3 may be electrically connected by a plurality of first traces RL 2.

Fig. 13A to 13G are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed. In the case where the size of the chip CP1 is large, the method of manufacturing the display device according to the exemplary embodiment of the present disclosure may include at least the following steps. It should be noted that the case where the size of the chip CP1 is large may include: the size of the chip CP1 is larger than the size of the LED chip, or the ratio of the area of the orthographic projection of the chip CP1 on the substrate to the area of the orthographic projection of the LED chip on the substrate is larger than 1.2.

Referring to fig. 13A, an adhesive layer AD1 is coated or adhered on a substrate SUB 2.

Referring to fig. 13B, the LED chip CP3 is transferred onto the substrate SUB2 by SMT or bulk transfer process and is fixed on the substrate by the adhesive layer AD 1.

For example, the terminal p1 of the LED chip CP3 may face upward, i.e., on the side of the chip away from the substrate.

Referring to fig. 13C, a passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.

Alternatively, a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 remote from the substrate.

Referring to fig. 13D, a substrate (which may be referred to as a backplane) on which the chips are formed is photographed, and positions of terminals p1 of respective LED chips CP3 disposed on the backplane are determined using an image recognition technique, and a pattern file of openings of terminal areas (i.e., pad areas) is generated according to corresponding logic. Next, a photoresist is coated on the back plate and patterned by a digital direct writing or digital exposure machine according to the above-described pattern file, and then portions of the passivation layer PVX2, the planarization layer PLN1, and the passivation layer PVX2, which are not covered by the pattern of the photoresist, are etched to form via holes VH3 exposing a portion of the terminals p1 of the respective LED chips CP 3. Alternatively, the portions of the passivation layer PVX2, the planarization layer PLN1, and the passivation layer PVX2 above the terminals may be directly etched with EBL to form the via holes VH3 exposing a portion of the terminals p1 of the respective LED chips CP 3.

Referring to fig. 13E, a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, the graphic file of the terminal extension layer RDL1 is automatically generated according to the connection relationship of the respective terminals and based on the previously determined positions of the terminals p1 of the respective LED chips CP 3. The terminal extension layer RDL1 is patterned with digital exposure or EBL to form a plurality of extension traces RL 1. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

Alternatively, referring to fig. 13F, after the post-alignment process described above is completed, a redistribution layer RDL2 may be prepared according to the requirements of the line interconnect.

For example, the rewiring layer RDL2 may be prepared by a conventional photolithography process to form the first wirings RL2 for electrically connecting the respective chips in the rewiring layer RDL 2. Embodiments of the present disclosure are not so limited and the redistribution layer RDL2 may be fabricated by a post-alignment process.

For example, according to the routing requirement, a third layer of wiring, a fourth layer of wiring, and the like may also be prepared, and embodiments of the present disclosure are not particularly limited herein.

Referring to fig. 13G, the driving chip CP1 is transferred onto the substrate SUB2 through SMT or bulk transfer process. For example, the terminal p1 of the driving chip CP1 may be electrically connected to the first trace RL2 in the redistribution layer RDL2 by eutectic bonding, solder paste bonding, conductive paste, or the like, so that the electrical connection between the driving chip CP1 and the LED chip CP3 is realized.

Referring to fig. 13G, a semiconductor device according to some embodiments of the present disclosure may be a display device, which may include: a substrate SUB 2; an adhesive layer AD1 provided on the substrate SUB 2; a plurality of LED chips CP3 disposed on a side of the adhesive layer AD1 remote from the substrate, each LED chip CP3 may include at least one terminal p 1; a passivation layer PVX1 disposed on a side of the plurality of LED chips CP3 remote from the substrate; a planarization layer PLN1 disposed on a side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on a substrate-remote side of the planarization layer PLN 1; a terminal extension layer RDL1 arranged on the side of the passivation layer PVX2 far away from the substrate; a covering layer PLN2 arranged on the substrate-away side of the terminal extension layer RDL 1; a rewiring layer RDL2 disposed on the side of the cover layer PLN2 remote from the substrate; and at least one chip CP1 disposed on a substrate-remote side of the redistribution layer RDL 2. The plurality of extension tracks RL1 are located in the terminal extension layer RDL1, and the plurality of first tracks RL2 are located in the redistribution layer RDL 2.

For example, chip CP1 and chip CP3 may be located at different layers. The plurality of LED chips CP3 may be located on the same layer, all in contact with the adhesive layer AD 1. The driving chip CP1 may be located at a side of the plurality of LED chips CP3 away from the substrate. The LED chip CP3 located at the lower layer is electrically connected to the driving chip CP1 located at the upper layer through the extension trace RL1 and the first trace RL 2.

Fig. 14 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure, where the display device can be a large-size display device or a tiled display device. Referring to fig. 13G and 14 in combination, a bonding region BND for electrically connecting a circuit board (e.g., a flexible circuit board FPC) may be provided between the 2 structures shown in fig. 13G. In the embodiment of the disclosure, the binding region BND does not need to be punched or LED, and the binding region BND is located on the back side of the light emitting region of the LED, thereby facilitating seamless tiled display. Furthermore, the edge of the display device does not need to be provided with the expanded routing area, so that the edge size of the formed display device is only related to the cutting process edge of the substrate. For example, in the case of using the laser cutting process, the width of the laser cutting edge breakage can be controlled within 20 micrometers, and the width of the heat affected zone can be smaller than 50 micrometers, so that a smaller frame can be realized, four sides of the display device can be equal in width, and the application to tiled display is facilitated.

Referring back to fig. 13G, a main light emitting surface of the LED may face the substrate SUB2, that is, the driving chip CP1 may be located at a rear surface of a light emitting side of the LED, so that the driving chip CP1 may not occupy an area of the light emitting region, that is, an orthographic projection of the driving chip CP1 on the substrate SUB2 may at least partially overlap with an orthographic projection of the LED chip CP3 on the substrate SUB 2. Therefore, a plurality of the driving chips CP1 can be disposed at a smaller pitch, thereby facilitating high-resolution display.

It should be noted that the embodiments of the present disclosure are not limited to the embodiment of emitting light downward. Fig. 15 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure, schematically illustrating an implementation of upward light emission. Referring to fig. 15, the LED chip CP3 may emit light upward, i.e., the driving chip CP1 may be located at a light emitting side of the LED. That is, the orthographic projection of the driver chip CP1 on the substrate SUB2 does not overlap with the orthographic projection of the LED chip CP3 on the substrate SUB 2.

Fig. 16 is a schematic cross-sectional view of a semiconductor device (e.g., a display device) according to some embodiments of the present disclosure. Referring to fig. 13G and 16 in combination, the display device may further include: an adhesive layer AD2 disposed on the substrate-remote side of the rewiring layer RDL 2; a driving chip CP1 disposed on a side of the adhesive layer AD2 remote from the substrate; a passivation layer PVX3 disposed on a side of the driving chip CP1 remote from the substrate; a planarization layer PLN3 disposed on a side of the passivation layer PVX3 away from the substrate; and a rewiring layer RDL3 disposed on the substrate-remote side of the planarization layer PLN 3. A plurality of second traces RL3 may be provided in the rewiring layer RDL 3. The plurality of terminals p1 of the driving chip CP1 may face upward, i.e., a side facing away from the substrate. The driving chip CP1 is disposed on the adhesive layer AD2, which facilitates the fixing of the driving chip CP 1.

For example, the process of preparing the redistribution layer RDL3 and the second trace RL3 may be similar to the process of preparing the terminal extension layer RDL1 and the extension trace RL1, that is, the redistribution layer RDL3 and the second trace RL3 are also prepared by using a post-alignment process.

The driving chip CP1 can be electrically connected to the first trace RL2 through the second trace RL3, the first trace RL2 is electrically connected to the extended trace RL1, and the extended trace RL1 is electrically connected to the terminal p1 of the LED chip CP 3. In this way, electrical connection between the driving chip CP1 and the LED chip CP3 can be achieved.

In the following, some exemplary embodiments of the present disclosure are described in detail further taking a display device as an example.

Referring to fig. 17A and 17B, an adhesive layer AD1 is coated or adhered on a substrate SUB 2. The substrate SUB2 may be, for example, a glass substrate, a polyimide (i.e., PI) substrate, or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in a subsequent process to remove the substrate SUB 2.

For example, in embodiments of the present disclosure, the material of the substrate may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like. The terminal may have a columnar structure. The material of the terminal may include a conductive material, such as a metal material, and in particular, may be at least one selected from gold, silver, copper, aluminum, molybdenum, gold alloy, silver alloy, copper alloy, aluminum alloy, molybdenum alloy, and the like, or a combination of at least two selected from the same, which is not limited in this embodiment of the present disclosure.

Then, the LED chip CP3 and/or the functional element CP4 are transferred onto the substrate SUB2 by SMT or bulk transfer process, and fixed onto the substrate by the adhesive layer AD 1.

For example, the LED chip CP3 and the functional element CP4 may both be located on the adhesive layer AD1, and the terminals p1 of the LED chip CP3 and the functional element CP4 may be facing upward, i.e., located on the side of the chip away from the substrate. For example, the functional element CP4 may be a microchip as described above for implementing specific functions, including but not limited to, a control chip, a memory chip, a logic operation chip, a sensing chip, etc.

Referring to fig. 17B and 17C, a substrate (which may be referred to as a backplane) provided with the LED chip CP3 and the functional element CP4 is photographed, and coordinates and areas of terminals p1 of the respective LED chips CP3 and functional elements CP4 provided on the backplane are determined using an image recognition technique, and a graphic file of a terminal area (i.e., pad area) is generated. And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension wirings RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wirings RL1 may be electrically connected to the terminals p1 of the respective LED chips CP3 and functional elements CP4, respectively, to lead out the respective terminals p 1. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

Referring to fig. 17D, a planarization layer PLN1 is applied to the side of the terminal extension layer RDL1 away from the substrate.

For example, the planarization layer PLN1 may include a resin-based material for filling up a level difference between each of the LED chips CP3 and the functional element CP4 to achieve planarization.

With continued reference to fig. 17D, vias can be formed through the planarization layer PLN1 and the passivation layer PVX2 to expose at least a portion of the respective extension traces RL 1. Then, a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, etching, and the like. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL 2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the vias, respectively, to further lead out each terminal p 1.

Referring to fig. 17E, an adhesive layer AD2 is formed on the side of the redistribution layer RDL2 away from the substrate. Next, the side of the adhesive layer AD2 remote from the substrate forms the drive elements DRU. The driving element DRU may be fixed to the substrate by an adhesive layer AD 2.

For example, the driving element DRU may include a driving chip CP1, and the driving chip CP1 may be transferred onto the substrate SUB2 through SMT or bulk transfer process and fixed on the substrate through an adhesive layer AD 2. For another example, the driving element DRU may include an electronic element such as a thin film transistor, that is, a plurality of thin film transistors may be formed on the substrate SUB2 through a process of manufacturing a TFT.

Next, a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate. For example, the planarization layer PLN2 may include a resin-like material for filling up the level difference between the respective driving elements DRU to achieve planarization.

Then, vias may be formed through the planarization layer PLN2 and the adhesive layer AD2 to expose at least a portion of each first trace RL 2. A metal layer is deposited on the side of planarization layer PLN2 remote from the substrate, and a redistribution layer RDL3 is formed by a patterning process including the steps of applying photoresist, exposing, developing, etching, and the like. For example, a plurality of second traces RL3 are formed in the redistribution layer RDL 3. The plurality of second routing lines RL3 may be electrically connected with the plurality of first routing lines RL2 through the above-mentioned via holes, respectively, to further lead out the respective terminals p1, and electrically connect the driving element DRU with the respective LED chips CP3 and the respective functional elements CP 4.

Referring to fig. 17F, a planarization layer PLN3 is formed on the side of the redistribution layer RDL3 away from the substrate. The substrate SUB4 is then attached by an adhesive layer AD3 to the surface of the planarization layer PLN3 remote from the substrate SUB 2.

Referring to fig. 17G, substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation, or UV dissociation, for example.

Referring to fig. 17H, a protective layer PTL is applied to the side of each LED chip CP3 and each functional element CP4 away from the substrate SUB 4.

Referring to fig. 17I, a patterning process is performed on the protective layer PTL to expose the respective LED chips CP3 and the respective functional elements CP4 near the surface of the protective layer PTL. In this way, the protective layer PTL may protect, for example, the metal layer of the extension trace RL1 so that the metal layer may not be exposed to the air, and at the same time, so that the main light emitting surfaces of the respective LED chips CP3 and the functional surfaces of the respective functional elements CP4 may be exposed, facilitating light emission and realizing respective functions.

It should be noted that, in the embodiment of the present disclosure, the step of performing the patterning process on the protective layer PTL is optional. For example, in some embodiments, at least a portion of the chip or the functional element may not be exposed on the surface facing the protection layer PTL, and at this time, a patterning process does not need to be performed on the portion of the protection layer PTL corresponding to the chip or the functional element.

For example, the protective layer PTL may include an insulating layer, i.e., function as an insulator.

In the above embodiments, the terminals p1 of each chip are located on one surface of the chip, for example, the LED chip CP3 includes at least two terminals p1, and the at least two terminals p1 are both located on the surface of the LED chip CP3 away from the light exit surface, i.e., on the back surface of the light exit side. However, embodiments of the present disclosure are not limited to such terminal arrangements.

Fig. 18 schematically illustrates a schematic cross-sectional view of a semiconductor device, in which terminals of a chip are located on two opposing sides of the chip, according to some embodiments of the present disclosure. Referring to fig. 18, the chip CP includes at least two terminals p1, and at least two terminals p1 are respectively located on two opposite sides of the chip CP. The chip CP includes a surface (i.e., a lower surface in fig. 18) facing the substrate SUB2, and two opposite side surfaces of the chip CP are located on both sides of the lower surface, respectively. For example, the chip CP shown in fig. 18 may be the LED chip CP3 and/or the functional element CP4 described above.

In the embodiment shown in fig. 18, the extension traces RL1 located in the terminal extension layer RDL1 may also be electrically connected with at least two terminals p1, respectively, so as to lead out the terminals p1 of the chip.

Referring to fig. 19A, an adhesive layer AD1 is coated or adhered on a substrate SUB 2. The substrate SUB2 may be, for example, a glass substrate, a polyimide (i.e., PI) substrate, or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in a subsequent process to remove the substrate SUB 2.

Next, a conductive layer CDL1 was formed on the side of adhesive layer AD1 away from the substrate. For example, the conductive layer CDL1 can include a conductive material such as a metal, a conductive oxide, or the like.

Adhesive layer AD2 is formed on the side of conductive layer CDL1 away from the substrate. For example, adhesive layer AD2 may be tacky and may be evaporated by heating to reflux. For example, the adhesive layer AD2 may contain solder resist.

Then, the chip CP (e.g., the LED chip CP3 and/or the functional element CP4) is transferred onto the substrate SUB2 by SMT or bulk transfer process. As shown in fig. 19A, the chip CP has terminals on both a surface close to the substrate SUB2 (i.e., a lower surface in the drawing) and a surface far from the substrate SUB2 (i.e., an upper surface in the drawing). Here, for convenience of description, the terminal located on the lower surface is referred to as a terminal p11, and the terminal located on the upper surface is referred to as a terminal p 12.

Referring to fig. 19B, the adhesive layer AD2 is evaporated by means of heat reflow so that the terminal p11 can be electrically connected to the conductive layer ADL 1. In this way, chip CP is in good electrical communication with underlying conductive layer ADL 1.

Referring to fig. 19C, a passivation layer PVX1 is formed on a side of the chip CP remote from the substrate, and a planarization layer PLN1 is formed on a side of the passivation layer PVX1 remote from the substrate.

Referring to fig. 19C and 19D, the substrate (which may be referred to as a backplane) provided with the chips CP is photographed, and coordinates and areas of terminals p12 of the respective chips CP provided on the backplane are determined using an image recognition technique, and a graphic file of terminal areas (i.e., pad areas) is generated. And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 may be electrically connected to the terminals p12 of the respective chips CP through vias, respectively, so as to lead out the respective terminals p 12. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

Referring to fig. 19E, an adhesive layer AD3 is formed on the side of the terminal extension layer RDL1 away from the substrate. Next, the driving elements DRU are formed on the side of the adhesive layer AD3 remote from the substrate. The driving element DRU may be fixed to the substrate by an adhesive layer AD 3.

Next, a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate.

Then, vias may be formed through the planarization layer PLN2 and/or the adhesive layer AD3 to expose at least a portion of the terminals of the respective extension traces RL1 and the drive element DRU. A metal layer is deposited on the side of planarization layer PLN2 remote from the substrate, and a redistribution layer RDL2 is formed by a patterning process including the steps of applying photoresist, exposing, developing, etching, and the like. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL 2. The plurality of first traces RL2 can be electrically connected with the plurality of extended traces RL1 through the above vias, respectively, to further lead out the respective terminals p12 and electrically connect the driving element DRU with the respective chips CP.

Referring to fig. 19F, a planarization layer PLN3 is formed on the side of the redistribution layer RDL2 away from the substrate. The substrate SUB4 is then attached by an adhesive layer AD4 to the surface of the planarization layer PLN3 remote from the substrate SUB 2.

Referring to fig. 19G, substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation, or UV dissociation, for example.

Referring to fig. 19H, a protective layer PTL is applied to the side of conductive layer CDL1 away from substrate SUB 4. Then, a patterning process is performed on protective layer PTL to expose a portion of conductive layer CDL1 (e.g., corresponding to a portion of each chip CP) near the surface of protective layer PTL. In this way, terminal p11 of chip CP can be led out through a portion of conductive layer CDL1 exposed.

Hereinafter, some exemplary embodiments of the present disclosure will be described in detail further taking as an example the semiconductor device as a display device and a driving element of the display device including a TFT driving circuit.

Fig. 20A to 20F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device including a TFT driving circuit according to an exemplary embodiment of the present disclosure are performed, and the manufacturing method is implemented by the above-described chip first process.

Referring to fig. 20A, an adhesive layer AD1 is coated or adhered on a substrate SUB 2. The substrate SUB2 may be, for example, a glass substrate, a polyimide (i.e., PI) substrate, or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in a subsequent process to remove the substrate SUB 2.

Referring to fig. 20B, a plurality of chips CP are transferred onto a substrate SUB2 through SMT or bulk transfer process and fixed thereon through an adhesive layer AD 1. For example, the plurality of chips CP may include, but are not limited to, an LED chip, a driving chip, a memory chip, a control chip, a digital-to-analog conversion chip, an information processing chip, a sensor chip, and the like. For example, the LED chip may be an LED chip with a sapphire substrate removed, the driving chip, the memory chip, the control chip, the digital-to-analog conversion chip, the information processing chip, and the sensor chip may be Si-based chips, the Si-based chips may be bare chips without package structures, and the height of the chips may be less than 100 micrometers.

In the embodiment of fig. 20B, 4 chips are schematically illustrated, and for convenience of description, the 4 chips are respectively referred to as chips CP1, CP2, CP3 and CP4, for example, the chip CP1 may be a control chip, the chip CP2 may be a memory chip, the chip CP3 may be an LED chip, and the chip CP4 may be a sensor chip. It should be understood that embodiments of the present disclosure are not limited to the arrangement shown in fig. 20B.

For example, the chips CP1, CP2, CP3, CP4 may all be located on the adhesive layer AD1, and the terminal p1 of each of the chips CP1, CP2, CP3, CP4 may be facing upward, i.e., located on the side of the chip away from the substrate.

Referring to fig. 20C, a substrate (which may be referred to as a backplane) provided with the chips CP1, CP2, CP3, and CP4 is photographed, and coordinates and areas of terminals p1 of the respective chips CP1, CP2, CP3, and CP4 provided on the backplane are determined using an image recognition technique, and a graphic file of terminal areas (i.e., pad areas) is generated. And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 may be electrically connected to the terminals p1 of the respective chips CP1, CP2, CP3 and CP4, respectively, so as to lead out the respective terminals p 1. That is, through the post-alignment process, the extension trace RL1 for electrically connecting the respective chips is formed in the terminal extension layer RDL 1.

With continued reference to fig. 20C, a planarization layer PLN1 is applied to the side of terminal extension layer RDL1 remote from the substrate.

Alternatively, the passivation layer PVX1 may be formed on the side of the planarization layer PLN1 close to the substrate and the passivation layer PVX2 may be formed on the side of the planarization layer PLN1 remote from the substrate. For example, the passivation layers PVX1 and PVX2 may include silicon nitride, silicon oxide, or the like, for isolating moisture in the planarization layer PLN1 and preventing moisture in the planarization layer PLN1 from corroding the terminal extension layer.

With continued reference to fig. 20C, a via VH1 may be formed through the passivation layer PVX1, the planarization layer PLN1, and the passivation layer PVX2 to expose at least a portion of each extension trace RL 1.

In some embodiments of the present disclosure, the planarization layer PLN1 may include a resin material, such as polyimide (i.e., PI), for filling up the level difference between the respective chips CP1, CP2, CP3, and CP4, so as to achieve planarization.

In some embodiments of the present disclosure, planarization layer PLN1 may comprise a low temperature curable planarization material, for example, an acrylic-based material. The cost of the planarization material which can be cured at low temperature is lower than that of the polyimide material, thereby being beneficial to reducing the cost of the product.

It should be noted that, after the chip transfer is completed, a planarization material capable of being cured at a low temperature is used, and then, a low-temperature oxide TFT process or other semiconductor devices capable of being manufactured at a low temperature can be used to complete the manufacture of the whole TFT device. For example, the curing temperature of the low temperature curable planarization material may be less than 250 ℃, and accordingly, the TFT device may be fabricated below 250 ℃ in the TFT process, so that the risk of damaging the performance of the microchip due to the high temperature in the TFT process may be reduced.

For example, the thickness of the planarization layer PLN1 is 10 μm or more higher than the maximum height of each of the chips CP1, CP2, CP3, and CP 4.

Referring to fig. 20D, a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including the steps of coating photoresist, exposing, developing, etching, and the like. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL 2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the vias, respectively, to further lead out each terminal p 1.

Fig. 26A and 26B respectively schematically illustrate schematic cross-sectional views of vias of a display device according to an embodiment of the present disclosure.

In the process of forming the redistribution layer RDL2, a part of a metal layer needs to be deposited in the via VH1, so that the plurality of first traces RL2 in the redistribution layer RDL2 can be electrically connected with the plurality of extension traces RL1 in the terminal extension layer RDL1 through the via VH1, respectively. In this case, the insulating layer between the terminal extension layer RDL1 and the rewiring layer RDL2 may be formed using a conventional organic material. Referring to fig. 26A, via VH1 is shaped in cross-section as an inverted trapezoid to facilitate deposition of a portion of a metal layer in via VH 1.

Optionally, in some embodiments of the present disclosure, the terminal expansion layer RDL1 may be used as a seed layer, and the metal layer (for example, a copper layer) may be plated by using an electrochemical method or an electroless plating method, so that a metal layer having a thickness equal to that of the combination of the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2 may be grown in the via hole VH1 to fill and level up the via hole VH1, so that the plurality of first traces RL2 located in the redistribution layer RDL2 may be electrically connected to the plurality of expansion traces RL1 located in the terminal expansion layer RDL1 through the via hole VH1, respectively.

In this case, an insulating layer between the terminal extension layer RDL1 and the rewiring layer RDL2 may be formed using a high-temperature resistant organic material. On this basis, a more vertical via can be formed by using a hard mask layer-exposure development-dry etching-hard mask layer removal mode. Referring to fig. 26B, the via VH1 may be rectangular in shape in cross-section. That is, the area of the opening of the via VH1 on the side close to the terminal extension layer RDL1 is substantially equal to the area of the opening of the via VH1 on the side close to the rewiring layer RDL 2. Therefore, in this embodiment, the requirement on the profile of the via is low, and the via with the opening size of less than 10 microns can be formed, which is beneficial to improving the PPI of the display device.

It should be noted that, according to the circuit logic design requirement, the number of layers of routing layers may also be increased, for example, a redistribution layer RDL3, an RDL4, and the like may also be formed on a side of the redistribution layer RDL2 away from the substrate, and insulating layers may be used for isolation and insulation between two adjacent routing layers.

In this way, a backplane including the respective chips CP1, CP2, CP3, CP4 and a terminal extension layer is formed, and then, a driving element including a TFT driving circuit may be formed on the backplane. That is, in this embodiment, the display device is formed using a chip first process.

Fig. 21 is a partially enlarged view of a portion I of fig. 20E. For example, referring to fig. 20E and 21, a barrier layer BRL and a buffer layer BFL may be sequentially formed on the side of the redistribution layer RDL2 away from the substrate. Then, a film structure of the TFT may be formed on a side of the buffer layer BFL away from the substrate. For example, an active layer, a gate insulating layer GI1, a conductive layer CDL1, a gate insulating layer GI2, a conductive layer CDL2, an interlayer dielectric layer IDL, and a conductive layer CDL3 may be sequentially formed on the side of the buffer layer BFL away from the substrate. For example, a TFT driver circuit may include at least one thin film transistor and at least one storage capacitor, a gate electrode of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in conductive layer CDL1, another electrode of the storage capacitor may be located in conductive layer CDL2, and a source and a drain of the thin film transistor may be located in conductive layer CDL 3. For example, a plurality of second traces RL3 can be located in conductive layer CDL 3. The second trace RL3 can be electrically connected to the first trace RL2 through a via penetrating through the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric IDL. The source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through vias that penetrate the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL.

For example, planarization layer PLN2 can be formed on the side of conductive layer CDL3 away from the substrate.

It should be understood that in this embodiment, the driving element including the TFT driving circuit may be formed by using a known TFT manufacturing process, which is not described herein.

It should be noted that, in the embodiment of the present disclosure, the thin film transistor included in the TFT driving circuit may include, but is not limited to, a polysilicon TFT, a low temperature polysilicon TFT, an oxide TFT, and the like.

For example, as described above in connection with fig. 17F-17I, substrate SUB4 may be attached by adhesive layer AD3 on the surface of planarization layer PLN3 away from substrate SUB 2. The substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation or UV dissociation, etc. A protective layer PTL is applied to the side of the respective chip CP1, CP2, CP3, CP4 remote from the substrate SUB 4. A patterning process is performed on the protective layer PTL to expose the surfaces of the respective chips CP1, CP2, CP3, CP4 near the protective layer PTL. In this way, the protective layer PTL may protect, for example, the metal layer of the extension trace RL1, so that the metal layer may not be exposed to the air, and at the same time, the functional surfaces of the respective chips CP1, CP2, CP3, and CP4 may be exposed, which is advantageous for realizing the functions of the respective chips.

Fig. 20F is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure. Referring to fig. 20F, 20E, and 21, the semiconductor device according to some embodiments of the present disclosure may be a display device, for example, the display device may be a μ LED display device. It may include: a substrate SUB 4; an adhesive layer AD3 provided on the substrate SUB 4; a planarization layer PLN2 disposed on the side of the adhesive layer AD3 remote from the substrate; a conductive layer CDL3 disposed on a substrate-remote side of the planarization layer PLN 2; an interlayer dielectric layer IDL disposed on a side of conductive layer CDL3 remote from the substrate; a conductive layer CDL2 disposed on a side of the interlayer dielectric IDL remote from the substrate; a gate insulating layer GI2 provided on a side of the conductive layer CDL2 away from the substrate; a conductive layer CDL1 provided on a side of the gate insulating layer GI2 away from the substrate; an active layer ACT disposed on a side of conductive layer CDL1 remote from the substrate; the buffer layer BFL is arranged on one side of the active layer ACT, which is far away from the substrate; the barrier layer BRL is arranged on one side of the buffer layer BFL, which is far away from the substrate; a rewiring layer RDL2 arranged on the side, far away from the substrate, of the blocking layer BRL; a passivation layer PVX2 arranged on the side, away from the substrate, of the redistribution layer RDL 2; a planarization layer PLN1 disposed on a side of the passivation layer PVX2 away from the substrate; a passivation layer PVX1 disposed on a substrate-remote side of the planarization layer PLN 1; a terminal extension layer RDL1 arranged on the side of the passivation layer PVX1 far away from the substrate; a plurality of chips CP1, CP2, CP3, CP4 disposed on a substrate-remote side of the terminal extension layer RDL 1; and a protective layer PTL disposed on a side of the chips CP1, CP2, CP3, CP4 remote from the substrate.

For example, a TFT driver circuit may include at least one thin film transistor and at least one storage capacitor, a gate electrode of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in conductive layer CDL1, another electrode of the storage capacitor may be located in conductive layer CDL2, and a source and a drain of the thin film transistor may be located in conductive layer CDL 3.

For example, a plurality of extension traces RL1 may be located in the terminal extension layer RDL 1. The plurality of first traces RL2 may be located in the redistribution layer RDL 2. A plurality of second tracks RL3 can be located in conductive layer CDL 3. Each of the chips CP1, CP2, CP3, CP4 may include at least one terminal p 1. The terminals p1 of the respective chips CP1, CP2, CP3, CP4 are led out through the extension wirings RL 1. The plurality of first routing lines RL2 may be electrically connected with the plurality of extension routing lines RL1 through vias penetrating the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2, respectively. The plurality of second routing lines RL3 can be electrically connected to the first routing lines RL2 through vias penetrating through the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric layer IDL, respectively. The source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through vias that penetrate the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL. Thus, it is possible to realize electrical connection between the TFT driving circuit and the chip, and electrical connection between a plurality of chips.

Fig. 22 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the LED chip and the other chips are located in different layers. Fig. 23 is a partially enlarged view of a portion II in fig. 22. Referring to fig. 22 and 23 in combination, the LED chip and the other chips may be disposed on different sides of the TFT in consideration of differences in process and performance (e.g., temperature resistance) between the LED chip and the display-related and sensing-related Si-based chip. For example, the LED chip may be provided on a side of the thin film transistor close to the substrate SUB2, and the other chips may be provided on a side of the thin film transistor remote from the substrate SUB 2. In this embodiment, the chips CP1, CP2, and CP4 located on the upper layer may be electrically connected to the LED chip CP3 located on the lower layer through the plurality of second traces RL3 located in the redistribution layer RDL 3.

Specifically, the display device may be a μ LED (i.e., miniLED) display device, which may include: a substrate SUB 2; an adhesive layer AD1 provided on the substrate SUB 2; an LED chip CP3 disposed on a side of the adhesive layer AD1 remote from the substrate; a terminal extension layer RDL1 disposed on a side of the LED chip CP3 remote from the substrate; a passivation layer PVX1 disposed on a substrate-remote side of the terminal extension layer RDL 1; a planarization layer PLN1 disposed on a side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on a substrate-remote side of the planarization layer PLN 1; a rewiring layer RDL2 arranged on one side of the passivation layer PVX2 far away from the substrate; the barrier layer BRL and/or the buffer layer BFL are/is arranged on the side, far away from the substrate, of the redistribution layer RDL 2; the active layer ACT is arranged on one side, far away from the substrate, of the buffer layer BFL; a gate insulating layer GI1 provided on the substrate-remote side of the active layer ACT; a conductive layer CDL1 provided on a side of the gate insulating layer GI1 away from the substrate; a gate insulating layer GI2 provided on a side of the conductive layer CDL1 away from the substrate; a conductive layer CDL2 provided on a side of the gate insulating layer GI2 away from the substrate; an interlayer dielectric layer IDL disposed on a side of conductive layer CDL2 remote from the substrate; a conductive layer CDL3 disposed on a side of the interlayer dielectric IDL remote from the substrate; a planarization layer PLN2 disposed on a substrate-remote side of conductive layer CDL 3; an adhesive layer AD2 disposed on a side of the planarization layer PLN2 remote from the substrate; a plurality of chips CP1, CP2 and CP4 arranged on the side of the adhesive layer AD2 far away from the substrate; a rewiring layer RDL3 provided on a substrate-remote side of the plurality of chips CP1, CP2, CP 4; a passivation layer PVX3 arranged on the side of the redistribution layer RDL3 away from the substrate; a planarization layer PLN3 disposed on a side of the passivation layer PVX3 remote from the substrate.

For example, a plurality of extension traces RL1 may be located in the terminal extension layer RDL 1. The plurality of first traces RL2 may be located in the redistribution layer RDL 2. A plurality of second tracks RL3 can be located in conductive layer CDL 3. A plurality of third traces RL4 may be located in the redistribution layer RDL 3. Each of the chips CP1, CP2, CP3, CP4 may include at least one terminal p 1. The terminal p1 of each chip CP1, CP2, CP4 can be led out through the second trace RL 3. The terminals p1 of the chips CP1, CP2, CP4 may be electrically connected through the second trace RL 3. The at least one third routing RL4 may be electrically connected with at least one of the second routing RL3, the source electrode and the drain electrode of the thin film transistor through a via hole penetrating through the adhesive layer AD2 and the planarization layer PLN 2. The plurality of first routing lines RL2 may be electrically connected with the plurality of extension routing lines RL1 through vias penetrating the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2, respectively. The plurality of second routing lines RL3 can be electrically connected to the first routing lines RL2 through vias penetrating through the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric layer IDL, respectively. The source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through vias that penetrate the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL. Thus, it is possible to realize electrical connection between the TFT driving circuit and the chip, and electrical connection between a plurality of chips.

In this embodiment, the chips CP1, CP2, CP4 are located on the opposite side of the thin film transistor from the LED chip CP 3. The plurality of terminal extension layers formed by the post-alignment process can still realize the electric connection between the TFT driving circuit and the chip and the electric connection between a plurality of chips.

Fig. 24 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the LED chip and the other chips are located in different layers. Referring to fig. 24, a plurality of terminal extension layers may be provided to achieve electrical connection between the plurality of chips CP1, CP2, CP4 located at an upper layer. For example, a terminal extension layer RDL4 and a passivation layer PVX4 may be disposed between the passivation layer PVX3 and the planarization layer PLN 3. A passivation layer PVX4 is disposed on the side of the planarization layer PLN3 remote from the substrate SUB4, and a terminal extension layer RDL4 is disposed between the passivation layer PVX4 and the passivation layer PVX 3. A plurality of extension traces RL5 may be located in the terminal extension layer RDL 4.

For example, the chips CP1, CP2, CP4 may include at least 3 terminals p 1. The third trace RL4 located in the redistribution layer RDL3 may lead out the terminal p1 located on both sides. An extension trace RL5 located in the terminal extension layer RDL4 may electrically connect the intermediately located terminal p1 of one chip with the intermediately located terminal p1 of another chip.

By providing a plurality of terminal extension layers, it is advantageous to achieve electrical connection between the plurality of chips CP1, CP2, CP4 located on the upper layer. It should be understood that more terminal extension layers may be provided to achieve electrical connection between the plurality of chips CP1, CP2, CP4 located at the upper layer according to the need of actual wiring.

Referring to fig. 25A, a TFT driver circuit may be formed on a substrate SUB 2. For example, in the embodiments of the present disclosure, the thin film transistor in the TFT driving circuit may include, but is not limited to, a polysilicon TFT, a low temperature polysilicon TFT, an oxide TFT, and the like. Taking a polysilicon TFT process as an example, a blocking layer BRL and a buffer layer BFL may be sequentially formed on the substrate SUB 4. Then, a film structure of the TFT may be formed on a side of the buffer layer BFL away from the substrate. For example, an active layer ACT, a gate insulating layer GI1, a conductive layer CDL1, a gate insulating layer GI2, a conductive layer CDL2, an interlayer dielectric layer IDL, and a conductive layer CDL3 may be sequentially formed on the side of the buffer layer BFL away from the substrate. For example, a TFT driver circuit may include at least one thin film transistor and at least one storage capacitor, a gate electrode of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in conductive layer CDL1, another electrode of the storage capacitor may be located in conductive layer CDL2, and a source and a drain of the thin film transistor may be located in conductive layer CDL 3. For example, a plurality of second traces RL3 can be located in conductive layer CDL 3. The source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through vias that penetrate the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL.

For example, conductive layer CDL4 can be formed by forming planarization layer PLN1 on the side of conductive layer CDL3 away from the substrate and forming conductive layer CDL1 on the side of planarization layer PLN1 away from the substrate. For example, a plurality of third traces RL4 can be located in conductive layer CDL 4. The plurality of third routing lines RL4 may be electrically connected with the plurality of second routing lines RL3 and the source and drain electrodes of the thin film transistors through vias penetrating through the planarization layer PLN1, respectively.

Thus, in this embodiment, the TFT driver circuit is formed over the substrate SUB4, and then each chip and at least one terminal extension layer are formed over the backplane on which the TFT driver circuit is formed, that is, the display device is formed using a chip later process.

Referring to fig. 25B and 25C, adhesive layer AD2 is formed on the side of conductive layer CDL4 away from the substrate. Then, the plurality of chips CP are transferred onto the substrate SUB4 by SMT or bulk transfer process, and fixed on the substrate SUB4 by the adhesive layer AD 2. Each chip CP may comprise at least two terminals p1, in the illustrated embodiment the terminals p1 of each chip CP are facing upwards, i.e. towards the side of the chip remote from the substrate SUB 4.

For example, the plurality of chips CP may include, but are not limited to, an LED chip, a driving chip, a memory chip, a control chip, a digital-to-analog conversion chip, an information processing chip, a sensor chip, and the like. For example, the LED chip may be an LED chip with a sapphire substrate removed, and the driving chip, the memory chip, the control chip, the digital-to-analog conversion chip, the information processing chip, and the sensor chip may be Si-based chips, and the Si-based chips may be bare chips without a package structure. In the embodiment of fig. 25C, 4 chips are schematically shown, and for convenience of description, the 4 chips are respectively referred to as chips CP1, CP2, CP3 and CP4, for example, the chip CP1 may be a control chip, the chip CP2 may be a memory chip, the chip CP3 may be an LED chip, and the chip CP4 may be a sensor chip. It should be understood that embodiments of the present disclosure are not limited to the arrangement shown in fig. 25C.

The substrate SUB4 may be, for example, a glass substrate, a polyimide (i.e., PI) substrate, or a quartz substrate.

For example, the adhesive layer AD2 may include, but is not limited to, a thermal sensitive adhesive, a laser curable adhesive, a photoresist, a UV curable adhesive, and the like.

Referring to fig. 25D, a plurality of vias VH2 may be formed in the adhesive layer AD2 by using a patterning process to expose at least a portion of the third trace RL4 located in the conductive layer CDL 4. For example, the patterning process herein may employ a known photolithography process including steps of photoresist coating, exposure, development, and etching, and a mask plate may be used during the exposure.

Referring to fig. 25E, a substrate (which may be referred to as a backplane) provided with the chips CP1, CP2, CP3, and CP4 is photographed, and coordinates and areas of terminals p1 of the respective chips CP1, CP2, CP3, and CP4 provided on the backplane are determined using an image recognition technique, and a graphic file of terminal areas (i.e., pad areas) is generated. And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 may be electrically connected to the terminals p1 of the respective chips CP1, CP2, CP3, and CP4, respectively, so as to lead out the respective terminals p 1. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

For example, the at least one extension trace RL1 can be electrically connected with a TFT driving circuit, for example, a source or a drain of a thin film transistor, through the third trace RL4 located in the conductive layer CDL 4. At least one extension trace RL1 may also electrically connect at least two of chips CP1, CP2, CP3, CP 4. In this way, electrical connection between the TFT driving circuit and the chip, and electrical connection between a plurality of chips can be achieved.

Referring to fig. 25F, a passivation layer PVX1 and a planarization layer PLN2 may be sequentially formed on a side of the terminal extension layer RDL1 away from the substrate.

It should be noted that, according to the circuit logic design requirement, the number of layers of routing layers may also be increased, for example, a rewiring layer RDL2, RDL3, etc. may also be formed on the side of the terminal extension layer RDL1 away from the substrate, and insulating layers may be used for isolation and insulation between two adjacent routing layers.

Referring to fig. 25F, the semiconductor device according to some embodiments of the present disclosure may be a display device, for example, the display device may be a μ LED display device. It may include: a substrate SUB 4; a barrier layer BRL provided on the substrate SUB 4; the buffer layer BFL is arranged on one side, far away from the substrate, of the barrier layer BRL; the active layer ACT is arranged on one side, far away from the substrate, of the buffer layer BFL; a gate insulating layer GI1 provided on the substrate-remote side of the active layer ACT; a conductive layer CDL1 provided on a side of the gate insulating layer GI1 away from the substrate; a gate insulating layer GI2 provided on a side of the conductive layer CDL1 away from the substrate; a conductive layer CDL2 provided on a side of the gate insulating layer GI2 away from the substrate; an interlayer dielectric layer IDL disposed on a side of conductive layer CDL2 remote from the substrate; a conductive layer CDL3 disposed on a side of the interlayer dielectric IDL remote from the substrate; a planarization layer PLN1 disposed on a substrate-remote side of conductive layer CDL 3; a conductive layer CDL4 disposed on a side of the planarization layer PLN1 remote from the substrate; an adhesive layer AD2 disposed on a substrate-remote side of conductive layer CDL 4; a plurality of chips provided on a side of the adhesive layer AD2 remote from the substrate; a terminal extension layer RDL1 disposed on a side of the plurality of chips remote from the substrate; a passivation layer PVX1 disposed on a substrate-remote side of the terminal extension layer RDL 1; and a planarization layer PLN2 disposed on a side of the passivation layer PVX1 remote from the substrate.

For example, a TFT drive circuit may include at least one thin film transistor (i.e., TFT) and at least one storage capacitor, a gate of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in conductive layer CDL1, another electrode of the storage capacitor may be located in conductive layer CDL2, and a source and drain of the thin film transistor may be located in conductive layer CDL 3.

For example, a plurality of extension traces RL1 may be located in the terminal extension layer RDL 1. Each of the chips CP1, CP2, CP3, CP4 may include at least one terminal p 1. The terminals p1 of the respective chips CP1, CP2, CP3, CP4 are led out through the extension wirings RL 1.

A plurality of second tracks RL3 can be located in conductive layer CDL 3. The source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through vias that penetrate the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL. A plurality of third tracks RL4 can be located in conductive layer CDL 4. The plurality of third routing lines RL4 may be electrically connected with the plurality of second routing lines RL3 and the source and drain electrodes of the thin film transistors through vias penetrating through the planarization layer PLN1, respectively.

For example, the at least one extension trace RL1 can be electrically connected with a TFT driving circuit, for example, a source or a drain of a thin film transistor, through the third trace RL4 located in the conductive layer CDL 4. At least one extension trace RL1 may also electrically connect at least two of chips CP1, CP2, CP3, CP 4. In this way, it is possible to realize electrical connection between the TFT driving circuit and the chip, and electrical connection between a plurality of chips.

In the above embodiments, the thin film transistor is a top gate type thin film transistor, and it should be understood that embodiments of the present disclosure are not limited thereto. For example, the thin film transistor may also be a bottom gate type thin film transistor, for example, employing a back channel etch type structure (i.e., BCE type TFT).

Fig. 27 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the thin film transistor is a bottom gate type thin film transistor. Referring to fig. 27, in the process of forming the film structure of the TFT on the side of the buffer layer BFL away from the substrate, the gate material layer CDL1 may be prepared, the gate insulating layer GI1 may be formed, and the active layer ACT may be formed. For example, the gate material layer CDL1 may include Mo/Al/Mo or Mo/Cu, and the thickness may be 3000-6000 angstroms. The gate insulating layer GI1 may include silicon nitride or silicon oxide, and may have a thickness of 2000-5000 angstroms. The active layer ACT may include an oxide semiconductor material such as IGZO, IGTO, IZO, etc., and may have a thickness of 300 to 1000 angstroms.

Hereinafter, an application of the semiconductor device according to the embodiments of the present disclosure in a sensor scenario will be described in detail with reference to the accompanying drawings. It should be noted that, in the following description, the structure of the semiconductor device applied in the sensor scenario will be mainly described, and the manufacturing process thereof may refer to the above description, and will not be described herein again.

In the embodiment of the present disclosure, the chip having the integrated function is functionally divided into a plurality of microchips. In a sensor application scene, a plurality of chips can be arranged at the front end part, so that the information acquisition capability is improved, and the miniature rear end parts (such as a control part) of the front ends can share the control chip, so that the function optimization of a sensing device is facilitated through the chip splitting and part of function enhancement.

For example, with the increasing demands of huge screen, 3D display, virtual reality, etc. of the display screen, the demand for the space detection technology of the object also increases, for example, the object needs to be detected at a plurality of depths and a plurality of positions, so as to realize the intelligent display screen integrated with multi-region space detection. For example, in the existing space detection technology, an external module scheme is generally adopted. That is, the sensor for space detection is usually placed in the middle of the upper frame of the display or on the desktop in front of the display, the application space is limited, and there is a blind area for identification. For the existing 2D display, the gesture control can be realized when people stand in the optimal recognition range. However, for 3D display, the display image is distributed in multiple levels and positions, and the user wants to experience that the virtual object is touched at different positions, so that a device solution in which a sensor for spatial detection is integrated with a display element is becoming one of important issues to be focused on by developers.

In the following embodiments, a device scheme in which a sensor for space detection and a display element are integrated according to an embodiment of the present disclosure is described by taking an acoustic sensor as an example.

In embodiments of the present disclosure, the acoustic sensor may be functionally separated to form a plurality of microchips. For example, the acoustic sensor may include at least a signal acquisition chip and a signal processing chip. Fig. 28A and 28b are schematic block diagrams of acoustic sensors according to some embodiments of the present disclosure, and fig. 28C schematically illustrates an arrangement of the acoustic sensors in a display according to some embodiments of the present disclosure. Referring to fig. 28A and 28B, a plurality of microchips may be formed by functionally dividing the acoustic sensor. For example, a plurality of signal collection chips SNC1 may be provided in one acoustic sensor, and a plurality of signal collection chips SNC1 may be electrically connected to at least one signal processing chip. A plurality of signal acquisition chips SNC1 may be connected in series to increase the signal-to-noise ratio of the acquired signals, thereby increasing the signal detection sensitivity and enabling remote detection.

For example, one signal processing chip may include an LC filter circuit, an amplification circuit, a digital-to-analog conversion circuit, and a control circuit. The LC filter circuit can filter the signals collected by the signal collecting chip. The amplifying circuit may amplify, rectify, etc. the filtered signal. The digital-to-analog conversion circuit may perform digital-to-analog conversion on the amplified signal. The control circuit may receive the digital-to-analog converted signal and perform a corresponding control function based on the signal.

Alternatively, the signal processing chip may also be functionally split, so that one signal processing chip may include a plurality of microchips, for example, the LC filter circuit, the amplifying circuit, the digital-to-analog conversion circuit, and the control circuit may respectively form independent microchips, so that the respective microchips may be flexibly arranged. That is, the acoustic sensor may include an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3, and a control chip SNP 4.

For example, a plurality of signal collection chips SNC1 may be connected in series with each other and then electrically connected to the LC filter chip SNP1, the amplifier chip SNP2, the digital-to-analog conversion chip SNP3, and the control chip SNP4, and a plurality of signal collection chips SNC1, the LC filter chip SNP1, the amplifier chip SNP2, the digital-to-analog conversion chip SNP3, and the control chip SNP4 may be aligned as shown in fig. 28A. Thus, the acoustic sensor SR1 having such an arrangement may be disposed at a position intermediate the upper bezel of the display. The plurality of signal collection chips SNC1, the LC filter chip SNP1, the amplifier chip SNP2, the digital-to-analog conversion chip SNP3, and the control chip SNP4 may be arranged in a rectangle, as shown in fig. 28B. Thus, the acoustic sensor SR2 having such an arrangement may be disposed in the display area of the display. In the embodiments of the present disclosure, the sensor may be placed in the display area of the display, or may be placed on the bezel of the display. Moreover, since the sensor is divided into a plurality of microchips, the sensor can be flexibly arranged, for example, the sensor can be arranged in a row, a loop, a serpentine shape, a rectangular region, a circular region, an elliptical region, or the like; multiple microchips may be densely arranged in the blank area, or may be placed in the gaps between the pixels. That is to say, the sensor according to this disclosed embodiment can arrange on the display in a flexible way, has improved device performance and installation flexibility ratio to solve current device and surveyed the problem that the limitation can only be placed in the outer module mode.

In an embodiment of the present disclosure, the sensor may be a Si-based sensor. For example, the signal acquisition chip may include a transducer for acquiring an acoustic signal and converting it into an electrical signal. Fig. 29 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure, wherein the sensor is a Si-based sensor. Referring to fig. 29, the display device may include a substrate SUB 5; a drive element provided on the substrate SUB 5; a planarization layer PLN1 disposed on a substrate-remote side of the driving element; a conductive layer CDL4 disposed on a substrate-remote side of said planarization layer PLN 1; a planarization layer PLN2 disposed on a substrate-remote side of conductive layer CDL 4; a passivation layer PVX1 disposed on a substrate-remote side of the planarization layer PLN 2; a terminal extension layer RDL1 arranged on the side of the passivation layer PVX1 far away from the substrate; a passivation layer PVX2 disposed on a substrate-remote side of the terminal extension layer RDL 1; and a plurality of chips disposed on a side of the passivation layer PVX2 remote from the substrate. For example, the plurality of chips may be a signal acquisition chip SNC1, an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3, and a control chip SNP4 of the sensor.

A plurality of extension traces RL1 may be located in the terminal extension layer RDL 1. The plurality of signal acquisition chips SNC1 can be connected in series through the plurality of extension wiring RL1, and the plurality of extension wiring RL1 can also electrically connect the plurality of signal acquisition chips SNC1, the LC filter chip SNP1, the amplifier chip SNP2, the digital-to-analog conversion chip SNP3 and the control chip SNP4 which are connected in series in sequence.

In this embodiment, the driving element may include the TFT driving circuit, and the specific film structure may refer to the above description, which is not described herein again.

FIG. 30 schematically shows the increase in output voltage versus the number of transducers in series in a sensor according to an embodiment of the disclosure. Referring to fig. 30, in the embodiment of the present disclosure, the transducer and other signal processing circuits such as filtering and amplifying are separated, and a plurality of transducers are connected in series to increase the amount of received signals, as shown in fig. 30, and then pass through the circuits such as filtering and amplifying. Therefore, the sensitivity of the device can be increased, and detection at a longer distance can be realized. In addition, in the embodiment of the disclosure, the signal processing chip can be closely placed with the transducer, so that the RC load and noise are reduced, and the signal detection sensitivity is increased, thereby facilitating the detection at a longer distance.

In the embodiment shown in fig. 29, the TFT backplane and the terminal extension layer are fabricated first, and then the chip is bonded. However, embodiments of the present disclosure are not limited thereto, and the individual chips may be bonded side-by-side/stacked, chip-side down or chip-side up (i.e., face down/up), chip first or RDL first. Types of substrate SUB5 include, but are not limited to, glass substrates, PCBs, FPCs, etc.

Fig. 31 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric sensor including a piezoelectric film. Referring to fig. 31, in this embodiment, a plurality of piezoelectric sensing units, which are connected in series and bonded to a signal processing chip, are fabricated on a backplate including a TFT driving circuit.

It should be noted that, in this embodiment, a "piezoelectric film" is used for the purpose of illustration, and the embodiment of the present disclosure is not limited thereto, for example, a sensing chip included in a semiconductor device according to the embodiment of the present disclosure may include other types of sensors, and the sensors may include other types of functional films. That is, herein, the expression "functional thin film" includes, but is not limited to, a piezoelectric thin film.

In particular, the display device may include a substrate SUB 5; a drive element provided on the substrate SUB 5; a planarization layer PLN1 disposed on a substrate-remote side of the driving element; a conductive layer CDL4 disposed on a substrate-remote side of said planarization layer PLN 1; a piezoelectric film PVL disposed on a substrate-remote side of conductive layer CDL 4; and a conductive layer CDL5 disposed on a side of the piezoelectric film PVL remote from the substrate.

The piezoelectric sensing unit includes a first electrode E1, a second electrode E2, and a piezoelectric thin film PVL interposed between the first electrode E1 and the second electrode E2. For example, the piezoelectric film PVL may be a PVDF piezoelectric film. A plurality of first electrodes E1 are located in conductive layer CDL4 and a plurality of second electrodes E2 are located in conductive layer CDL 5. The first electrode E1 and the second electrode E2 of each piezoelectric sensing unit are oppositely and separately disposed.

Fig. 32 is a partially enlarged view of a portion iii in fig. 31. Referring to fig. 31 and 32 in combination, in the adjacent 2 piezoelectric sensing units, the first electrode E1 of one piezoelectric sensing unit is electrically connected with the second electrode E2 of the other piezoelectric sensing unit through a via or a groove. In this way, a series connection of a plurality of piezoelectric sensing units can be achieved.

In the process of forming a plurality of piezoelectric sensing units, a conductive layer may be deposited first, and a plurality of first electrodes E1 may be formed through a patterning process; then, spin-coating a PVDF piezoelectric thin film layer, and curing and dry-etching the PVDF piezoelectric thin film layer to form a patterned PVDF piezoelectric thin film; then, a conductive layer may be deposited, and a plurality of second electrodes E2 may be formed through a patterning process. For example, since the PVDF piezoelectric thin film layer has a large thickness, for example, several micrometers, a flat layer may be formed on the piezoelectric thin film layer, and then the second electrode E2 may be formed.

The signal processing chip may include at least two terminals p 1. For example, the terminals p1 may face downward, one terminal p1 may be electrically connected to the first electrode E1 of an adjacent one of the piezoelectric sensing units, and the other terminal p1 may be electrically connected to an extended trace located in the conductive layer CDL 4.

Referring to fig. 33A, the piezoelectric sensor may be separately manufactured, and then a plurality of piezoelectric sensing units may be formed by cutting.

Referring to fig. 33B, a backplane including a TFT driving circuit may be separately manufactured, for example, the backplane includes a substrate SUB 5; a drive element provided on the substrate SUB 5; and a planarization layer PLN1 disposed on a side of the driving element remote from the substrate. For example, conductive layer CDL4 can be formed on the side of planarization layer PLN1 remote from the substrate.

Referring to fig. 33C, a plurality of piezoelectric sensing units and chips are disposed on a back plate. For example, at least 2 conductive portions are formed in conductive layer CDL4, and at least 2 conductive portions are provided at intervals. 2 adjacent piezoelectric sensing units are placed on the same conductive part in a manner of opposite polarity. In the 2 piezoelectric sensing units placed on the same conductive portion, the first electrode E1 of one piezoelectric sensing unit and the second electrode E2 of the other piezoelectric sensing unit are in electrical contact with the conductive layer CDL 4.

With continued reference to fig. 33C, the planarization layer PLN2 on the substrate-away side of the plurality of piezoelectric sensing units and chips, and the rewiring layer RDL2 on the substrate-away side of the planarization layer PLN 2. A plurality of first traces RL2 are formed in the redistribution layer RDL 2. In the 2 piezoelectric sensing units placed on different conductive portions, the second electrode E2 of one piezoelectric sensing unit is electrically connected to the first electrode E1 of the other piezoelectric sensing unit through one first trace RL 2. In this way, a series connection of a plurality of piezoelectric sensing units can be achieved.

The signal processing chip may include at least two terminals p 1. For example, the terminal p1 may face upward, one terminal p1 may be electrically connected to the second electrode E2 of the adjacent one piezoelectric sensing unit through one first trace RL2, and the other terminal p1 may be electrically connected to an extended trace located in the redistribution layer RDL 2.

Fig. 34 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure. Referring to fig. 34, a plurality of piezoelectric sensing units may be arranged in an overlap-and-bottom bonded manner. For example, a piezoelectric sensing unit is placed on the conductive part with its first electrode E1 in contact with the conductive part and its second electrode E2 facing upward; the other piezoelectric sensing unit, the first electrode E1 of which is prevented from being on the piezoelectric sensing unit, is in contact with the second electrode E2 of the piezoelectric sensing unit. In this way, a series connection of a plurality of piezoelectric sensor units can also be realized.

In the embodiment, by independently manufacturing the piezoelectric sensor, the problem of incompatibility of production lines which may exist can be solved, the formation of a through hole in a piezoelectric film layer with large thickness is avoided, the problem of odd-even polarization is solved, and the process requirement of the piezoelectric film is reduced.

In the above embodiments, the driver circuit such as the TFT driver element and each chip are provided on the same substrate, and the detailed description is given by taking chip first and chip later processes as examples. However, embodiments of the present disclosure are not limited thereto, and for example, a driver circuit such as a TFT driver element and each chip may be fabricated on different substrates and then the semiconductor device may be formed by means of a pair of boxes.

Referring to fig. 35A, an adhesive layer AD1 is coated or adhered on a substrate SUB 7.

Referring to fig. 35B, the respective chips (e.g., the LED chip CP3 and the functional element CP4) are transferred onto the substrate SUB7 by SMT or bulk transfer process and fixed on the substrate by an adhesive layer AD 1.

For example, each die may be located on adhesive layer AD1, and terminal p1 of each die may be facing upward, i.e., on the side of the die away from the substrate.

The substrate (which may be referred to as a backplane) provided with the LED chip CP3 and the functional element CP4 is photographed, and coordinates and areas of the terminals p1 of the respective LED chips CP3 and functional elements CP4 provided on the backplane are determined using an image recognition technique, and a graphic file of a terminal area (i.e., pad area) is generated. And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension wirings RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wirings RL1 may be electrically connected to the terminals p1 of the respective LED chips CP3 and functional elements CP4, respectively, to lead out the respective terminals p 1. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

Referring to fig. 35C, a planarization layer PLN1 is applied to the side of the terminal extension layer RDL1 away from the substrate.

With continued reference to fig. 35C, vias can be formed through the planarization layer PLN1 and the passivation layer PVX2 to expose at least a portion of the respective extension traces RL 1. Then, a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, etching, and the like. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL 2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the vias, respectively, to further lead out each terminal p 1.

Alternatively, referring to fig. 35C, after the post-alignment process described above is completed, a redistribution layer RDL3 may be prepared according to the requirements of the line interconnect.

For example, a capping layer PLN2 may be formed on the side of redistribution layer RDL2 remote from the substrate. Then, a rewiring layer RDL3 was formed on the side of the cover PLN2 remote from the substrate.

For example, the rewiring layer RDL3 may be prepared by a conventional photolithography process to form the second wirings RL3 for electrically connecting the respective chips in the rewiring layer RDL 3. Embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL3 may also be prepared by a post-alignment process.

For example, according to the requirement of the extension wiring, a fourth layer wiring, a fifth layer wiring, and the like can also be prepared, and the embodiments of the present disclosure are not particularly limited herein.

Referring to fig. 35D, a back plate including a TFT driving element is prepared. For example, the backplane may include a substrate SUB 8; a drive element provided on the substrate SUB 8; and a plurality of terminals p2 provided on a substrate-remote side of the drive element.

Referring to fig. 35E, the backplane and the substrate SUB7 provided with the chip are set for a box. For example, the plurality of terminals p2 on the backplane are electrically connected to the plurality of second traces RL3 in the redistribution layer RDL3, respectively, so as to electrically connect the driving element and the chip.

As described above, in the embodiment of the present disclosure, the chips may be arranged with a certain precision, and then the positions, areas, and features of the chips and the terminals (i.e., pads) are identified and analyzed by the post-alignment process, and the high-precision automatic wiring and chip bonding is realized by combining with the photolithography process. Through the post-alignment process, the bonding precision of the microchip can be improved, and the integration of the chip and other circuits is facilitated. Moreover, the post-alignment process is arranged, so that the requirement on the precision of the chip transfer process can be reduced, namely the difficulty of the chip transfer process is favorably reduced. In addition, the automatic wiring process can simultaneously carry out high-precision bonding on a large number of chips transferred in a large area, improves bonding efficiency, and is more suitable for bonding large-batch and large-area chips.

Figure 36A schematically illustrates a top view of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure. In the embodiment shown in fig. 36A, a partial top view of a display substrate is shown, taking a display device as an example. Referring to fig. 36A, a substrate SUB9 has a plurality of pixels PX disposed thereon, for example, the plurality of pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like. The display pixels include, but are not limited to, OLED, micro LED, miniLED, LCD, etc. display elements.

A plurality of chips CP are also provided on the substrate SUB 9. For example, a plurality of chips CP may be transferred onto substrate SUB9 by SMT or bulk transfer processes. Then, a plurality of extension traces RL1 can be formed using the post-alignment process to electrically connect the plurality of chips CP. Specifically, a substrate (which may be referred to as a backplane) provided with the chips CP is photographed, and parameters such as coordinates, areas and appearances of the terminals p11 of the chips CP provided on the backplane are determined by using an image recognition technology, so as to generate a graphic file of a terminal area (i.e., a pad area). For example, fig. 36A schematically shows the photo-taking regions PTA corresponding to the respective chips CP. From the coordinates of the terminal p11 of each chip CP with respect to the origin on the substrate SUB9, the coordinates of the terminal p11 of each chip CP can be determined; also, the area and the shape of the terminal p11 of each chip CP can be determined by using an image recognition technique.

In addition, in the process of identifying and analyzing the picture, the visual graph on the backboard can be judged and detected badly so as to identify the connecting line of the broken circuit on the backboard, the metal extension wiring of the post-alignment process is utilized to repair the bad points on the backboard, and the chips which can not be connected due to overlarge offset after transfer are screened. For example, the coordinate information of each defective point may be determined using an image recognition technique.

And then, depositing a metal layer on the whole backboard, coating photoresist on the metal layer, and patterning the photoresist by a digital direct writing or digital exposure machine according to the graphic file. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 may be electrically connected to the terminals p11 of the respective chips CP through vias, respectively, so as to lead out the respective terminals p 11. That is, through the post-alignment process, extension traces RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL 1.

For example, referring to fig. 36A, the software may determine the path of the automatic wiring based on the coordinates of the terminal p11 of each chip CP in combination with the actual transfer of the chip on each substrate. For example, in determining the route of the automatic wiring, it may be considered to avoid functional areas such as display pixels so that the wiring route is distributed in a gap area between pixels to electrically connect the respective chips.

For example, the photoresist may be patterned by a digital direct writing or digital exposure machine according to the coordinate information of each defective point. The metal layer is then etched according to the patterned photoresist to form terminal extension layer RDL 1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 can be electrically connected with each bad point through a via hole respectively to repair each bad point.

Fig. 39A, 39B, and 39C schematically show shot regions formed in the post-alignment process, respectively. Referring to fig. 39A, each chip on the back plate may be a full-screen closely-spaced chip, for example, a micro led chip in a display device. In this case, the microscope takes a position MARK (MARK) of the whole backboard as an origin, photographs according to a fixed stepping distance and then translates to the next photographing area, and the actual photographing times are related to the size of the backboard and the density of chips. One or more chips may be provided in one photographing region. Referring to fig. 39B, the chips are not closely arranged on the backplane, i.e., the number of chips is small. In this case, the photographing region may be a region surrounding an ideal position of the chip, and a coverage of one photographing region may be larger than a range in which the chip may be shifted, ensuring that the chip is in the photographing region. A calibration MARK (MARK) can be made on the back plate as an origin point for determining the actual coordinates of the chip after transfer. Referring to fig. 39C, regularly arranged position MARK MARKs (MARK1) may be made on the backplane, and the position between the position MARK (MARK1) in each single image and the backplane global absolute coordinate MARK (MARK0) is relatively fixed for converting the chip position in each photographed single image into absolute position coordinates relative to the backplane as a whole. When a plurality of chips are arranged in a photographing area at one time and the arrangement density is high, in order to prevent adjacent images from being not completely sealed due to movement errors of a machine and avoid the problem of edge image distortion of a single image due to a lens imaging mode, overlapped photographing areas can exist between the adjacent photographing areas, and the images of all the chips are completely photographed. Because each single image is provided with the position calibration MARK (MARK1), image splicing is not needed when the coordinates of the chip are subjected to image recognition, the coordinates of the position of the chip in the single image relative to the position calibration MARK (MARK1) in the single image are calculated only after the image recognition, and the absolute coordinates of the position of the chip in the single image relative to the whole backboard absolute coordinate calibration MARK (MARK0) are obtained by converting the position relationship between the position calibration MARK (MARK1) in the single image and the whole backboard absolute coordinate calibration MARK (MARK 0).

Fig. 36B and 36C each schematically illustrate a top view of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure. Fig. 37A and 37B are sectional views taken along line AA' in fig. 36B. Fig. 38 schematically shows a partially enlarged view of the wiring between two chips.

Referring to fig. 36B and 38, in an embodiment of the present disclosure, a plurality of fixed connections 12 may be provided on the substrate SUB 9. For example, at least two fixed connections 12 may be provided near the position where each chip CP is located. The extended trace for electrically connecting the two chips CP may include at least a first trace segment RL11 for connecting the terminal p1 of one chip with one fixed connection 12 adjacent to the chip, a second trace segment RL12 for connecting the two fixed connections 12 between the two chips, and a third trace segment RL13 for connecting the terminal p1 of another chip with one fixed connection 12 adjacent to the other chip.

It should be noted that in this embodiment, for convenience of description, the expressions of a first routing segment, a second routing segment and a third routing segment are used, and it should be understood that the first routing segment and the third routing segment are used for electrically connecting one terminal of the chip and the fixed connection portion, so they may be both referred to as a first routing segment; the second route segment is used for electrically connecting the two fixed connecting parts. That is, in this document, the expressions first trace segment and second trace segment may also be used to distinguish different portions of one extended trace.

For example, each chip CP may have a mark that can distinguish different pads according to pictures, and the actual coordinates of each chip are calculated and determined by the photographed image after recognition analysis. The markings on the chip may include, but are not limited to, features of the topography, shape, size, orientation, etc. of the pads on the chip. Alternatively, specialized features may be fabricated to distinguish the pads of different chips.

For example, the second routing segment RL12 can be fabricated on the backplane by using a conventional photolithography process, and the post-alignment process forms only the first routing segment RL11 and the third routing segment RL 13. Referring to fig. 37A, the first trace segment RL11 and the third trace segment RL13 may be located in the terminal extension layer RDL1, and the second trace segment RL12 is located in a different layer from the terminal extension layer RDL 1.

For example, the first routing segment RL11, the second routing segment RL12 and the third routing segment RL13 can be formed by a post-alignment process. Referring to fig. 37B, the first track segment RL11, the second track segment RL12 and the third track segment RL13 may be located in the terminal expansion layer RDL 1. That is, the first routing segment RL11, the second routing segment RL12 and the third routing segment RL13 can be the same layer of metal extension routing.

For example, the spacing between the fixed connection 12 and the center of the ideal transfer position of the chip may be greater than the maximum amount of offset that may occur during chip transfer. For example, in the case where the maximum amount of shift that can occur during chip transfer is about 10 micrometers, the spacing between the fixed connection 12 and the center of the ideal transfer position of the chip is greater than 10 micrometers.

It should be understood that the routing paths of the routing wires between the fixed connection parts 12 are relatively fixed, for example, the routing paths of the routing wires between the fixed connection parts 12 may be set to be the same for the same product, i.e., the routing paths of the second routing segments RL12 are the same. In this way, when the wiring path is determined by calculation, it is not necessary to calculate the wiring path of each second wiring segment RL12, so that the complexity of automatic wiring can be reduced. When confirming the wiring route, can be according to the actual position of each chip after the transfer, the wiring route between the terminal of each chip and the fixed connection portion of accurate calculation, promptly, carry out local update to the wiring route according to the actual position of chip, be favorable to improving the precision and the efficiency of automatic wiring.

With combined reference to fig. 4, 36B and 36C, at least one second track segment RL12 extends along the first direction or the second direction; and in two chips electrically connected through an extended trace including a second trace segment extending in a first direction or a second direction, a relative position of one chip in the first direction is different from a relative position of the other chip in the first direction.

For example, in two chips electrically connected by an extended trace comprising at least one second trace segment, at least one chip is inclined with respect to the extension of said second trace segment RL 12. For example, 4 chips as shown in fig. 36C.

For example, in two chips electrically connected by an extended trace including at least one second trace segment, the orientation of one chip with respect to the extension line of the second trace segment RL12 is different from the orientation of the other chip with respect to the extension line of the second trace segment RL 12. For example, the two chips on the left side illustrated in fig. 36B.

For example, in two chips electrically connected by extended traces including at least one second trace segment, each of the chips includes a plurality of terminals including at least a first terminal (e.g., a left terminal of the chip shown in fig. 36B, 36C) and a second terminal (e.g., a right terminal of the chip shown in fig. 36B, 36C). The second routing section RL12 included in the extended routing for electrically connecting the first terminals of the two chips and the second routing section RL12 included in the extended routing for electrically connecting the second terminals of the two chips are parallel to each other, and/or the second routing section RL12 included in the extended routing for electrically connecting the first terminals of the two chips and the second routing section RL12 included in the extended routing for electrically connecting the second terminals of the two chips are substantially equal in length.

For example, at least one of the first track segments RL11 and RL13 has an included angle with the second track segment RL12 adjacent to and electrically connected with it, the included angle is greater than 0 ° and less than 180 °.

For example, in the two first trace segments RL11 and RL13 adjacent to and electrically connected with the same second trace segment RL12, the included angle between one first trace segment RL113 and the second trace segment RL12 adjacent to and electrically connected with it is different from the included angle between the other first trace segment RL13 and the second trace segment RL12 adjacent to and electrically connected with it.

For example, in the two first routing segments electrically connected to the first terminal and the second terminal of the same chip, the included angle between one first routing segment RL11 and the second routing segment RL12 adjacent to and electrically connected to it is different from the included angle between the other first routing segment RL11 and the second routing segment RL12 adjacent to and electrically connected to it.

For example, the second routing segments RL12 between the fixed connection portions 12 may be configured as buses that can be shared by different products according to common characteristics of the products, such as transfer accuracy deviation or chip connection manner; or the intelligent bus is electrically connected with the gating circuit on the chip or the backboard, so that the intelligent bus can be used as the intelligent bus with the gating function.

Referring to fig. 36B and 36C in combination, the actual positions of the respective chips may be different for the same product under the influence of the accuracy of the transfer process. Due to the fixed connection parts 12, the paths of the second routing segments RL12 between the fixed connection parts 12 can be the same. When calculating the actual wiring path, only the paths of the first routing segment RL11 and the third routing segment RL13 need to be updated in a layout mode.

In an embodiment of the present disclosure, the semiconductor device may be a display device. The driving element of the display device may be provided in the form of a driving chip. Fig. 40A to 40C schematically show the arrangement of the driving chip and each pixel of the display device according to the embodiment of the present disclosure, respectively.

For example, the driving chip CP1 serving as a driving element may be electrically connected to a portion corresponding to a pixel, so that the driving chip CP1 may drive a plurality of pixels PX. That is, in the embodiments of the present disclosure, there is no need to provide a driving circuit on the back plate. For example, the plurality of pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like. The display pixels include, but are not limited to, OLED, micro LED, miniLED, LCD, etc. display elements.

Referring to fig. 40A, one chip CP may include at least 2 terminals p1, for example, 4 terminals p 1. At least 2 pixels PX, for example, 4 pixels PX may be disposed around one chip CP. The 4 terminals p1 of one chip CP are electrically connected to the 4 pixels PX surrounding it through the extension wirings RL7, respectively. For example, if the pixel PX is a display pixel, the 1 terminal p1 of one chip CP is electrically connected to the anode of the display pixel through the extension wiring RL7, and the chip CP can supply a driving signal to the display pixel. If the pixel PX is a sensor pixel, the 1 terminal p1 of a chip CP is electrically connected to one electrode of the sensor pixel through the extension wiring RL7, and the chip CP can receive the sensing signal from the sensor pixel and perform certain processing (e.g., filtering, amplifying).

For example, multiple chips CP can be electrically connected to a master chip CP10 through extended traces RL 8.

For example, the chip CP may be a driving chip corresponding to the display pixel; corresponding to the sensor pixel, the chip CP can be a power amplifier chip, and the master control chip CP10 can be an ADC chip.

In the embodiment of the present disclosure, the extension track RL7 and the extension track RL8 may be located in the same terminal extension layer, or the extension track RL7 and the extension track RL8 may be located in different terminal extension layers. For example, extension trace RL7 and extension trace RL8 can be formed by the post-alignment process described above.

The routing manner of each of the extension traces RL7 and RL8 can be determined according to the pitch between chips. If the distance between the chips is relatively close, for example, the distance is a distance of a plurality of pixels, a direct extension wiring mode can be adopted according to the actual coordinates of the chips. If the distance between the chips is long and the connection path is complicated, the combination of the fixed extension routing and the flexible extension routing provided in the above embodiments can be adopted. For example, the extension trace RL8 between chips can adopt a fixed extension trace mode, and the extension trace RL7 between chips and pixels can adopt a flexible extension trace mode.

For example, one general control chip CP10 and a plurality of chips CP may constitute one chipset, and one or more such chipsets may be disposed on the backplane.

It should be noted that the corresponding relationship between the number of chips CP having the driving circuit and the number of pixels PX may be determined according to the PPI of the display device and the extended routing space that can be provided, for example, the chips CP and the pixels PX may correspond one to one, or one chip CP may correspond to all the pixels PX on the back plate.

Referring to fig. 40B, the pixels PX on the back plate may be different types of pixels, for example, the pixels PX may include a red sub-pixel (i.e., R sub-pixel), a green sub-pixel (i.e., G sub-pixel), and a blue sub-pixel (i.e., B sub-pixel). In this case, one chip CP may have 6 terminals p1 (i.e., 6 interfaces). The 6 terminals p1 are electrically connected with the R/G/B sub-pixels of the two pixels through the extension wirings RL7, respectively.

Referring to fig. 40C, both the display pixels and the sensor pixels may be disposed on the backplane. In this case, one chip CP may have interfaces (i.e., terminals) having different functions, such as a driver interface and a power amplifier interface. Through the post-alignment process, the position of the chip pad is judged after image recognition, and the chip CP is correctly connected with each pixel PX. For example, the display pixel PX may be electrically connected to the terminal p11 of the chip CP, and the sensor pixel PX may be electrically connected to the terminal p12 of the chip CP.

In an embodiment of the present disclosure, the display device may include a light emitting element. For example, the light emitting element may be a top emission light emitting element, and the chip CP may be disposed below the light emitting element; alternatively, the light emitting element may be a bottom emission light emitting element, and the chip CP may be disposed above the light emitting element. Fig. 41 schematically shows the projection relationship of the chip and the pixel. Referring to fig. 41, the orthographic projection of the chip CP on the substrate may partially overlap with the orthographic projection of the plurality of pixels PX on the substrate. In this way, a display device having a higher PPI can be realized.

In the embodiments of the present disclosure, a chip driving manner on a smaller scale can be realized. In addition, because a plurality of total control chips can be arranged, the total control chips can also be electrically connected to a higher-level control chip, and therefore respective control of each area can be realized.

In an embodiment of the present disclosure, the display device may include a gating chip CP12 disposed on the backplane. For example, the gate chip CP12 may include a gate TFT or a gate-level circuit. Fig. 42 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure. Fig. 43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure. Fig. 44A and 44B are circuit connection diagrams of a display device including a gate chip according to an embodiment of the present disclosure, respectively.

Referring to fig. 42 to 44B in combination, the display apparatus may include a gate chip CP12, a chip CP, and a total control chip CP 10. One of the gated chips CP12 may include at least 2 ports (e.g., 4 ports MUX1/MUX2/MUX3/MUX4), and one of the chips CP may include at least 2 terminals p1 (e.g., 4 terminals p 1). The plurality of pixels PX located in the same row may be electrically connected by a row signal connection line L1, and the plurality of pixels PX located in the same column may be electrically connected by a column signal connection line L2. The ports MUX1 to MUX4 of the gating chip CP12 may be electrically connected to the row signal connecting lines L1 through the extension traces RL13, respectively. One terminal p1 of one chip CP may be electrically connected to a plurality of pixels in the same column through a plurality of gate TFTs, respectively. The gating chip CP12 and the plurality of chips CP may also be electrically connected to the general control chip CP10 through extension traces RL 14. For example, a plurality of gating chips, at least one master control chip and a plurality of chips may form a chipset, and a plurality of such chipsets may be disposed on the backplane.

For example, under the control of a row strobe signal sent from a certain port of the strobe chip CP12, the pixels of a certain row can be controlled to be turned on. Under the control of the column strobe signal, the corresponding chip CP may be controlled to send a driving signal to the pixels of a certain column. In this way, partitioned display and individual control of pixels on the backplane can be achieved under control of the strobe signal.

Similarly, for example, the pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like. The display pixels include, but are not limited to, OLED, micro LED, miniLED, LCD, etc. display elements.

It should be noted that some steps of the above-mentioned manufacturing method can be executed individually or in combination, and can be executed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figures.

As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, and are intended to explain the inherent deviation of a measured or calculated value that would be recognized by one of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated values and indicates that the particular values determined by one of ordinary skill in the art are within acceptable deviation ranges, taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of the particular quantities (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 10% or ± 5% of the stated value.

Although a few embodiments of the present general inventive concept have been illustrated and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that the semiconductor device comprises:

the first substrate and the second substrate are oppositely arranged;

a chip disposed on the first substrate, the chip including a chip body and a plurality of first terminals disposed on the chip body;

a terminal extension layer disposed on the first substrate, the terminal extension layer comprising a conductive material; and

a plurality of second terminals disposed on the second substrate,

the terminal extension layer and the at least one first terminal are located on the same side of the chip main body, the semiconductor device further comprises a plurality of extension wires located in the terminal extension layer, and the plurality of extension wires are electrically connected with the plurality of first terminals respectively and used for leading out the plurality of first terminals;

the orthographic projection of a plurality of extension wires on the first substrate completely covers the orthographic projection of a first terminal electrically connected with the extension wires on the first substrate; and

2. The semiconductor device according to claim 1, further comprising a plurality of driving elements provided over the second substrate, wherein the plurality of second terminals are located on a side of the plurality of driving elements away from the second substrate, and wherein the plurality of second terminals are electrically connected to the plurality of driving elements, respectively.

3. The semiconductor device according to claim 1, wherein the chip includes a plurality of first terminals each located on a side of a chip body of the chip away from the first substrate; and

the semiconductor device further includes an adhesive layer disposed between the first substrate and the chip body for fixing the at least one chip on the first substrate.

4. The semiconductor device according to claim 1, wherein the chip includes a plurality of first terminals which are respectively located on both sides of a chip main body of the chip in a direction parallel to a first substrate surface of the first substrate which provides the first substrate with a surface of the chip; and

the semiconductor device further comprises an adhesive layer disposed between the first substrate and the chip body for fixing the chip on the first substrate.

5. The semiconductor device according to claim 1, wherein the chip includes a plurality of first terminals which are respectively located on both sides of a chip main body of the chip in a direction perpendicular to a first substrate surface of the first substrate which provides the first substrate with a surface of the chip; and

the semiconductor device further includes an adhesive layer disposed between the first substrate and the chip main body, and a first conductive layer disposed between the adhesive layer and the chip, the first conductive layer being electrically connected to at least one first terminal of the chip near the first substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first substrate comprises a first substrate surface on which the chip is provided, the first substrate surface comprising a first substrate edge; and

an orthographic projection of at least one extension trace on the first substrate is inclined relative to the first substrate edge.

7. The semiconductor device according to claim 6, wherein the chip body has a second surface remote from the first substrate, an orthographic projection of the second surface on the first substrate having a regular shape, the orthographic projection of the second surface on the first substrate including a first edge; and

the first edge is inclined relative to the first substrate edge.

8. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of second terminals on a second substrate; and

photographing the substrate provided with the chip;

9. The method of manufacturing according to claim 8, wherein the placing the chip on the first substrate comprises:

forming an adhesive layer on the first substrate; and