CN115084024A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115084024A CN115084024A CN202210844775.1A CN202210844775A CN115084024A CN 115084024 A CN115084024 A CN 115084024A CN 202210844775 A CN202210844775 A CN 202210844775A CN 115084024 A CN115084024 A CN 115084024A
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 127
- 239000002184 metal Substances 0.000 claims abstract description 127
- 239000000758 substrate Substances 0.000 claims abstract description 122
- 150000004767 nitrides Chemical class 0.000 claims abstract description 64
- 230000008569 process Effects 0.000 claims abstract description 62
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 34
- 238000000137 annealing Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 322
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 15
- 229910021334 nickel silicide Inorganic materials 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000002161 passivation Methods 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
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- 238000006243 chemical reaction Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
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- 229910021529 ammonia Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention provides a semiconductor device and a preparation method thereof, comprising the following steps: providing a substrate, wherein a plurality of grid structures are formed on the substrate, side wall protection layers are formed on two sides of each grid structure and comprise an oxide layer and a nitride layer, the oxide layers cover two sides of each grid structure and part of the surface of the substrate, and the nitride layer is positioned on the oxide layers and covers the side surfaces and the top surfaces of the oxide layers; forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, exposing partial side of the oxide layer between the nitride layer and the substrate, and contacting the metal layer on the surface of the substrate with the oxide layer; etching to remove part of the oxide layer to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer from the metal layer; forming a barrier layer to cover the metal layer and fill at least part of the gap; performing a thermal annealing process to form metal silicide in the substrate on both sides of the gate structure; the invention improves the sidetrack phenomenon of the metal silicide.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The self-aligned nickel silicide process is used when the characteristic size of a semiconductor device reaches below 65nm, after the ion implantation of a source region and a drain region of the device is completed, a layer of nickel metal is plated on the surface of the device, the nickel metal and silicon form low-resistance nickel silicide through thermal reaction, and the nickel metal cannot react with the silicon because a nitride layer is formed on the side wall of a channel, so that the nickel metal can be selectively removed, and only the nickel silicide on the source region, the drain region and a grid polycrystalline silicon layer is reserved, namely the self-aligned nickel silicide process. And a through hole structure is formed on the nickel silicide later, so that the contact resistance of the device can be obviously reduced. Compared with the traditional cobalt silicide process, the self-aligned nickel silicide process has the characteristics of no narrow line width effect and high stability.
The existing self-aligned nickel silicide process still has certain defects, the most obvious problem is the problem of sidetracking of nickel silicide, and if oxygen atoms participate in the formation process of nickel silicide, unstable compounds are generated on the interface of nickel silicide and silicon, so that the nickel silicide generates sidetracking phenomenon, and the device generates electric leakage.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to the prior art after a substrate is provided; FIG. 2 is a schematic cross-sectional view illustrating a metal layer and a barrier layer formed in a method for manufacturing a semiconductor device according to the prior art; fig. 3 is a schematic cross-sectional view illustrating a thermal annealing process performed in a method for manufacturing a semiconductor device according to the related art. Referring to fig. 1, a substrate 10 is provided, a plurality of gate structures 20 are formed ON the substrate 10, and at least one ON structure layer is formed ON two sides of the gate structures 20, the ON structure layer including an oxide layer and a nitride layer. In fig. 1, two ON structure layers are shown, namely a first ON structure layer and a second ON structure layer, the second ON structure layer (not shown) covers the side surface of the gate structure 20, the first ON structure layer includes a first oxide layer 31 and a first nitride layer 32, the first oxide layer 31 covers the side surface of the gate structure 20 and a portion of the surface of the substrate 10, the first nitride layer 32 is located ON the first oxide layer 31 and covers the side surface and a portion of the top surface of the first oxide layer 31, and the first oxide layer 31 is spaced between the first nitride layer 32 and the substrate 10; and forming a plurality of doped regions in the substrate 10, wherein the doped regions are located between two adjacent gate structures 20, the doped regions are used as source regions 41 or drain regions 42, and the source regions 41 and the drain regions 42 are arranged in the substrate 10 at intervals.
Referring to fig. 2, a metal layer 50 is formed to cover the exposed surfaces of the substrate 10, the gate structure 20 and the ON structure layer, the metal layer 50 ON the surface of the substrate 10 is in contact with a portion of the surface of the first oxide layer 31, and the metal layer 50 is made of nickel; further, a barrier layer 60 is formed to cover the metal layer 50, and the barrier layer 60 can isolate oxygen.
Referring to fig. 3, a thermal annealing process is performed to form a metal silicide 51, i.e., a nickel silicide, in the substrate 10 on both sides of the gate structure 20. Because the metal layer 50 on the surface of the substrate 10 is in contact with the first oxide layer 31, when the thermal annealing process is performed, the metal layer 50 on the surface of the substrate 10 and the first oxide layer 31 are likely to react to generate an unstable compound, so that the metal silicide 51 on the surface of the substrate 10 is likely to generate a sidetrack phenomenon (shown by a circular dotted frame in fig. 3), that is, the nickel silicide is likely to generate a sidetrack phenomenon, thereby increasing the leakage current of the device and easily causing the device failure.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which can improve the sidetracking phenomenon of metal silicide so as to improve the stability of the device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a plurality of grid structures are formed on the substrate, side wall protection layers are formed on two sides of each grid structure and comprise an oxide layer and a nitride layer, the oxide layers cover two sides of each grid structure and extend to cover part of the surface of the substrate, the nitride layer is positioned on the oxide layers and covers the side surfaces and the top surfaces of the oxide layers, and the oxide layers are arranged between the nitride layer and the substrate at intervals;
forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, and expose a part of the side surface of the oxide layer between the nitride layer and the substrate, wherein the metal layer on the surface of the substrate is in contact with the oxide layer;
etching to remove part of the oxide layer so as to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer and the metal layer;
forming a barrier layer to cover the metal layer and fill at least part of the gap so that the metal layer on the surface of the substrate is covered by three sides of the barrier layer; and the number of the first and second groups,
and performing a thermal annealing process to form metal silicide in the substrate on two sides of the gate structure.
Optionally, the material of the metal layer includes nickel.
Optionally, the thickness of the metal layer is smaller than that of the oxide layer, and the thickness of the metal layer is 50A-200A.
Optionally, the metal layer is formed by a first physical vapor deposition process.
Optionally, a plasma precleaning process is used to etch and remove a part of the oxide layer.
Optionally, the etching gas of the plasma precleaning process comprises NF 3 And NH 3 。
Optionally, the material of the barrier layer includes titanium nitride.
Optionally, the barrier layer is formed by a second physical vapor deposition process.
Optionally, the step of performing the thermal annealing process includes:
performing a first thermal annealing process to form the metal silicide in the substrate on both sides of the gate structure;
removing the barrier layer and the unreacted metal layer; and the number of the first and second groups,
and performing a second thermal annealing process to reduce the resistance of the metal silicide.
The invention also provides a semiconductor device which is prepared by the preparation method of the semiconductor device.
In the semiconductor device and the preparation method thereof provided by the invention, a plurality of grid structures are formed on a substrate, side wall protective layers are formed on two sides of each grid structure, each side wall protective layer comprises an oxide layer and a nitride layer, the oxide layers cover two sides of each grid structure and extend to cover part of the surface of the substrate, the nitride layers are positioned on the oxide layers and cover the side surfaces and the top surfaces of the oxide layers, and the oxide layers are arranged between the nitride layers and the substrate at intervals; forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, exposing partial side surfaces of the oxide layer between the nitride layer and the substrate, and contacting the metal layer on the surface of the substrate with the oxide layer; etching to remove part of the oxide layer to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer from the metal layer; forming a barrier layer to cover the metal layer and fill at least part of the gap so as to enable three sides of the barrier layer to cover the metal layer on the surface of the substrate; and performing a thermal annealing process to form metal silicide in the substrate on both sides of the gate structure. According to the invention, the metal layer on the surface of the substrate is contacted with the oxide layer to cause the sidetracking phenomenon of the metal silicide, namely, a gap is formed by removing part of the oxide layer, the gap plays a role of isolating the oxide layer from the metal layer, the barrier layer fills at least part of the gap to cover the metal layer on the surface of the substrate by three sides, the effect of isolating the oxide layer from the metal layer is also played, the metal layer is prevented from flowing in a thermal annealing process, and when the thermal annealing process is carried out, the metal layer is not contacted with the oxide layer to react to generate an unstable compound, so that the sidetracking phenomenon of the metal silicide is improved, the leakage current of a device is reduced, and the stability of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to the prior art after a substrate is provided.
Fig. 2 is a schematic cross-sectional view illustrating a metal layer and a barrier layer formed in a method for manufacturing a semiconductor device according to the prior art.
Fig. 3 is a schematic cross-sectional view illustrating a thermal annealing process performed in a method for manufacturing a semiconductor device according to the related art.
Fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention after a substrate is provided.
Fig. 6 is a schematic cross-sectional view illustrating a metal layer formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention after forming a void.
Fig. 8 is a schematic cross-sectional view illustrating a barrier layer formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a thermal annealing process performed in a method for manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a passivation layer, a source plug, a drain plug, and a gate plug formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
The reference numerals in fig. 1 to 3 are:
10-a substrate; 20-a gate structure; 31-a first oxide layer; 32-a first nitride layer; a 41-source region; 42-a drain region; 50-a metal layer; 51-metal silicide; 60-barrier layer.
The reference numerals in fig. 5 to 10 are:
100-a substrate; 200-a gate structure; 210-a gate polysilicon layer; 220-a gate oxide layer; 311-a first oxide layer; 312 — a first nitride layer; 321-a second oxide layer; 322-a second nitride layer; 410-a source region; 420-a drain region; 500-a metal layer; 510-metal silicide; 600-a barrier layer; 700-a passivation layer; 810-source plug; 820-drain plug; 830-gate plugs.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. Referring to fig. 4, the present embodiment provides a method for manufacturing a semiconductor device, including:
step S1: providing a substrate, wherein a plurality of grid structures are formed on the substrate, side wall protection layers are formed on two sides of each grid structure and comprise an oxide layer and a nitride layer, the oxide layers cover two sides of each grid structure and extend to cover part of the surface of the substrate, the nitride layer is positioned on the oxide layers and covers the side surfaces and the top surface of the oxide layers, and the oxide layers are arranged between the nitride layers and the substrate at intervals;
step S2: forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, exposing partial side of the oxide layer between the nitride layer and the substrate, and contacting the metal layer on the surface of the substrate with the oxide layer;
step S3: etching to remove part of the oxide layer to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer from the metal layer;
step S4: forming a barrier layer to cover the metal layer and fill at least part of the gap so that three sides of the barrier layer cover the metal layer on the surface of the substrate;
step S5: a thermal annealing process is performed to form a metal silicide in the substrate on both sides of the gate structure.
Fig. 5 is a schematic cross-sectional view after a substrate is provided in the method for manufacturing a semiconductor device provided in this embodiment; fig. 6 is a schematic cross-sectional view after a metal layer is formed in the method for manufacturing a semiconductor device according to this embodiment; fig. 7 is a schematic cross-sectional view after forming a void in the method for manufacturing a semiconductor device according to the present embodiment; fig. 8 is a schematic cross-sectional view after forming a barrier layer in the method for manufacturing a semiconductor device according to this embodiment; fig. 9 is a schematic cross-sectional view illustrating a thermal annealing process performed in the method for manufacturing a semiconductor device according to the present embodiment; fig. 10 is a schematic cross-sectional view illustrating a passivation layer, a source plug, a drain plug, and a gate plug formed in the method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing the semiconductor device according to the present embodiment will be described in detail with reference to fig. 5 to 10.
Referring to fig. 5, step S1 is executed: a substrate 100 is provided, the substrate 100 being a silicon substrate. A plurality of gate structures 200 are formed on the substrate 100, and in the present embodiment, the gate structures 200 include a gate polysilicon layer 210 and a gate oxide layer 220, and the gate oxide layer 220 is located between the gate polysilicon layer 210 and the substrate 100.
The gate structure 200 has sidewall protection layers formed on both sides thereof, and the sidewall protection layers serve to protect the gate polysilicon layer 210 in a subsequent ion implantation process. The sidewall protection layer includes at least one ON structure layer, where the ON structure layer includes an oxide layer and a nitride layer, and when the sidewall protection layer includes only one ON structure layer, the oxide layer covers both sides of the gate structure 200 and extends to cover a portion of the surface of the substrate 100, the nitride layer is located ON the oxide layer and covers the sides and top of the oxide layer, and the oxide layer is spaced between the nitride layer and the substrate 100. In fig. 5, two ON structure layers are shown, namely a first ON structure layer and a second ON structure layer, the second ON structure layer covers two sides of the gate structure 200, the first ON structure layer covers a side surface of the second ON structure layer, the first ON structure layer includes a first oxide layer 311 and a first nitride layer 312, and the second ON structure layer includes a second oxide layer 321 and a second nitride layer 322. Specifically, the second oxide layer 321 covers the side surface of the gate structure 200 and a portion of the surface of the substrate 100 (the second oxide layer 321 is L-shaped), and the second nitride layer 322 is located on the second oxide layer 321 and covers the side surface and a portion of the top surface of the second oxide layer 321; the first oxide layer 311 covers the side surface of the second nitride layer 322 and extends to cover a portion of the surface of the substrate 100 (the first oxide layer 311 is L-shaped), the first nitride layer 312 is located on the first oxide layer 311 and covers the side surface and a portion of the top surface of the first oxide layer 311, and the first oxide layer 311 is spaced between the first nitride layer 312 and the substrate 100.
In this embodiment, the sidewall protection layer needs to include an oxide layer (the first oxide layer 311) and a nitride layer (the first nitride layer 312), i.e., the sidewall protection layer only includes the first ON structure layer, and the second ON structure layer can be omitted according to practical situations. When the second ON structure layer is omitted, the oxide layer (the first oxide layer 311) covers the side surface of the gate structure 200 and extends to cover a portion of the surface of the substrate 100, the nitride layer (the first nitride layer 312) is located ON the oxide layer (the first oxide layer 311) and covers the side surface and a portion of the top surface of the oxide layer (the first oxide layer 311), and the oxide layer (the first oxide layer 311) is spaced between the nitride layer (the first nitride layer 312) and the substrate 100.
Further, a plurality of doped regions are formed in the substrate 100 between two adjacent gate structures 200, the doped regions are used as the source regions 410 or the drain regions 420, the source regions 410 and the drain regions 420 are arranged in the substrate 100 at intervals, the conductivity types of the source regions 410 and the drain regions 420 are the same, and the source regions 410 and the drain regions 420 are preferably formed after the sidewall protection layer is formed.
Referring to fig. 6, step S2 is executed: the metal layer 500 is formed by a first physical vapor deposition process, the exposed surfaces of the substrate 100, the first nitride layer 312 and the gate polysilicon layer 210 are covered by the metal layer 500, a part of the side surface (shown by a circular dotted frame in fig. 6) of the first oxide layer 311 between the first nitride layer 312 and the substrate 100 is exposed after the metal layer 500 is formed, and the metal layer 500 on the surface of the substrate 100 is in contact with the first oxide layer 311. In this embodiment, to reveal portions of the side surfaces of the first oxide layer 311 between the first nitride layer 312 and the substrate 100, the thickness of the metal layer 500 is required to be less than the thickness of the first oxide layer 311, and the thickness of the metal layer 500 may be 50 a-200 a, without being limited to this thickness range. In this embodiment, the material of the metal layer 500 is preferably nickel, and the self-aligned nickel silicide process is suitable for use when the feature size of the semiconductor device reaches 65nm or less, and because the coverage of nickel is poor, when the thickness of nickel is small (smaller than the thickness of the first oxide layer 311), nickel is not deposited on a part of the side surface of the first oxide layer 311 between the first nitride layer 312 and the substrate 100, so as to ensure that a part of the side surface of the first oxide layer 311 between the first nitride layer 312 and the substrate 100 is exposed after the metal layer 500 is formed, and the material of the metal layer 500 may also be a nickel platinum alloy, which is not limited to the above materials.
Referring to fig. 7, step S3 is executed: a plasma preclean process is used to etch away a portion of the exposed first oxide layer 311, so as to form a gap (shown by a circular dashed box in fig. 7) between the first nitride layer 312 and the substrate 100, and the gap exposes the surface of the substrate 100, and the gap isolates the first oxide layer 311 from the metal layer 500. The plasma precleaning process has high selectivity, and does not have a large influence on the metal layer 500 and the substrate 100 when the first oxide layer 311 is etched.
In this embodiment, the plasma precleaning process includes an etchant generation process, an etching process, and a sublimation process, wherein in the etchant generation process, the process temperature may be between 30 ℃ and 40 ℃, preferably, the process temperature is 35 ℃, and the etching gas includes NF 3 (Nitrogen trifluoride) and NH 3 (ammonia), NF 3 And NH 3 Introducing the mixed gas into a plasma precleaning reaction chamber, NF 3 And NH 3 The mixed gas is converted into NH under the action of plasma 4 F (ammonium fluoride) and NH 4 HF 2 (ammonium hydrogen fluoride); during the etching, NH 4 F and NH 4 HF 2 Condensation occurs on the surface of the device and preferentially reacts with the oxide, i.e., first oxide layer 311, to form solid (NH) 4 ) 2 SiF 6 (hexafluorosilicone ammonia) and liquid water; in the sublimation process, the process temperature is higher than 100 ℃, hydrogen is introduced into the plasma precleaning reaction chamber, the etchant generation process, the etching process and the sublimation process are carried out in the same plasma precleaning reaction chamber, the flowing hydrogen brings heat to the surface of the device, and the device is rapidly heated to be higher than 100 ℃ so as to enable the device to be solid (NH) 4 ) 2 SiF 6 Is decomposed into gaseous SiF 4 (silicon tetrafluoride), NH 3 (ammonia gas) and HF (hydrogen fluoride), and then the gas is pumped out by a vacuum pump, thereby achieving etching of the first oxide layer 311. In this embodiment, the width of the gap is greater than 5nm, and the width of the gap is a dimension along the left-right direction in fig. 7, which not only ensures that the gap can expose the substrate 100, but also ensures that the subsequently formed barrier layer can fill at least part of the gap.
Referring to fig. 8, step S4 is executed: a second physical vapor deposition process is used to form the barrier layer 600, and the barrier layer 600 covers the surface of the metal layer 500 and fills at least a portion of the gap. In this embodiment, it is preferable that the barrier layer 600 covers the metal layer 500 on the surface of the substrate 100 on three sides, that is, the barrier layer 600 covers not only the top surface of the metal layer 500 on the surface of the substrate 100, but also the side surface (shown by the circular dashed box in fig. 8) of the metal layer 500 on the surface of the substrate 100, so that the barrier layer 600 can not only isolate the metal layer 500 on the surface of the substrate 100 from the first oxide layer 311, but also prevent the metal layer 500 on the surface of the substrate 100 from flowing in the subsequent thermal annealing process, and isolate oxygen in the environment. In this embodiment, the material of the barrier layer 600 is preferably TiN (titanium nitride), which has good coverage and can fill the gap well, but is not limited to this material.
Referring to fig. 9, step S5 is executed: a thermal annealing process is performed to form metal silicide 510 in the substrate 100 on both sides of the gate structure 200. Specifically, a first thermal annealing process is performed to form metal silicide 510 in the substrate 100 on both sides of the gate structure 200, and simultaneously form metal silicide 510 on the top of the gate polysilicon layer 210, wherein the annealing temperature of the first thermal annealing process may be 240-330 ℃. Next, a wet etching process is used to remove the barrier layer and selectively remove the unreacted metal layer, i.e., the unreacted metal layer on the sidewall protection layer is removed, however, since the substrate 100 and a part of the metal layers on the gate polysilicon layer 210 do not completely react in the first thermal annealing process to form the metal silicide 510, when the unreacted metal layer on the sidewall protection layer is removed, the unreacted metal layers on the substrate 100 and the gate polysilicon layer 210 are simultaneously removed, and the metal silicide 510 is remained. In this embodiment, the etchant of the wet etching process includes sulfuric acid and ammonia water, and is not limited to the above etchant. Furthermore, a second thermal annealing process is performed to reduce the resistance of the metal silicide 510, wherein the metal silicide 510 is located on the surfaces of the source region 410, the drain region 420 and the gate polysilicon layer 210, and the annealing temperature of the second thermal annealing process is higher than that of the first thermal annealing process, so as to improve the thermal stability of the formed metal silicide 510, and in this embodiment, the metal silicide 510 is preferably nickel silicide.
In this embodiment, because the metal layer on the surface of the substrate contacts with the first oxide layer, which may result in the sidetracking of the metal silicide, a gap is formed by removing part of the first oxide layer, the gap plays a role in isolating the first oxide layer from the metal layer, and the barrier layer fills at least part of the gap to wrap the metal layer on the surface of the substrate with three sides, which also plays a role in isolating the first oxide layer from the metal layer, and prevents the metal layer from flowing in the thermal annealing process.
Referring to fig. 10, a passivation layer 700 is formed to cover the substrate 100, the gate structure 200 and the sidewall protection layer, and the passivation layer 700 may be silicon nitride and/or silicon oxide, but is not limited thereto. And forming a source plug 810, a drain plug 820 and a gate plug 830 in the passivation layer 700, wherein the source plug 810 penetrates through the passivation layer 700 and contacts the metal silicide 510 on the surface of the source region 410, the drain plug 820 penetrates through the passivation layer 700 and contacts the metal silicide 510 on the surface of the drain region 420, and the gate plug 830 penetrates through the passivation layer 700 and contacts the metal silicide 510 on the surface of the gate polysilicon layer 210.
The invention also provides a semiconductor device which is prepared by the preparation method of the semiconductor device, and the structure of the semiconductor device is not repeated herein, and the semiconductor device can be an MOS (metal oxide semiconductor) device, a memory device and the like.
In summary, in the semiconductor device and the manufacturing method thereof provided by the present invention, a plurality of gate structures are formed on a substrate, sidewall protection layers are formed on two sides of the gate structures, the sidewall protection layers include an oxide layer and a nitride layer, the oxide layer covers two sides of the gate structures and extends to cover a portion of the surface of the substrate, the nitride layer is located on the oxide layer and covers the side surfaces and the top surface of the oxide layer, and the oxide layer is spaced between the nitride layer and the substrate; forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, exposing partial side surfaces of the oxide layer between the nitride layer and the substrate, and contacting the metal layer on the surface of the substrate with the oxide layer; etching to remove part of the oxide layer to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer from the metal layer; forming a barrier layer to cover the metal layer and fill at least part of the gap so that three sides of the barrier layer cover the metal layer on the surface of the substrate; and performing a thermal annealing process to form metal silicide in the substrate on both sides of the gate structure. According to the invention, the metal layer on the surface of the substrate is contacted with the oxide layer to cause the sidetracking phenomenon of the metal silicide, namely, a gap is formed by removing part of the oxide layer, the gap plays a role of isolating the oxide layer from the metal layer, the barrier layer fills at least part of the gap to cover the metal layer on the surface of the substrate by three sides, the effect of isolating the oxide layer from the metal layer is also played, the metal layer is prevented from flowing in a thermal annealing process, and when the thermal annealing process is carried out, the metal layer is not contacted with the oxide layer to react to generate an unstable compound, so that the sidetracking phenomenon of the metal silicide is improved, the leakage current of a device is reduced, and the stability of the device is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a plurality of grid structures are formed on the substrate, side wall protection layers are formed on two sides of each grid structure, each side wall protection layer comprises an oxide layer and a nitride layer, the oxide layers cover two sides of each grid structure and extend to cover part of the surface of the substrate, the nitride layers are positioned on the oxide layers and cover the side surfaces and the top surfaces of the oxide layers, and the oxide layers are arranged between the nitride layers and the substrate at intervals;
forming a metal layer to cover the gate structure, the nitride layer and the surface of the substrate, and expose a part of the side surface of the oxide layer between the nitride layer and the substrate, wherein the metal layer on the surface of the substrate is in contact with the oxide layer;
etching to remove part of the oxide layer so as to form a gap between the nitride layer and the substrate, wherein the gap exposes the substrate to isolate the oxide layer and the metal layer;
forming a barrier layer to cover the metal layer and fill at least part of the gap so that the metal layer on the surface of the substrate is covered by three sides of the barrier layer; and the number of the first and second groups,
performing a thermal annealing process to form a metal silicide in the substrate on both sides of the gate structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the metal layer includes nickel.
3. The method of manufacturing a semiconductor device according to claim 2, wherein a thickness of the metal layer is less than a thickness of the oxide layer, and the thickness of the metal layer is 50A-200A.
4. The method for manufacturing a semiconductor device according to claim 2, wherein the metal layer is formed by a first physical vapor deposition process.
5. The method for manufacturing a semiconductor device according to claim 1, wherein a portion of the oxide layer is etched away by using a plasma precleaning process.
6. The method of manufacturing a semiconductor device according to claim 5, wherein an etching gas of the plasma preclean process includes NF 3 And NH 3 。
7. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the barrier layer comprises titanium nitride.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the barrier layer is formed by a second physical vapor deposition process.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the step of performing the thermal annealing process comprises:
performing a first thermal annealing process to form the metal silicide in the substrate on both sides of the gate structure;
removing the barrier layer and the unreacted metal layer; and the number of the first and second groups,
and performing a second thermal annealing process to reduce the resistance of the metal silicide.
10. A semiconductor device characterized by being produced by the production method for a semiconductor device according to any one of claims 1 to 9.
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