CN115080490B - SPI communication method and system with self-adaptive tuning - Google Patents

SPI communication method and system with self-adaptive tuning Download PDF

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Publication number
CN115080490B
CN115080490B CN202210687192.2A CN202210687192A CN115080490B CN 115080490 B CN115080490 B CN 115080490B CN 202210687192 A CN202210687192 A CN 202210687192A CN 115080490 B CN115080490 B CN 115080490B
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spi
mode
read
flash
write
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CN115080490A (en
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冯鹏斌
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses an SPI communication method and system with self-adaptive tuning, wherein the method comprises the following steps: defining an SPI working mode negotiation area in a flash partition hung on a chip on a server main device; after the server is electrified, a chip on the main equipment reads the model of the flash and judges whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model; if yes, starting the chip according to the recorded SPI read-write mode and SPI bus rate; otherwise, determining the read-write mode of the SPI through negotiation; then determining SPI bus rate through negotiation; and starting the chip according to the negotiated SPI read-write mode and the SPI bus rate. The system comprises: the SPI working mode negotiation zone setting module, the flash model reading module, the chip starting module, the SPI reading and writing mode determining module and the SPI bus rate determining module. Through the method and the device, the problem that the chip is started to fail due to the fact that firmware cannot be loaded successfully due to SPI signals can be effectively avoided, and the chip starting efficiency is improved.

Description

SPI communication method and system with self-adaptive tuning
Technical Field
The application relates to the technical field of SPI (Serial Peripheral Interface ) communication, in particular to an SPI communication method and system with self-adaptive tuning.
Background
With the rapid development of cloud computing applications, various chips participating in management and computing functions, such as BMC (Baseboard Management Controller ), PCH (Platform Controller Hub, platform controller center, intel corporation's integrated south bridge), switch chip, and expander chip, are increasing in artificial intelligence servers and heterogeneous servers. These chips usually need to plug-in flash to store their own FW program, where the FW (Firmware) program contains configuration information, driving information, and the like of the current chip. When the current chip is started each time, corresponding configuration information is required to be loaded in flash (flash memory, one of the memory chips), and whether the server can be started successfully or not and the starting time are affected by the communication interaction process. The chips and the flash usually adopt SPI communication modes, so that what SPI communication method is adopted is as follows: how to design the flow of loading FW from SPI flash is an important technical problem.
The current SPI communication method between the chip and flash can be seen in fig. 1. As can be seen from fig. 1, the current SPI communication method is generally: and after the Host is powered on, reading the model of the flash, and then loading data according to the SPI read-write mode and the speed written in the FW.
However, in the current SPI communication method between the chip and the flash, since the FW is a preset fixed SPI read/write mode and rate, when the server system is started for the first time, the board card does not debug the SPI signal, and when it is required to be compatible with flash of different types, the FW cannot be loaded successfully due to the SPI signal, and finally the startup is failed. Namely: the conventional SPI communication method between the chip and the flash has the defect that the failure rate of starting failure is high due to abnormal loading of FW.
Disclosure of Invention
The application provides an SPI communication method and system with self-adaptive tuning, and aims to solve the problem that the failure rate of startup failure is high due to FW loading abnormality in the SPI communication method in the prior art.
In order to solve the technical problems, the embodiment of the application discloses the following technical scheme:
an adaptive tuning SPI communication method, the SPI communication method comprising:
defining an SPI working mode negotiation area in a flash partition hung on a chip on a server main device, wherein the SPI working mode negotiation area is used for negotiating a read-write mode and an SPI bus rate of an SPI, the main device is a device hung on the server, and the flash is used for storing firmware of the chip;
after the server is electrified, a chip on the main equipment reads the model of the flash and judges whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model;
if yes, starting the chip according to the recorded SPI read-write mode and SPI bus rate;
if not, determining the read-write mode of the SPI through negotiation, wherein the read-write mode of the SPI comprises the following steps: standard SPI read-write mode, dual IO mode, and Quad IO mode;
after determining the read-write mode of the SPI, determining the SPI bus rate through negotiation;
and starting the chip according to the negotiated SPI read-write mode and the SPI bus rate.
Optionally, the method for determining the read-write mode of the SPI through negotiation comprises the following steps:
the method comprises the steps that a master device sends a first write instruction to an SPI working mode negotiation area, wherein the first write instruction is used for setting an SPI read-write mode to be a Quad IO mode;
judging whether correct data matched with the first write instruction and returned by the flash are received within a set time;
if yes, setting the Quad IO mode as an SPI working mode;
if not, the master device sends a second write instruction to the SPI working mode negotiation area, wherein the second write instruction is used for setting the SPI reading and writing mode to be a Dual IO mode in the SPI working mode negotiation area;
judging whether correct data matched with the second write instruction and returned by the flash are received within a set time;
if yes, setting the Dual IO mode as an SPI working mode;
if not, the master device sets the SPI read-write mode to the standard SPI read-write mode in the SPI working mode negotiation area, and sets the standard SPI read-write mode to the SPI working mode.
Optionally, the method for determining the SPI bus rate through negotiation comprises the following steps:
setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the main equipment;
sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area;
and setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
Optionally, according to the fixed difference, the default SPI bus rate is taken as a starting point, the SPI bus rate is sequentially increased in a step manner, and the maximum SPI bus rate in the current SPI communication process is determined according to a response result of the flash to the command sent by the SPI operating mode negotiation area, including:
summing the default SPI bus rate and the fixed difference value, calculating to obtain a first SPI bus rate, summing the first SPI bus rate and the fixed difference value, calculating to obtain a second SPI bus rate, and calculating by analogy to obtain an N-th bus rate which is less than or equal to the maximum SPI bus rate supported by the main equipment;
under a first SPI bus rate, the master device sends an instruction to the SPI working mode negotiation zone;
judging whether the main equipment receives correct data corresponding to the instruction returned by the flash within a set time;
if so, judging that the SPI bus can work at a first SPI bus rate, and sending an instruction to the SPI working mode negotiation area by the main equipment at a second SPI bus rate;
if not, judging that the SPI bus does not support the first SPI bus rate, and taking the default SPI bus rate as the maximum SPI bus rate in the current SPI communication process;
after the main equipment sends an instruction to the SPI working mode negotiation area at the second SPI bus rate, continuing to send the instruction to the SPI working mode negotiation area at the third SPI bus rate, and re-judging whether the main equipment receives correct data corresponding to the instruction returned by flash within a set time;
if so, judging that the SPI bus can work at the current SPI bus rate, and sending an instruction to the SPI working mode negotiation area by the main equipment at the next stepping SPI bus rate of the current SPI bus rate until the main equipment does not receive correct data corresponding to the instruction returned by flash within a set time;
if not, judging that the SPI bus does not support the current SPI bus rate, and taking the previous stepping SPI bus rate of the current SPI bus rate as the maximum SPI bus rate in the current SPI communication process.
Optionally, after the chip is started according to the negotiated SPI read/write mode and SPI read/write rate, the method further includes:
and storing the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in the firmware.
Optionally, storing the negotiated SPI read/write mode, SPI read/write rate, and corresponding flash model in the firmware, including:
judging whether a hardware link of the current firmware design stage is determined;
if so, recording the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in a flash table;
if not, recording the negotiated SPI read-write mode and the corresponding flash model in the flash table.
An adaptive tuning SPI communication system, the system comprising:
the SPI working mode negotiation zone setting module is used for defining an SPI working mode negotiation zone in a flash partition hung on a chip on the server main equipment, wherein the SPI working mode negotiation zone is used for negotiating a read-write mode and an SPI bus rate of the SPI, the main equipment is equipment hung with a flash in the server, and the flash is used for storing firmware of the chip;
the flash model reading module is arranged on the main equipment chip and is used for reading the model of the flash after the server is electrified and judging whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model;
the chip starting module is used for starting the chip according to the recorded SPI read-write mode and the recorded SPI bus rate when the SPI read-write mode and the recorded SPI bus rate are recorded in the flash of the current model;
the SPI read-write mode determining module is used for determining the SPI read-write mode through negotiation when the SPI read-write mode and the SPI bus rate are not recorded in the flash of the current model, and the SPI read-write mode comprises: standard SPI read-write mode, dual IO mode, and Quad IO mode;
the SPI bus rate determining module is used for determining the SPI bus rate through negotiation after determining the read-write mode of the SPI;
the chip starting module is also used for starting the chip according to the negotiated SPI read-write mode and SPI bus rate.
Optionally, the SPI read/write mode determining module includes:
the first write command sending unit is used for sending a first write command to the SPI working mode negotiation area, and the first write command is used for setting an SPI read-write mode to be a Quad IO mode;
the first judging unit is used for judging whether correct data which is returned by the flash and is matched with the first writing instruction is received within a set time;
the SPI working mode setting unit is used for setting the Quad IO mode into an SPI working mode when correct data which is returned by the flash and is matched with the first writing instruction is received in set time;
the second write command sending unit is used for sending a second write command to the SPI working mode negotiation area when correct data which is returned by the flash and is matched with the first write command is not received within a set time, and the second write command is used for setting an SPI read-write mode into a Dual IO mode in the SPI working mode negotiation area;
the second judging unit is used for judging whether correct data matched with the second writing instruction and returned by the flash are received within a set time;
the SPI working mode setting unit is further configured to set the Dual IO mode as an SPI working mode when correct data, which is returned by the flash and is matched with the second write instruction, is received in a set time;
the SPI working mode setting unit is further configured to set an SPI reading and writing mode to a standard SPI reading and writing mode in the SPI working mode negotiation area when correct data, which is returned by the flash and is matched with the second writing instruction, is not received within a set time, and set the standard SPI reading and writing mode to an SPI working mode.
Optionally, the SPI bus rate determination module includes:
the fixed difference value setting unit is used for setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the main equipment;
the maximum SPI bus rate determining unit is used for sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area;
and the SPI working bus rate determining unit is used for setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
Optionally, the system further comprises: and the storage module is used for storing the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in the firmware.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
the application provides a self-adaptive tuning SPI communication method, which comprises the steps of defining an SPI working mode negotiation area in a flash partition hung on a chip of a server main device, negotiating an SPI reading and writing mode and an SPI bus rate, then, after the server is powered on, reading the model of the flash by the chip, judging whether the SPI reading and writing mode and the SPI bus rate are recorded in the flash of the current model, if so, starting the chip according to the recorded SPI reading and writing mode and the SPI bus rate, otherwise, determining the SPI reading and writing mode firstly through negotiation, determining the SPI bus rate through negotiation, and finally, starting the chip according to the negotiated SPI reading and writing mode and the SPI bus rate. According to the embodiment, the SPI working mode negotiation area is defined in the flash partition, a basis is provided for subsequent negotiation of related content of the SPI working mode, and as long as the host equipment accesses the address space of the flash of the slave equipment in the area, the flash needs to respond to and feed back corresponding data after receiving the specific data sent by the host equipment, and the data are called correct data in the embodiment, so that whether negotiation is successful or not is judged, and the next step of continuous negotiation is facilitated. In this embodiment, the SPI read/write mode and the SPI bus rate are not fixedly preset in the firmware, but are adaptively selected according to the negotiation result in combination with a specific scenario, so as to ensure that the SPI is in an optimal working mode. Meanwhile, the negotiation determination is sequentially carried out on the SPI read-write mode and the SPI bus rate, so that the process of starting the firmware loaded from the SPI flash by the main equipment chip can be optimized, especially when the server system is started for the first time, the board card is not debugged with SPI signals and needs to be compatible with different types of flash, the problem that the chip is finally started to fail due to the fact that the firmware cannot be loaded successfully due to the SPI signals can be effectively avoided, and the chip starting failure rate is greatly reduced. By adopting the method in the embodiment, the problem that the chip is finally started to fail due to the fact that firmware cannot be loaded successfully due to SPI signals can be effectively avoided when the flash of different types is required to be compatible, and therefore the compatibility among the flash of different types is improved.
The application also provides an SPI communication system with self-adaptive tuning, which mainly comprises: the SPI working mode negotiation zone setting module, the flash model reading module, the chip starting module, the SPI reading and writing mode determining module and the SPI bus rate determining module. The SPI working mode negotiation zone setting module can define an SPI working mode negotiation zone in a flash zone hung on a chip of the server main equipment, is used for defining an SPI working mode negotiation zone in the flash zone hung on the chip of the server main equipment, and provides a foundation for the follow-up optimization of a starting flow of loading firmware from the SPI flash by the main equipment chip. And through the arrangement of the SPI read-write mode determining module and the SPI bus rate determining module, the optimal SPI read-write mode and the SPI bus rate which are suitable for the current environment are sequentially determined in a negotiation mode, so that the optimal SPI working mode is determined, and the SPI communication process of self-adaptive tuning is realized. Especially when the server system is started for the first time, the board card does not carry out SPI signal debugging and needs to be compatible with flash of different types, the problem that the chip is finally failed to start due to the fact that firmware cannot be loaded successfully due to SPI signals can be effectively avoided, and the chip starting failure rate is greatly reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a flow chart of an SPI communication method between a chip and a flash in the background art;
fig. 2 is a flow chart of an SPI communication method with adaptive tuning according to an embodiment of the present application;
fig. 3 is a schematic flow chart of comparing the recorded SPI read/write rate and the unrecorded SPI read/write rate in the embodiment of the present application;
fig. 4 is a schematic structural diagram of an SPI communication system with adaptive tuning according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions in the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the drawings.
Example 1
Referring to fig. 2, fig. 2 is a flow chart of an adaptive tuning SPI communication method according to an embodiment of the present application. As can be seen from fig. 2, the adaptive tuning SPI communication method in this embodiment mainly includes the following steps:
s1: and defining an SPI working mode negotiation area in a flash partition hung on a chip on the server main equipment, wherein the SPI working mode negotiation area is used for negotiating the read-write mode of the SPI and the SPI bus speed.
The server usually has various chips with multiple functions, and some chips participating in management and computing functions usually need to plug in flash, such as a BMC chip, a BIOS (Basic Input Output System ) chip, and the like. The plug-in flash is used for storing the firmware of the chip, namely FW. In this embodiment, a device with a flash hung in the server is defined as a master device, and a slave device corresponding to the master device is the flash. The SPI bus rate is also referred to as SPI bus read-write rate, or SPI read-write rate.
According to the embodiment, the SPI working mode negotiation area is defined in the flash partition, so that an address space is provided for the subsequent negotiation of the SPI reading and writing mode and the SPI bus speed, the smooth negotiation of the SPI working mode can be ensured, the SPI communication process is favorably optimized, and the chip starting efficiency is improved.
After defining an SPI operation mode negotiation area in the flash partition, step S2 is executed: after the server is electrified, a chip on the main equipment reads the model of the flash and judges whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model.
If the SPI read-write mode is recorded in the flash of the current model, executing the step S3: and starting the chip according to the recorded SPI read-write mode and the SPI bus rate.
That is, if the SPI read/write mode is already recorded in the flash of the current model, it is usually indicated that the system is not started for the first time or the flash of the current model has been started successfully on the system, and the situation that the server system fails to start for the first time due to the SPI communication is not existed, and the chip is started directly according to the recorded SPI read/write mode and the SPI bus rate.
If the SPI read-write mode is not recorded in the flash of the current model, executing the step S4: the read-write mode of the SPI is determined through negotiation. The read-write mode of the SPI comprises the following steps: standard SPI read/write mode, dual IO mode, and Quad IO mode. Quad IO mode is four-wire mode, dual IO mode is two-wire mode.
Specifically, step S4 includes the following procedure:
s41: the master device sends a first write command to the SPI working mode negotiation area, wherein the first write command is used for setting the SPI read-write mode to be a Quad IO mode.
S42: judging whether correct data matched with the first write instruction and returned by the flash is received within set time.
If the correct data matching the first write command returned by the flash is received within the set time, step S43 is executed: and setting the Quad IO mode as an SPI working mode.
If the main equipment successfully receives the data returned by the flash, the flash is proved to support the current Quad IO mode, and the subsequent reading and writing are finished by adopting the four-wire mode.
If the correct data matching the first write command returned by the flash is not received within the set time, step S44 is executed: the master device sends a second write command to the SPI working mode negotiation area, and the second write command is used for setting the SPI reading and writing mode to be a Dual IO mode in the SPI working mode negotiation area.
S45: judging whether correct data matched with the second write instruction and returned by the flash is received within set time.
If the correct data matching the second write command returned by the flash is received within the set time, step S46 is executed: the Dual IO mode is set to SPI mode.
If the correct data matching the second write command returned by the flash is not received within the set time, step S47 is executed: the master device sets the SPI read-write mode to the standard SPI read-write mode in the SPI working mode negotiation area, and sets the standard SPI read-write mode to the SPI working mode.
As can be seen from the above steps S41 to S47, in this embodiment, when the SPI read/write mode negotiation is performed, the SPI read/write mode first determines whether to be suitable for the Quad IO mode, then the Dual IO mode, and finally the standard SPI read/write mode. The judging sequence can select the read-write mode with the maximum bandwidth according to the sequence of the bandwidth from high to low, and is beneficial to improving the communication efficiency, so that the chip starting time is saved, and the chip starting efficiency is improved.
With continued reference to fig. 2, after determining the read/write mode of the SPI, step S5 is performed: the SPI bus rate is determined by negotiation. Specifically, step S5 includes the following processes:
s51: and setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the master device.
S52: and according to the fixed difference, sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area.
Specifically, step S52 further includes the following steps:
s521: and summing the default SPI bus rate and the fixed difference value, calculating to obtain a first SPI bus rate, summing the first SPI bus rate and the fixed difference value, calculating to obtain a second SPI bus rate, and calculating by analogy to obtain an N-th bus rate which is less than or equal to the maximum SPI bus rate supported by the main equipment.
S522: and at the first SPI bus rate, the master device sends an instruction to the SPI working mode negotiation zone.
S523: judging whether the main equipment receives correct data corresponding to the instruction returned by the flash within the set time.
If the host device receives the correct data corresponding to the instruction returned by the flash within the set time, step S524 is executed: the determination SPI bus can operate at a first SPI bus rate, and at a second SPI bus rate, the master device sends instructions to the SPI operating mode negotiation zone.
Otherwise, step S52 is performed: and judging that the SPI bus does not support the first SPI bus rate, and taking the default SPI bus rate as the maximum SPI bus rate in the current SPI communication process.
S525: and under the second SPI bus rate, after the main equipment sends the instruction to the SPI working mode negotiation area, continuing to send the instruction to the SPI working mode negotiation area under the third SPI bus rate, and re-judging whether the main equipment receives correct data returned by the flash and corresponding to the instruction within a set time.
If the host device receives the correct data corresponding to the instruction returned by the flash within the set time, step S526 is executed: the judging SPI bus can work at the current SPI bus rate, and the main device sends an instruction to the SPI working mode negotiation area at the next stepping SPI bus rate of the current SPI bus rate until the main device does not receive correct data corresponding to the instruction, which is returned by the flash, within a set time.
Otherwise, step S527 is executed: and judging that the SPI bus does not support the current SPI bus rate, and taking the previous stepping SPI bus rate of the current SPI bus rate as the maximum SPI bus rate in the current SPI communication process.
The maximum SPI bus rate is the maximum operating frequency that the SPI bus can support, and the master device is the Host. As can be seen from the above steps S521-S527, the process of determining the maximum SPI bus rate in this embodiment is as follows: at initial start-up, the SPI bus will operate at a default value or at a lower rate. The method comprises the steps that a master device increases the clock frequency on an SPI bus according to the maximum working frequency supported by the master device and a certain step, still sends an instruction to an SPI working mode negotiation partition, if a flash receives and analyzes corresponding data, returns one data to the master device, and after the master device correctly receives the data, the master device proves that the SPI bus can work at the frequency, the frequency is continuously increased, and higher-frequency negotiation actions are carried out; if the flash does not correctly analyze the upper data of the SPI bus or the main equipment does not receive the fed back data in a certain time, the bus is considered not to support the frequency. This is repeated until the maximum frequency that the master device can support is reached, thereby confirming the maximum operating frequency that the SPI bus can support.
After determining the maximum SPI bus rate in the current SPI communication process, step S53 is performed: and setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
As can be seen from the above steps S51 to S53, in this embodiment, when the SPI bus rate negotiation is performed, the maximum SPI bus rate in the current SPI communication process that the SPI bus can support is finally determined according to the order of the SPI bus rate from low to high, which is favorable for improving the SPI read/write efficiency, thereby improving the chip start efficiency.
With continued reference to fig. 2, after determining the SPI read/write mode and the SPI bus rate by negotiation, step S6 is performed: and starting the chip according to the negotiated SPI read-write mode and the SPI bus rate.
The following describes the SPI communication method procedure of adaptive tuning in this embodiment, taking a BMC chip as an example.
After the BMC is powered on, a default standard SPI read-write mode and a default working frequency (generally 25 MHz) are used first, the model of the flash is read, whether the flash has the recorded SPI read-write mode and SPI bus rate or not is inquired, if yes, configuration information is directly imported, and FW is loaded according to the optimal working mode. If the flash is not in the data, negotiation of SPI bus read-write Mode is carried out, the BMC firstly writes a command of the Quad IO Mode into the SPI working Mode negotiation partition of the flash, and if the flash supports the Mode and correctly feeds back the data and the BMC receives the data, the bus works at the Quad IO Mode; otherwise, the BMC rewrites the instruction switched to the Dual IO Mode, and if the instruction is supported, the bus is the Dual IO Mode; and if not, the SPI read-write mode is operated in the standard SPI read-write mode. After determining the bus read-write mode, the BMC negotiates the bus read-write rate, increases the SPI clock frequency step by step on the basis of a lower frequency, such as 33MHz, if the flash successfully receives data and the BMC obtains returned data, and proves that the bus can work under 33MHz, the bus frequency is continuously increased until the maximum working frequency supported by the BMC or the data is not fed back.
After the chip is started according to the negotiated SPI read/write mode and SPI read/write rate, the SPI communication method in this embodiment further includes step S7: and storing the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in firmware.
In the embodiment, the flash type, the corresponding SPI read-write mode and the corresponding SPI read-write rate can be stored in the firmware in a flash table mode, so that when the power-on is started next time, the power-on can be directly started according to the configured SPI read-write mode and the SPI read-write rate, the chip and the time required by starting the whole server system are reduced, and the starting efficiency is improved. The flash table mode is a mode of establishing a mapping relation table of flash and corresponding SPI read-write modes and SPI read-write rates.
Specifically, step S7 includes the following processes:
s71: it is determined whether the hardware link of the current firmware design phase has been determined.
The stage of the project can be initially known by judging the hardware link, the hardware link is uncertain in the current research and development test stage, and the later hardware link of the project is usually determined.
If the hardware link of the current firmware design stage has been determined, the description item is in the late stage, the SPI read/write rate has been basically determined, and step S72 is performed: and recording the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in a flash table.
If the hardware link of the current firmware design phase is not determined, step S73 is performed: recording the negotiated SPI read-write mode and the corresponding flash model in a flash table.
If the hardware link of the current firmware design stage is not determined, the item is in the early stage, if the expected target SPI read-write rate is not reached, the SPI read-write rate can be improved by adjusting the serial resistance and other modes in the link, that is to say, the SPI read-write rate is not determined at the stage, only the SPI read-write mode is recorded through the step S73, the SPI read-write rate is not recorded, negotiation of the SPI read-write rate is not needed, and therefore, the flow is saved, and the starting efficiency of the chip is improved.
As can be seen from fig. 3, in this embodiment, there are two sets of processes 1,2 and 3,4, where 1,2 is that the SPI read/write rate of the flash is not recorded in the flash table, corresponding to the case of step S73, and 3,4 is that the SPI read/write rate of the flash is recorded in the flash table, corresponding to the case of step S72.
Example two
Referring to fig. 4 on the basis of the embodiments shown in fig. 2 and fig. 3, fig. 4 is a schematic structural diagram of an adaptive tuning SPI communication system according to an embodiment of the present application. As can be seen from fig. 4, the adaptive tuning SPI communication system in this embodiment mainly includes: the SPI working mode negotiation zone setting module, the flash model reading module, the chip starting module, the SPI reading and writing mode determining module and the SPI bus rate determining module.
The SPI working mode negotiation zone setting module is used for defining an SPI working mode negotiation zone in a flash partition hung on a chip on the server main equipment, wherein the SPI working mode negotiation zone is used for negotiating a read-write mode and an SPI bus rate of an SPI, the main equipment is equipment hung with a flash in the server, and the flash is used for storing firmware of the chip; the flash model reading module is arranged on the main equipment chip and is used for reading the model of the flash after the server is electrified and judging whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model; the chip starting module is used for starting the chip according to the recorded SPI read-write mode and the recorded SPI bus rate when the SPI read-write mode and the recorded SPI bus rate are recorded in the flash of the current model; the SPI read-write mode determining module is used for determining the SPI read-write mode through negotiation when the SPI read-write mode and the SPI bus rate are not recorded in the flash of the current model, wherein the SPI read-write mode comprises: standard SPI read-write mode, dual IO mode, and Quad IO mode; the SPI bus rate determining module is used for determining the SPI bus rate through negotiation after determining the read-write mode of the SPI; the chip starting module is also used for starting the chip according to the negotiated SPI read-write mode and the SPI bus rate.
Further, the SPI read/write mode determining module includes: the SPI working mode setting device comprises a first writing instruction sending unit, a first judging unit, an SPI working mode setting unit, a second writing instruction sending unit and a second judging unit.
The first write command sending unit is used for sending a first write command to the SPI working mode negotiation area, and the first write command is used for setting the SPI read-write mode to be a Quad IO mode; the first judging unit is used for judging whether correct data which is returned by the flash and is matched with the first writing instruction is received within a set time; the SPI working mode setting unit is used for setting the Quad IO mode into an SPI working mode when correct data which is returned by the flash and is matched with the first writing instruction is received in set time; the second write instruction sending unit is used for sending a second write instruction to the SPI working mode negotiation area when correct data which is returned by the flash and is matched with the first write instruction is not received within a set time, and the second write instruction is used for setting the SPI reading and writing mode to be a Dual IO mode in the SPI working mode negotiation area; the second judging unit is used for judging whether correct data matched with the second writing instruction and returned by the flash is received within a set time; the SPI working mode setting unit is also used for setting the Dual IO mode into an SPI working mode when correct data which is returned by the flash and is matched with the second writing instruction is received in set time; the SPI working mode setting unit is further used for setting the SPI reading and writing mode to be a standard SPI reading and writing mode in the SPI working mode negotiation area when correct data which is returned by the flash and is matched with the second writing instruction is not received within a set time, and setting the standard SPI reading and writing mode to be the SPI working mode.
The SPI bus rate determining module comprises: the SPI working bus speed determining device comprises a fixed difference value setting unit, a maximum SPI bus speed determining unit and an SPI working bus speed determining unit. The fixed difference value setting unit is used for setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the main equipment; the maximum SPI bus rate determining unit is used for sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area; and the SPI working bus rate determining unit is used for setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
Further, the system also comprises a storage module for storing the negotiated SPI read-write mode, the negotiated SPI read-write speed and the corresponding flash model in the firmware.
The storage module further comprises: and the third judging unit and the recording unit. The third judging unit is used for judging whether the hardware link of the current firmware design stage is determined. The recording unit is used for recording the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in the flash table if the hardware link of the current firmware design stage is determined, or recording the negotiated SPI read-write mode and the corresponding flash model in the flash table if the hardware link of the current firmware design stage is not determined.
The parts of this embodiment that are not described in detail can be referred to the embodiment shown in fig. 2 and 3, and reference may be made to the two embodiments, which are not described in detail herein.
The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. An adaptive tuning SPI communication method is characterized by comprising the following steps:
defining an SPI working mode negotiation area in a flash partition hung on a chip on a server main device, wherein the SPI working mode negotiation area is used for negotiating a read-write mode and an SPI bus rate of an SPI, the main device is a device hung on the server, and the flash is used for storing firmware of the chip;
after the server is electrified, a chip on the main equipment reads the model of the flash and judges whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model;
if yes, starting the chip according to the recorded SPI read-write mode and SPI bus rate;
if not, determining the read-write mode of the SPI through negotiation, wherein the read-write mode of the SPI comprises the following steps: standard SPI read-write mode, dual IO mode, and Quad IO mode;
after determining the read-write mode of the SPI, determining the SPI bus rate through negotiation;
starting the chip according to the negotiated SPI read-write mode and SPI bus rate;
the method for determining the read-write mode of the SPI through negotiation comprises the following steps:
the method comprises the steps that a master device sends a first write instruction to an SPI working mode negotiation area, wherein the first write instruction is used for setting an SPI read-write mode to be a Quad IO mode;
judging whether correct data matched with the first write instruction and returned by the flash are received within a set time;
if yes, setting the Quad IO mode as an SPI working mode;
if not, the master device sends a second write instruction to the SPI working mode negotiation area, wherein the second write instruction is used for setting the SPI reading and writing mode to be a Dual IO mode in the SPI working mode negotiation area;
judging whether correct data matched with the second write instruction and returned by the flash are received within a set time;
if yes, setting the Dual IO mode as an SPI working mode;
if not, the master device sets the SPI read-write mode as a standard SPI read-write mode in the SPI working mode negotiation area, and sets the standard SPI read-write mode as an SPI working mode;
a method for determining SPI bus rate through negotiation, comprising:
setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the main equipment;
sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area;
and setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
2. The adaptive tuning SPI communication method according to claim 1, wherein the method for sequentially increasing the SPI bus rate in a step-wise manner starting from the default SPI bus rate according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI operation mode negotiation zone, comprises:
summing the default SPI bus rate and the fixed difference value, calculating to obtain a first SPI bus rate, summing the first SPI bus rate and the fixed difference value, calculating to obtain a second SPI bus rate, and calculating by analogy to obtain an N-th bus rate which is less than or equal to the maximum SPI bus rate supported by the main equipment;
under a first SPI bus rate, the master device sends an instruction to the SPI working mode negotiation zone;
judging whether the main equipment receives correct data corresponding to the instruction returned by the flash within a set time;
if so, judging that the SPI bus can work at a first SPI bus rate, and sending an instruction to the SPI working mode negotiation area by the main equipment at a second SPI bus rate;
if not, judging that the SPI bus does not support the first SPI bus rate, and taking the default SPI bus rate as the maximum SPI bus rate in the current SPI communication process;
after the main equipment sends an instruction to the SPI working mode negotiation area at the second SPI bus rate, continuing to send the instruction to the SPI working mode negotiation area at the third SPI bus rate, and re-judging whether the main equipment receives correct data corresponding to the instruction returned by flash within a set time;
if so, judging that the SPI bus can work at the current SPI bus rate, and sending an instruction to the SPI working mode negotiation area by the main equipment at the next stepping SPI bus rate of the current SPI bus rate until the main equipment does not receive correct data corresponding to the instruction returned by flash within a set time;
if not, judging that the SPI bus does not support the current SPI bus rate, and taking the previous stepping SPI bus rate of the current SPI bus rate as the maximum SPI bus rate in the current SPI communication process.
3. An adaptive tuning SPI communication method according to claim 1 or 2, wherein after the chip is started according to the negotiated SPI read/write mode and SPI read/write rate, the method further comprises:
and storing the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in the firmware.
4. The adaptive tuning SPI communication method according to claim 3, wherein storing the negotiated SPI read/write mode, SPI read/write rate, and corresponding flash model in the firmware comprises:
judging whether a hardware link of the current firmware design stage is determined;
if yes, recording the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in a flash table;
if not, recording the negotiated SPI read-write mode and the corresponding flash model in the flash table.
5. An adaptive tuning SPI communication system, said system comprising:
the SPI working mode negotiation zone setting module is used for defining an SPI working mode negotiation zone in a flash partition hung on a chip on the server main equipment, wherein the SPI working mode negotiation zone is used for negotiating a read-write mode and an SPI bus rate of the SPI, the main equipment is equipment hung with a flash in the server, and the flash is used for storing firmware of the chip;
the flash model reading module is arranged on the main equipment chip and is used for reading the model of the flash after the server is electrified and judging whether the SPI read-write mode and the SPI bus rate are recorded in the flash of the current model;
the chip starting module is used for starting the chip according to the recorded SPI read-write mode and the recorded SPI bus rate when the SPI read-write mode and the recorded SPI bus rate are recorded in the flash of the current model;
the SPI read-write mode determining module is used for determining the SPI read-write mode through negotiation when the SPI read-write mode and the SPI bus rate are not recorded in the flash of the current model, and the SPI read-write mode comprises: standard SPI read-write mode, dual IO mode, and Quad IO mode;
the SPI bus rate determining module is used for determining the SPI bus rate through negotiation after determining the read-write mode of the SPI;
the chip starting module is also used for starting the chip according to the negotiated SPI read-write mode and SPI bus rate;
the SPI read-write mode determining module comprises:
the first write command sending unit is used for sending a first write command to the SPI working mode negotiation area, and the first write command is used for setting an SPI read-write mode to be a Quad IO mode;
the first judging unit is used for judging whether correct data which is returned by the flash and is matched with the first writing instruction is received within a set time;
the SPI working mode setting unit is used for setting the Quad IO mode into an SPI working mode when correct data which is returned by the flash and is matched with the first writing instruction is received in set time;
the second write command sending unit is used for sending a second write command to the SPI working mode negotiation area when correct data which is returned by the flash and is matched with the first write command is not received within a set time, and the second write command is used for setting an SPI read-write mode into a Dual IO mode in the SPI working mode negotiation area;
the second judging unit is used for judging whether correct data matched with the second writing instruction and returned by the flash are received within a set time;
the SPI working mode setting unit is further configured to set the Dual IO mode as an SPI working mode when correct data, which is returned by the flash and is matched with the second write instruction, is received in a set time;
the SPI working mode setting unit is further configured to set an SPI reading and writing mode to a standard SPI reading and writing mode in the SPI working mode negotiation area when correct data, which is returned by the flash and is matched with the second writing instruction, is not received within a set time, and set the standard SPI reading and writing mode to an SPI working mode;
the SPI bus rate determining module comprises:
the fixed difference value setting unit is used for setting a fixed difference value according to the current default SPI bus rate and the maximum SPI bus rate supported by the main equipment;
the maximum SPI bus rate determining unit is used for sequentially increasing the SPI bus rate in a stepping mode by taking the default SPI bus rate as a starting point according to the fixed difference value, and determining the maximum SPI bus rate in the current SPI communication process according to the response result of the flash to the command sent by the SPI working mode negotiation area;
and the SPI working bus rate determining unit is used for setting the maximum SPI bus rate in the current SPI communication process as the SPI working bus rate.
6. An adaptive tuning SPI communication system according to claim 5, further comprising: and the storage module is used for storing the negotiated SPI read-write mode, the negotiated SPI read-write rate and the corresponding flash model in the firmware.
CN202210687192.2A 2022-06-17 2022-06-17 SPI communication method and system with self-adaptive tuning Active CN115080490B (en)

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