CN115080453A - Address calculation array management method and system - Google Patents
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- 238000007726 management method Methods 0.000 title claims abstract description 28
- 239000011159 matrix material Substances 0.000 claims description 27
- 238000013507 mapping Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
The invention discloses an address calculation array management method and system. The address calculation array management method is used for DMA constant addressing or positive/negative address block crossing addressing, can calculate an address, a byte number occupied by a block address and a residual effective byte number in the boundary of the block address at the next addressing by using an address array mode according to five elements of an input initial address ini _ addr, a block address boundary size, a jump step size distance, an access address length, and an intra-block residual address space i _ dssize _ left (a residual space in a first size), and is used for the next addressing.
Description
Technical Field
The invention relates to an address calculation array management method and system, and relates to the technical field of access addresses.
Background
With the development and application of DMA technology, high performance DMA has supported linear addressing, constant addressing (FIFO format), and forward addressing across consecutive address jumps to satisfy flexible mapping of data space. In the case of constant addressing and forward skip mode, because the address of the access space is discontinuous (in the case of a negative skip mode or a positive skip mode), after the boundary of each address block (a continuous block of address access space) is accessed, the next address block is accessed in a span manner.
However, when the address offset determination is performed by the existing computer technology, the address offset determination is continuous addresses, and there is no calculation function of address jump (positive and negative). For example, intel mainly describes address offset determination, which is a memory address mapping manner, and the panasonic apparatus determines whether an address overflows by using a continuous start address and end address interval, and none of the three methods supports discontinuous address calculation and does not support skip address calculation across size.
Meanwhile, on the basis of no complex address calculation (positive jump and negative jump), the address and the block address occupied byte number and the residual effective byte number information in the boundary of the block address at the next addressing can not be calculated, large-range address array settlement is not supported, the address array comparison can not be converted into a plurality of groups of linear flow processing, and a hardware circuit converted into a high time sequence can not be supported. That is, at the present stage, there is no complicated address calculation function, and the positive jump address and the negative jump address, etc. cannot be calculated.
In view of the above, there is a need to provide an improvement to the existing address calculation array management method to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide an address calculation array management method which is used for DMA constant addressing or positive/negative address block crossing addressing, can calculate an address, block address occupation and residual effective byte number in a block address boundary when next addressing by using an address array mode according to five elements of an input initial address ini _ addr, a block address boundary size, a jump step size distance, an access address length and an intra-block residual address space i _ dssize _ left, and is used for using next addressing.
In order to achieve the above object, the present invention provides an address calculation array management method for implementing DMA constant addressing or positive/negative address block addressing, comprising the following steps:
s1, selecting/inputting any point in the access address as an initial address ini _ addr;
s2, defining block address boundary size, jump step size distance, access address length, and residual byte length i _ dssize _ left addressing element in block address boundary size;
s3, taking the initial address ini _ addr as an origin, filling according to the block address boundary size and the residual byte length i _ dssize _ left in the block address boundary size, and dividing the access address length until all the access address length are mapped after the block address boundary size is crossed;
s4, calculating the next mapping start address, the occupied length in the block address boundary size and the residual address length in the block address boundary size according to the form of the address array adopted by the S3;
and S5, taking the next mapping start address obtained by calculation in the S4 as the start address ini _ addr, repeating the steps S2 to S4, carrying out next addressing until the addressing of the whole access address length is completed, and calculating and outputting a final address o _ D _ addr, a residual length o _ dssize _ left in the final block address boundary size and an occupied length o _ left _ len in the final block address boundary size.
As a further improvement of the present invention, the S3 specifically is: and taking the initial address ini _ addr as an origin, filling according to the block address boundary size, according to the residual byte length i _ dssize _ left in the block address boundary size, and crossing the block address boundary size, splitting the access address length, wherein after the access address length is split according to the block address boundary size, the access address length is increased by one block address boundary size, and then increased by one jump step size distance until all the access address lengths are mapped.
As a further improvement of the present invention, in S4, the address array is used to indicate the next mapping start address, and the next mapping start address is indicated as ini _ addr + length + ((length + size-i _ dssize _ left)/size) × distance.
As a further improvement of the present invention, in S4, the occupied length in the block address boundary size is represented by the address array, and the occupied length in the block address boundary size is represented by (length + size-i _ dssize _ left)% size.
As a further improvement of the present invention, in S4, the address array is used to indicate the remaining address length in the block address boundary size, and the remaining address length in the block address boundary size is indicated as size- (length + size-i _ dssize _ left)% size.
As a further improvement of the present invention, in S4, each matrix element in the address array is N size, N sequentially increases in the address array, the value of N is obtained by comparing the values of each matrix element N size, and then the mapped start address of the next mapping is obtained by calculation; s4 further includes comparing N matrix elements N × size in the same column in each clock cycle to obtain a matching element, where the matching element is the first matrix element that satisfies i _ dssize _ left + N × size > length, and i _ dssize _ left is the remaining byte length in the block address boundary size.
As a further improvement of the present invention, in S5, the final address o _ D _ addr = ini _ addr + S _ addr _ inc _x-S _ size _x + i _ dssize _ left; wherein S _ addr _ inc _xis the sum of the block address boundary size and the jump step size distance accumulated in the address array; s _ size _ x is the sum of the block address boundary size lengths accumulated in the address array; i _ dssize _ left is the remaining byte length within the block address boundary size.
As a further improvement of the present invention, in S5, the remaining length o _ dssize _ left = S _ size _ x + i _ dssize _ left-length within the final block address boundary size; wherein S _ size _ x is the sum of the block address boundary size lengths accumulated in the address array, and i _ dssize _ left is the remaining byte length within the block address boundary size.
As a further improvement of the present invention, in S5, the occupied length o _ left _ len = size-o _ dssize _ left within the final block address boundary size.
In order to achieve the above object, the present invention further provides an address calculation array management system, which includes a control unit, where the control unit is configured to execute the foregoing address calculation array management method to implement calculation and addressing of jump addresses.
The invention has the beneficial effects that:
1. the address, the block address occupied byte number and the residual effective byte number in the block address boundary when the next addressing is carried out can be calculated according to five elements of the input initial address ini _ addr, the block address boundary size and the jump step size distance, namely the access address length and the residual byte length i _ dssize _ left in the block address boundary size, so that the address calculation of jump addressing is realized;
2. division and remainder operations used when the size crosses a plurality of block address boundaries are avoided through the form of an address array;
3. by comparing the matrix elements of the address array column by column, the hardware time sequence and the logic area are optimized; and a pipeline column-by-column element comparison method is adopted to lock the first element for comparison and matching, and the element participates in the final address calculation, so that good repeatability and flexibility are achieved.
Drawings
FIG. 1 is a flow chart of the address calculation array management method of the present invention.
FIG. 2 is a schematic diagram of the compute array for the address array of S4 in FIG. 1.
Fig. 3 is a schematic diagram of the processing flow of the address array in S4 in fig. 1.
Fig. 4 is a schematic diagram of forward jump address mapping in embodiment 1 of the present invention.
Fig. 5 is a diagram illustrating mapping of constant addressing addresses in embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Referring to FIG. 1, the present invention discloses an address calculation array management method for implementing DMA constant addressing or positive/negative address block addressing. The address calculation array management method comprises the following steps:
s1, selecting/inputting any point in the access address as an initial address ini _ addr;
s2, defining block address boundary size, jump step size distance, access address length, and residual byte length i _ dssize _ left addressing element in block address boundary size;
s3, with the start address ini _ addr as an origin, according to the block address boundary size, filling according to the remaining byte length i _ dssize _ left in the block address boundary size, and crossing the block address boundary size, and then splitting the access address length until all the access address lengths are mapped;
s4, calculating the next mapping start address, the occupied length in the block address boundary size and the residual address length in the block address boundary size according to the form of the address array adopted by the S3;
and S5, taking the next mapping start address obtained by calculation in the S4 as the start address ini _ addr, repeating the steps S2 to S4, carrying out next addressing until the addressing of the whole access address length is completed, and calculating and outputting a final address o _ D _ addr, a residual length o _ dssize _ left in the final block address boundary size and an occupied length o _ left _ len in the final block address boundary size.
Specifically, any point in the access address is selected/input as an initial address ini _ addr; defining a block address boundary size, a jump step size distance, an access address length and a residual byte length i _ dssize _ left in the block address boundary size, wherein the residual byte length i _ dssize _ left in the block address boundary size is a residual space in the first block address boundary size; and inputting the information of more than 5 of the initial address ini _ addr, the block address boundary size, the jump step size distance, the access address length and the residual byte length i _ dsize _ left in the block address boundary size as initial elements.
Further, with the start address ini _ addr as an origin, according to the block address boundary size, filling according to the residual byte length i _ dssize _ left in the block address boundary size and crossing the block address boundary size, splitting the access address length, wherein each time the access address length is split according to the block address boundary size, the access address length is increased by one block address boundary size and then increased by one jump step distance until all the access address lengths are mapped.
Representing the next mapping start address, the occupied length in the block address boundary size and the remaining address length in the block address boundary size by using an address array, wherein the next mapping start address is represented as ini _ addr + length + ((length + size-i _ dssize _ left)/size) × distance; the occupied length in the block address boundary size is represented as (length + size-i _ dsize _ left)% size; the remaining address length within the block address boundary size is denoted size- (length + size-i _ dssize _ left)% size.
Specifically, the method for representing the next mapping start address, the occupied length in the block address boundary size and the remaining address length in the block address boundary size by using the address array can effectively avoid the algorithm implemented in the prior art by using the remainder and division method, and in fact, in terms of the hardware implementation of the chip, because the ranges supported by the access address length, the block address boundary size and the jump step distance are large, if the calculation method of the remainder and division method is adopted in the calculation, the bottleneck of more logic resources and poorer time sequence can be generated, and in order to meet the requirement of high-performance chip hardware, the algorithm of the remainder and division method is converted into the form of the address array.
Referring to fig. 2, in the present invention, each matrix element in an address array is nxsize, N sequentially increases in the address array, the value of N is obtained by comparing the values of each matrix element nxsize, and then the start address of the next mapping is obtained by calculation. Furthermore, defining the address array, each column is provided with X elements, respectively calculating the length and jump address of occupied bytes containing 1 size to X sizes, calculating the size X and addr _ inc X of each matrix element as the calculation result of the last minimum element (i.e. the first element in the column corresponding to the matrix array), avoiding multiplication by adopting an accumulation form, comparing the access address length with each matrix element in the matrix, and locking the corresponding matrix element, thereby obtaining the block address boundary size and address increment value spanned by the current access address length. However, since there will be a shift of the occupancy length i _ dsize _ left within the block address boundary size at the input resulting in a shift of the final address, the occupancy length i _ dsize _ left within the block address boundary size needs to be considered when locking array elements. In fact, how to lock array elements is one of the important improvements of the present invention, the lock array element comparison algorithm is as follows: firstly, judging whether the occupied length i _ dsize _ left + N × size in the block address boundary size is larger than the access address length, and comparing each matrix element N × size in the address array according to columns to obtain matched elements; the matching element is the first element which is larger than the length of the current access address.
Specifically, the matching element is a matrix element in the first address array that matches the calculation formula i _ dssize _ left + N × size > length. In the address array, the matrix elements in each cell refer to S _ size _ x (cumulative sum of block address boundary sizes) and S _ addr _ inc _ x (cumulative sum of block address boundary sizes and jump step distance lengths); furthermore, each clock cycle compares X matrix elements in one column, and the next clock cycle compares X matrix elements in the next column, sequentially increasing in number, and performing pipelined comparison. It should be noted that this process is to find the matching elements, i.e. the first matrix elements corresponding to i _ dssize _ left + N × size > length, and the subsequent matrix elements corresponding to this equation are ignored and are not of interest.
Furthermore, because the timing sequence and the area occupation of the chip are considered, each address array needs to be divided into a plurality of columns, when matrix elements in the address array are compared, X elements in one column need to be compared under each clock, the next clock matches X elements in the second column, and when five addressing elements of the input start address ini _ addr, the block address boundary size, the jump step size distance, the access address length, and the residual byte length i _ dssize _ left in the block address boundary size are refreshed, the column-by-column comparison is started. It should be noted that, in the drawings of the present invention, only 16 matrix elements per column are taken as an example for illustration; of course, in other embodiments of the present invention, the number of matrix elements in each column may also be selected according to actual needs, which is not limited herein.
After the corresponding elements are matched, outputting a final address o _ D _ addr, a residual length o _ dssize _ left in the final block address boundary size and an occupied length o _ left _ len in the final block address boundary size: wherein the content of the first and second substances,
the final address o _ D _ addr = ini _ addr + S _ addr _ inc _ x-S _ size _ x + i _ dssize _ left;
wherein S _ addr _ inc _xis the sum of the block address boundary size and the jump step size distance accumulated in the address array; s _ size _ x is the sum of the block address boundary size lengths accumulated in the address array; i _ dssize _ left is the remaining byte length within the block address boundary size.
The remaining length o _ dssize _ left = S _ size _ x + i _ dssize _ left-length within the final block address boundary size;
wherein S _ size _ x is the sum of the block address boundary size lengths accumulated in the address array, and i _ dssize _ left is the remaining byte length within the block address boundary size.
The occupied length within the final block address boundary size o _ left _ len = size-o _ dssize _ left.
The following description section will describe in detail the address calculation array management method of the present invention by way of specific embodiments.
Example 1
As shown in fig. 4, with the DMA address mapping requirement as a background, taking a forward jump address mapping manner as an example, address mapping between S _ addr and D _ addr is performed. Specifically, in this embodiment, taking the access address length as an example, the forward jump mapping is to jump the address according to the block address boundary size, that is, calculate from the start address ini _ addr, and jump forward by one jump step distance after the block address boundary size is continuously transmitted. The address calculation formula for the next data access is: ini _ addr + length + ((length + size-i _ dssize _ left)/size) × distance; the calculation formula of the byte number occupied by the block address is as follows: (length + size-i _ dssize _ left)% size; the calculation formula of the residual effective byte number in the boundary of the block address is as follows: size- (length + size-i _ dssize _ left)% size.
Specifically, the start address ini _ addr is defined as 0X0, the occupied Byte in the block address boundary size is 0, that is, the remaining Byte length i _ dssize _ left in the block address boundary size is 4Byte, the block address boundary size =4Byte, the jump step distance =8Btype, the access address length =10Byte, that is, the source is the forward address jump mode, and the destination is linear addressing. The partition is performed by taking the block address boundary size as the size, (length + size-i _ dssize _ left)/size =2, that is, the distance spans two jumps, the start address of the next data access is calculated to be ini _ addr + length +2 × distance =0x1a, the occupied Byte number in the block address boundary size is (length + size-i _ dssize _ left)% size =2Byte, the remaining Byte number in the block address boundary size is size- (length + size-i _ dssize _ size)% size =2Byte, and the result of this calculation can be used as the input of the next calculation.
Example 2
As described in fig. 5, the source S _ addr is a negative address jump and the destination D _ addr is a linear address, taking constant addressing (negative address jump) as an example. Since jump step size distance is negative, constant addressing is a case for negative addresses, i.e. block address boundary size = -distance.
Specifically, a start address ini _ addr is defined as 0x0, a block address boundary size =4Byte, a remaining Byte length i _ dssize _ left in the block address boundary size is defined as 4Byte, a jump step distance = -4Byte, an access address length h =10Byte, and the size is cut by using the block address boundary size, (length + size-i _ dssize _ left)/size =2, that is, the size is calculated across two jump step distances, the start address of the next data access is calculated as ini _ addr + length-2 × size =0x2, the occupied Byte number in the block address boundary size is (length + size-i _ dssize _ left)% size =2Byte, and the remaining Byte number in the block address boundary size is calculated as size- (length + size-i _ size)% size _ size =2 Byte.
The invention also provides an address calculation array management system which comprises a control unit, and the control unit can be used for executing the address calculation array management method provided by the invention to realize the calculation and addressing of jump addresses.
In summary, the address calculation array management method of the present invention can calculate the address, the number of bytes occupied by the block address, and the number of remaining effective bytes in the boundary of the block address at the next addressing time according to the five elements, i _ addr, block address boundary size, and jump step distance, of the input start address ini _ addr, block address boundary size, and jump step distance, to access address length h, and i _ dssize _ left (remaining space in the first size), so as to implement address calculation of jump addressing; meanwhile, division and remainder operations used when the size of a plurality of block address boundaries is crossed in calculation are avoided in the form of address arrays; the matrix elements of the address array are compared column by column, so that the hardware time sequence and the logic area are optimized; and a pipeline column-by-column element comparison method is adopted to lock the first element for comparison and matching, and the element participates in the final address calculation, so that good repeatability and flexibility are achieved.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. An address calculation array management method for implementing DMA constant addressing or positive/negative address block addressing, comprising the steps of:
s1, selecting/inputting any point in the access address as an initial address ini _ addr;
s2, defining four addressing elements of block address boundary size, jump step distance, access address length, and residual byte length i _ dssize _ left in block address boundary size;
s3, taking the initial address ini _ addr as an origin, filling according to the block address boundary size and the residual byte length i _ dssize _ left in the block address boundary size, and dividing the access address length until all the access address length are mapped after the block address boundary size is crossed;
s4, calculating the next mapping start address, the occupied length in the block address boundary size and the residual address length in the block address boundary size according to the form of the address array adopted by the S3;
and S5, taking the next mapping start address obtained by calculation in the S4 as the start address ini _ addr, repeating the steps S2 to S4, carrying out next addressing until the addressing of the whole access address length is completed, and calculating and outputting a final address o _ D _ addr, a residual length o _ dssize _ left in the final block address boundary size and an occupied length o _ left _ len in the final block address boundary size.
2. The address calculation array management method according to claim 1, wherein the S3 is specifically: and taking the initial address ini _ addr as an origin, filling according to the block address boundary size, according to the residual byte length i _ dssize _ left in the block address boundary size, and crossing the block address boundary size, splitting the access address length, wherein after the access address length is split according to the block address boundary size, the access address length is increased by one block address boundary size, and then increased by one jump step size distance until all the access address lengths are mapped.
3. The address calculation array management method according to claim 1, characterized in that: in S4, the address array is used to indicate the next mapping start address, where the next mapping start address is denoted by ini _ addr + length + ((length + size-i _ dssize _ left)/size) × distance.
4. The address calculation array management method according to claim 1, wherein: in S4, the address array is used to indicate the occupied length in the block address boundary size, where the occupied length in the block address boundary size is indicated as (length + size-i _ dsize _ left)% size.
5. The address calculation array management method according to claim 1, wherein: in S4, the address array is used to indicate the remaining address length in the block address boundary size, where the remaining address length in the block address boundary size is indicated as size- (length + size-i _ dssize _ left)% size.
6. The address calculation array management method according to claim 1, characterized in that: in S4, each matrix element in the address array is N size, N sequentially increases in the address array, the value of N is obtained by comparing the values of each matrix element N size, and then the next mapping start address is obtained by calculation; s4 further includes comparing N matrix elements N × size in the same column in each clock cycle to obtain a matching element, where the matching element is the first matrix element that satisfies i _ dssize _ left + N × size > length, and i _ dssize _ left is the remaining byte length in the block address boundary size.
7. The address calculation array management method of claim 6, wherein: in the S5, the final address o _ D _ addr = ini _ addr + S _ addr _ inc _x-S _ size _ x + i _ dssize _ left; wherein S _ addr _ inc _xis the sum of the block address boundary size and the jump step length distance accumulated in the address array; s _ size _ x is the sum of the block address boundary size lengths accumulated in the address array; i _ dssize _ left is the remaining byte length within the block address boundary size.
8. The address calculation array management method according to claim 1, wherein: in S5, the remaining length o _ dssize _ left = S _ size _x + i _ dssize _ left-length within the final block address boundary size; wherein S _ size _ x is the sum of the block address boundary size lengths accumulated in the address array, and i _ dssize _ left is the remaining byte length within the block address boundary size.
9. The address calculation array management method according to claim 1, wherein: in S5, the final block address boundary size occupies a length o _ left _ len = size-o _ dssize _ left.
10. An address calculation array management system comprising a control unit, characterized in that: the control unit is used for executing the address calculation array management method of any one of claims 1-9 to realize calculation and addressing of jump addresses.
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| CN112565474A (en) * | 2019-09-25 | 2021-03-26 | 无锡江南计算技术研究所 | Batch data transmission method facing distributed shared SPM |
| CN113238977A (en) * | 2021-07-12 | 2021-08-10 | 深之蓝(天津)水下智能科技有限公司 | Data transmission method, device, system, electronic equipment and storage medium |
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| JPH0689230A (en) * | 1992-09-09 | 1994-03-29 | Nec Ibaraki Ltd | Array circuit for cache memory read data |
| US20120106287A1 (en) * | 2010-11-01 | 2012-05-03 | Telefonaktiebolaget L M Ericsson (Publ) | Memory Arrangement for Accessing Matrices |
| CN102508800A (en) * | 2011-09-30 | 2012-06-20 | 北京君正集成电路股份有限公司 | Transmission method and transmission system for two-dimension data block |
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