CN113238977A - Data transmission method, device, system, electronic equipment and storage medium - Google Patents
Data transmission method, device, system, electronic equipment and storage medium Download PDFInfo
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Abstract
The application provides a data transmission method, a device, a system, an electronic device and a storage medium, wherein the method comprises the following steps: the method comprises the steps of determining the number of data blocks to be transmitted in the external storage device, the initial position and the data length of each data block, reading an Nth data block in the external storage device into a first cache unit through a first DMA controller configured by a reading interface based on the initial position and the data length of the data block, sending the Nth data block to the external processing device through a second DMA controller configured by a sending interface after the reading is finished, reading an N +1 th data block in the external storage device into a second cache unit through the first DMA controller, and sending the N +1 th data block to the external processing device through the second DMA controller after the reading is finished. Therefore, the data transmission efficiency is higher and the time consumption is shorter when the N +1 th data block is read while the nth data block is transmitted compared with the method that the next data block is read after one data block is transmitted.
Description
Technical Field
The present application relates to the field of data transmission, and in particular, to a data transmission method, apparatus, system, electronic device, and storage medium.
Background
Currently, when driving an LCD (Liquid Crystal Display), an MCU (micro controller Unit) is usually used for driving control in order to reduce cost.
When the LCD needs to display specific images and words, a word stock needs to be generated, the word stock data is usually stored in an off-chip EEPROM (Electrically Erasable Programmable read only Memory) (for example, as shown in fig. 1), and when the LCD needs the word stock data, the MCU needs to read the word stock data in the EEPROM into an internal RAM (Random Access Memory) of the MCU first and then write the read word stock data into the LCD.
Because the data length of the word stock data is large, the MCU cannot read all the word stock data to the RAM at once, the word stock data needs to be divided into a plurality of data blocks to be read respectively, based on the fact that the MCU reads one data block firstly when reading the word stock data at present, then sends the data block to the LCD after carrying out data bit adjustment on the data block, and then reads the next data block until all the data blocks are read, the method consumes a long time.
Disclosure of Invention
In order to solve the technical problem that the data transmission consumes long time, the application provides a data transmission method, a device, a system, electronic equipment and a storage medium.
In a first aspect, the present application provides a data transmission method, which is applied to a microcontroller, where the microcontroller includes a read interface, a transmit interface, a first cache unit, and a second cache unit, the read interface is configured with a first DMA controller, the transmit interface is configured with a second DMA controller, and the method includes:
determining the number of data blocks to be transmitted in external storage equipment, and the starting position and the data length of each data block, wherein the data length of each data block is not more than the capacity of the first cache unit and not more than the capacity of the second cache unit;
reading an Nth data block in an external storage device into the first cache unit through the first DMA controller, wherein N is an integer greater than 0;
after the Nth data block is read into the first cache unit, the Nth data block is sent to external processing equipment through the second DMA controller, and the (N + 1) th data block in external storage equipment is read into the second cache unit through the first DMA controller;
and after the N +1 th data block is read into the second cache unit, the N +1 th data block is sent to external equipment through the second DMA controller.
As a possible implementation manner, the capacity of the first cache unit is consistent with the capacity of the second cache unit, and the method further includes:
before a first data block in external storage equipment is read into the first cache unit or the second cache unit through the first DMA controller, the number of the data blocks to be transmitted in the external storage equipment, and the initial position and the data length of each data block to be transmitted are determined based on the initial position and the data length corresponding to the data to be transmitted in the external storage equipment and the capacity of the first cache unit or the second cache unit.
As a possible implementation, the method further includes:
before the Nth data block in the external storage device is read into the first cache unit through the first DMA controller, judging whether all data blocks to be transmitted in the external storage device are transmitted completely or not based on the number of the data blocks to be transmitted in the external storage device;
if it is determined that all the data blocks to be transmitted in the external storage device are not completely transmitted, executing a step of reading an Nth data block in the external storage device into the first cache unit through the first DMA controller;
before the N +1 th data block in the external storage device is read into the second cache unit through the first DMA controller, whether all data blocks to be transmitted in the external storage device are transmitted completely is judged based on the number of the data blocks to be transmitted in the external storage device;
and if the data blocks to be transmitted in the external storage device are determined not to be transmitted completely, executing a step of reading the (N + 1) th data block in the external storage device into the second cache unit through the first DMA controller.
As a possible implementation manner, the reading, by the first DMA controller, the nth data block in the external storage device into the first cache unit includes:
determining the residual capacity of the first cache unit;
judging whether the residual capacity is smaller than the data length of the Nth data block or not;
if the residual capacity is determined to be not smaller than the data length of the Nth data block, reading the whole Nth data block into the first cache unit through the first DMA controller;
if the residual capacity is smaller than the data length of the Nth data block, reading the sub-data block with the data length consistent with the residual capacity in the Nth data block into the first cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the Nth data block into the first cache unit through the first DMA controller after the sub-data block is read into the first cache unit.
As a possible implementation manner, the reading, by the first DMA controller, the sub data block of which the data length is consistent with the remaining capacity in the nth data block into the first cache unit includes:
taking the initial position corresponding to the Nth data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the Nth data block into the first cache unit through the first DMA controller according to the initial position and the data length of the sub data block.
As a possible implementation manner, the reading, by the first DMA controller, the (N + 1) th data block in the external storage device into the second cache unit includes:
determining the residual capacity of the second cache unit;
judging whether the residual capacity is smaller than the data length of the (N + 1) th data block;
if the residual capacity is determined to be not smaller than the data length of the (N + 1) th data block, reading the whole (N + 1) th data block into the second cache unit through the first DMA controller;
if the residual capacity is determined to be smaller than the data length of the (N + 1) th data block, reading the sub-data block with the data length consistent with the residual capacity in the (N + 1) th data block into the second cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the (N + 1) th data block into the second cache unit through the first DMA controller after the sub-data block is completely read into the second cache unit.
As a possible implementation manner, the reading, by the first DMA controller, a sub data block in the N +1 th data block, where a data length of the sub data block is consistent with the remaining capacity, into the second cache unit includes:
taking the initial position corresponding to the (N + 1) th data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the (N + 1) th data block into the second cache unit according to the initial position and the data length of the sub data block by the first DMA controller.
In a second aspect, an embodiment of the present application further provides a data transmission device, which is applied to a microcontroller, where the microcontroller includes a read interface, a send interface, a first cache unit, and a second cache unit, the read interface is configured with a first DMA controller, the send interface is configured with a second DMA controller, and the device includes:
the determining module is used for determining the number of data blocks to be transmitted in the external storage device, and the starting position and the data length of each data block, wherein the data length of each data block is not greater than the capacity of the first cache unit and not greater than the capacity of the second cache unit;
the reading control module is used for reading an Nth data block in external storage equipment into the first cache unit through the first DMA controller, wherein N is an integer larger than 0;
the sending control module is used for sending the Nth data block to external processing equipment through the second DMA controller after the Nth data block is read into the first cache unit;
the read control module is further configured to read an N +1 th data block in an external storage device into the second cache unit through the first DMA controller after the nth data block is completely read into the first cache unit;
and the sending control module is further configured to send the (N + 1) th data block to an external processing device through the second DMA controller after the (N + 1) th data block is completely read into the second cache unit.
In a third aspect, an embodiment of the present application further provides a data transmission system, including an external storage device, a display device, and a microcontroller that implements the data transmission method of the first aspect;
the microcontroller is connected with the external storage device through the reading interface;
the microcontroller is connected with the display device through the sending interface.
In a fourth aspect, an embodiment of the present application further provides an electronic device, including: a processor and a memory, the processor being configured to execute a data transmission program stored in the memory to implement the data transmission method of the first aspect.
In a fifth aspect, this application further provides a storage medium storing one or more programs, where the one or more programs are executable by one or more processors to implement the data transmission method according to the first aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the data transmission method provided by the embodiment of the application is applied to a microcontroller, the number of data blocks to be transmitted in external storage equipment and the initial position and the data length of each data block are determined, based on the initial position and the data length of each data block, an Nth data block in the external storage equipment is read into a first cache unit through a first DMA controller configured by a reading interface, after the data blocks are read, the Nth data block is sent to external processing equipment through a second DMA controller configured by a sending interface, meanwhile, an N +1 data block in the external storage equipment is read into a second cache unit through the first DMA controller, and after the data blocks are read, the N +1 data block is sent to the external processing equipment through the second DMA controller. Therefore, the scheme can read the (N + 1) th data block while sending the (N) th data block, and compared with the method that the next data block is read after one data block is sent, the scheme has the advantages of higher data transmission efficiency and shorter time consumption.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram illustrating a data transmission system in accordance with an exemplary embodiment.
Fig. 2 is a schematic diagram illustrating another data transmission system in accordance with an example embodiment.
Fig. 3 is a flow chart illustrating a method of data transmission according to an example embodiment.
FIG. 4 is a schematic diagram illustrating a cache molecule in accordance with an exemplary embodiment.
FIG. 5 is a flow diagram illustrating a method for reading data by a first DMA controller in accordance with an exemplary embodiment.
Fig. 6 is a schematic diagram illustrating a data transmission apparatus according to an example embodiment.
Fig. 7 is a schematic diagram illustrating yet another data transmission system in accordance with an example embodiment.
FIG. 8 is a schematic diagram illustrating an electronic device in accordance with an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Currently, when driving the SPI serial LCD, the MCU is usually selected for driving control in order to reduce the cost.
When the LCD needs to display specific images and words, a word stock needs to be generated, and the word stock data (such as image data) required for generating the word stock is generally stored in the following manner:
the first mode is as follows: the word stock data is stored in the on-chip false of the MCU (e.g., as shown in fig. 1).
The second mode is as follows: the word bank data is stored in the MCU's off-chip EEPROM (e.g., as shown in fig. 2).
The advantage of adopting the first mode to save is that, when the LCD needs the word stock data, the MCU directly sends the word stock data to the LCD, and the step of reading the word stock data by the MCU is not available, but the disadvantage is that the internal storage space of the MCU is occupied, so that the program storage space becomes smaller.
The advantage of using the second mode for storage is that the internal storage space of the MCU is not occupied, but the disadvantage is that when the LCD needs the word library data, the MCU needs to read the word library data from the EEPROM to the internal RAM of the MCU and then write the word library data to the LCD, and the method is time-consuming.
For a higher resolution LCD, such as a 320 x 240 LCD, which is a monochrome screen, a picture has a size of 76.8 kbytes, or 153.6 kbytes if it is a 16-bit color screen. Although there is a large-capacity RAM MCU on the market, the larger the RAM, the higher the cost of the MCU, so in order to reduce the cost of the MCU, the second storage method is usually adopted to store the database data.
However, the memory capacity of the MCU with lower cost is usually smaller, usually 4k, 8k, and 16k, and the data length of the character data of the LCD is usually larger than the memory capacity of the MCU, for example, the size of a picture of a monochrome screen is 76.8 kbytes, so the MCU usually needs to perform block processing on the character data when processing the character data.
When the word stock data is stored in the second storage mode, the data transmission process corresponding to the MCU roughly comprises: the MCU reads a data block from the EEPROM, writes the read data block into the internal RAM, processes the data block (such as data bit adjustment, and the like), sends the processed data block to the video memory of the LCD, and repeats the steps until all data blocks of data to be transmitted in the EEPROM are transmitted.
Because the interfaces of most of the EEPROMs are the SPIs, the connection between the MCU and the EEPROMs and the connection between the MCU and the LCDs are the SPIs (the SPIs are abbreviations of the Serial Peripheral Interface and are high-speed, full-duplex, synchronous communication buses), so the MCU transmits data through the hardware SPIs in both the EEPROMs and the LCDs, but the SPI bus rate is very high, but the MCU often occupies the space facing the LCD with high resolution, and only the SPI is used to process the data.
In order to solve the technical problem of low transmission efficiency when the data transmission mode is adopted to transmit data with large data length, the invention provides a novel data transmission mode, a Direct Memory Access (DMA) mode of a hardware SPI is used, the characteristic that an MCU does not need to participate in the DMA transmission process is utilized, the data is processed in a blocking mode, and the processes of reading off-chip font data and writing font data into an LCD are processed in a mode of simultaneously reading in data and transmitting data.
Referring to fig. 3, a flowchart of a data transmission method according to an embodiment of the present invention is provided, where the method may be applied to a microcontroller MCU, and the microcontroller includes a read interface, a transmit interface, a first buffer unit, and a second buffer unit, where the read interface is configured with a first DMA controller, and the transmit interface is configured with a second DMA controller, where the DMA controllers are used to implement a DMA transmission mode of the interfaces.
As shown in fig. 3, the method provided by the embodiment of the present invention may include the following steps:
and S31, determining the number of data blocks to be transmitted in the external storage device, and the starting position and the data length of each data block, wherein the data length of each data block is not more than the capacity of the first cache unit and not more than the capacity of the second cache unit.
In the embodiment of the invention, the external storage device is connected with the microcontroller through the reading interface, the data to be transmitted is stored in the external storage device, and the MCU can transfer the bus control right to the first DMA controller when the first DMA controller reads the data block to be transmitted in the external processing device.
As one embodiment, the external storage device may be an EEPROM.
As an embodiment, the data length of the data to be transmitted in the external storage device is usually greater than the capacities of the first cache unit and the second cache unit, so when the data to be transmitted in the external storage device is read through the first DMA controller, block reading is required, that is, the data to be transmitted is divided into a plurality of data blocks to be transmitted and read respectively, and therefore, before the data to be transmitted in the external storage device is read through the first DMA controller, the number of the data blocks to be transmitted, which can be divided by the data to be transmitted, and the start position and the data length of each data block to be transmitted need to be determined first.
In the embodiment of the present invention, the number of data blocks to be transmitted in the external storage device, and the start position and the data length of each data block to be transmitted may be determined according to the start position and the data length of the data to be transmitted in the external storage device, and the capacity of the first cache unit and/or the capacity of the second cache unit.
In order to ensure that the data block can be successfully read into the first buffer unit or the second buffer unit, it is preferable that the length of the data block is not greater than the capacity of the first buffer unit and not greater than the capacity of the second buffer unit.
As an embodiment, if the capacities of the first buffer unit and the second buffer unit are consistent, the following formula may be adopted to calculate the number of data blocks to be transmitted:
SIZE（BLOCK）=N/SIZE（RAM）
the value obtained by rounding up size (block) represents the number of data blocks to be transmitted, N represents the data length of the data to be transmitted, and size (ram) represents the capacity of the first cache unit and the capacity of the second cache unit.
Further, the data length of each data block to be transmitted may be determined in the following manner:
if the value of size (block) is an integer, the data length of each data block to be transmitted is size (ram), if the value of size (block) is not an integer, the data length of the data blocks to be transmitted except the last data block to be transmitted is size (ram), and the length of the last data block to be transmitted is the remainder of N/size (ram), namely N% size (ram), and the remainder is smaller than size (ram).
Further, the starting position of each data block to be transmitted may be determined in the following manner:
the starting position of the data to be transmitted (referred to as start for convenience of description) is used as the starting position of the first data block to be transmitted, and then the other data blocks to be transmitted are calculated according to the following formula:
the start position = the start position of the last data block to be transmitted + the data length of the last data block to be transmitted.
For example, the start position of the second data block to be transmitted is start + size (ram), the start position of the third data block to be transmitted is start + size (ram), and so on, the start positions of all the data blocks to be transmitted can be determined. After the start position and the data length of the data block to be transmitted are determined, a data table containing the start position and the data length of each data block to be transmitted can be generated, so that the first DMA controller can read the data block to be transmitted in the external storage device according to the data table.
Of course, if the capacity of the first cache unit is not consistent with the capacity of the second cache unit, it is only required to ensure that the data length of the data block to be read into the first cache unit is not greater than the capacity of the first cache unit, and the data length of the data block to be read into the second cache unit is not greater than the capacity of the second cache unit.
And S32, reading the Nth data block in the external storage device into the first buffer unit through the first DMA controller based on the starting position and the data length of the data block, wherein N is an integer larger than 0.
The nth data block is the nth data block to be transmitted in the external storage device, wherein N is an integer greater than 0, and the value of N is not greater than the number of the data blocks to be transmitted in the external storage device.
Specifically, when reading a certain data block to be transmitted, the first DMA controller may use a start address of the data block to be transmitted recorded in the data table as a source address of the data block to be transmitted, use an address of a cache unit (a first cache unit or a second cache unit) into which the data block to be transmitted is to be read as a destination address, and then read the data block to be transmitted based on the source address and the destination address.
Further, when N is a value greater than 1, before the nth data block in the external storage device is read into the first cache unit by the first DMA controller, whether all the data blocks to be transmitted in the external storage device are completely transmitted is determined based on the number of the data blocks to be transmitted in the external storage device obtained by previous calculation, if it is determined that all the data blocks to be transmitted in the external storage device are not completely transmitted, the step of reading the nth data block in the external storage device into the first cache unit by the first DMA controller is performed, and similarly, before the N +1 th data block in the external storage device is read into the second cache unit by the first DMA controller, whether all the data blocks to be transmitted in the external storage device are completely transmitted is also determined based on the number of the data blocks to be transmitted in the external storage device, if it is determined that all the data blocks to be transmitted in the external storage device are not completely transmitted, and reading the (N + 1) th data block in the external storage device into the second cache unit through the first DMA controller.
If it is determined that all the data blocks to be transmitted in the external storage device are transmitted, the first DMA controller releases the bus control right of the microcontroller and stops reading.
And S33, after the Nth data block is read into the first cache unit, the Nth data block is sent to external processing equipment through the second DMA controller, and the (N + 1) th data block in external storage equipment is read into the second cache unit through the first DMA controller.
The (N + 1) th data block is the (N + 1) th data block to be transmitted in the external storage device.
Therefore, in the embodiment of the invention, the nth data block can be transmitted and the (N + 1) th data block can be read simultaneously, so that the time required for processing the transmission data can be reduced.
As an embodiment, when the nth data block is sent to the external processing device, the destination address is a storage address of the external processing device, for example, if the external processing device is an LCD, the destination address is a display address of the LCD, and the source address is a read value of the nth data block in the first cache unit, where the read value represents a start position of the nth data block in the first cache unit, that is, a start position of the destination address when the nth data block is written in the first cache unit.
And S34, after the N +1 th data block is completely read into the second cache unit, sending the N +1 th data block to an external processing device through the second DMA controller.
As an embodiment, when the (N + 1) th data block is sent to the external processing device, the destination address is a storage address of the external processing device, for example, if the external processing device is an LCD, the destination address is a display address of the LCD, and the source address is a read value of the (N + 1) th data block in the first cache unit, where the read value represents a starting position of the (N + 1) th data block in the first cache unit, that is, a starting position of the destination address when the (N + 1) th data block is written into the first cache unit.
The data transmission method provided by the embodiment of the invention is applied to a microcontroller, wherein the microcontroller reads an nth data block in external storage equipment into a first cache unit through a first DMA controller configured by a reading interface, after the reading is finished, the nth data block is sent to external processing equipment through a second DMA controller configured by a sending interface, meanwhile, an N +1 data block in the external storage equipment is read into a second cache unit through the first DMA controller, and after the reading is finished, the N +1 data block is sent to the external processing equipment through the second DMA controller. Therefore, the scheme can read the (N + 1) th data block while sending the (N) th data block, and compared with the method that the next data block is read after one data block is sent, the scheme has the advantages of higher data transmission efficiency and shorter time consumption.
It can be known from the description of the above-mentioned manner for determining the data length of the data block to be transmitted, when the data length of the data block to be transmitted is not an integral multiple of the capacity of the cache unit (the first cache unit or the second cache unit), the data length of the data block to be transmitted is smaller than the capacity of the cache unit, so that after such data block is read into the cache unit, the cache unit is not full, that is, the cache unit still has the remaining capacity after the data block is written, as shown in fig. 4, for this case, when the other sub-data block is read into the cache unit that is not full by the first DMA controller next time, the data block can be split into two sub-data blocks to be written, wherein the data length of one sub-data block is consistent with the remaining capacity, and then the sub-data block is written into the cache unit first, after the sub-data block is successfully written, writing another sub-data block into the cache unit. Thereby fully utilizing the memory space of the microcontroller.
Taking the example of reading the nth data block in the external storage device into the first buffer unit through the first DMA controller, the reading process is described as follows, as shown in fig. 5, and may include the following steps:
and S51, determining the residual capacity of the first cache unit.
As an embodiment, the remaining capacity of the first cache unit may be determined by a read, which is used to record the starting position in the first cache unit of data read into the first cache unit from the external storage device, the read pointing to the first byte of the first cache unit at initialization.
The value of read can be calculated by read = read% size (ram), where size (ram) represents the capacity of the first buffer unit, and the value of read can be increased due to the increase of data read according to the above formula, and even if the capacity of the first buffer unit is exceeded, the value of read can be calculated by the above formula, and the remaining capacity of the first buffer unit can be calculated by size (ram) -read% size (ram).
S52, judging whether the residual capacity is smaller than the data length of the Nth data block, if not, executing S53, and if so, executing S54.
And S53, reading the whole Nth data block into a first cache unit through the first DMA controller.
In the embodiment of the present invention, when the nth data block is read into the first cache unit, the source address is the start position of the nth data block, the read data length is the data length of the nth data block, if the read% size (ram) value is 0, the start position of the target address is the first byte of the first cache unit, and if the read% size (ram) value is not 0, the start position of the target address is size (ram) -read% size (ram).
And S54, reading the sub-data blocks with the data length consistent with the residual capacity in the Nth data block into a first cache unit through a first DMA controller, and reading other sub-data blocks except the sub-data block in the Nth data block into the first cache unit through the first DMA controller after the sub-data blocks are read into the first cache unit.
As an embodiment, reading, by the first DMA controller, a sub data block of which the data length is consistent with the remaining capacity in the nth data block into the first cache unit may include:
and taking the initial position corresponding to the N-th data block as the initial position of the sub-data block, taking the residual capacity as the data length of the sub-data block, and then reading the sub-data block in the N-th data block into a first cache unit according to the initial position and the data length of the sub-data block through the first DMA controller.
Further, since the length of the nth data block is not greater than the capacity of the first buffer unit, if the remaining capacity of the first buffer unit is less than the data length of the nth data block, it means that read% size (ram) is not 0, so that when the sub-data block is read into the first buffer unit, the starting position of the target address is size (ram) -read% size (ram), and when other sub-data blocks are written into the first buffer unit, the starting position of the target address is the first byte of the first buffer unit.
Similarly, when writing other data blocks to be transmitted into the second cache unit, the similar process described above is also performed, except that the nth data block is replaced with other sub-data blocks, and the first cache unit is replaced with the second cache unit, for example, when the (N + 1) th data block in the external storage device is read into the second cache unit by the first DMA controller:
determining the residual capacity of the second cache unit;
judging whether the residual capacity is smaller than the data length of the (N + 1) th data block;
if the residual capacity is determined to be not smaller than the data length of the (N + 1) th data block, reading the whole (N + 1) th data block into a second cache unit through a first DMA controller;
if the residual capacity is smaller than the data length of the (N + 1) th data block, reading the sub data block with the data length consistent with the residual capacity in the (N + 1) th data block into a second cache unit through the first DMA controller, and reading other sub data blocks except the sub data block in the (N + 1) th data block into the second cache unit through the first DMA controller after the sub data block is read into the second cache unit.
For specific implementation, reference may be made to the descriptions of S51-S54, which are not described herein again.
In the embodiment of the invention, the data is read in the above way, so that the memory space of the microcontroller can be fully utilized, and the waste of the memory space is avoided.
Further, under the condition that the data to be processed is split into a plurality of data blocks to be processed and read into the cache unit, and the data blocks to be processed are read into the cache unit twice, the situation of data bit confusion may occur, so that before the data blocks to be transmitted are sent to the external processing device through the second DMA controller, data bit adjustment can be performed on the data blocks to be transmitted according to preset processing logic, so as to ensure the accuracy of the data.
Referring to fig. 6, a schematic diagram of a data transmission apparatus according to another embodiment of the present invention is provided, where the data transmission apparatus is applied to a microcontroller, the microcontroller includes a read interface, a transmit interface, a first buffer unit, and a second buffer unit, the read interface is configured with a first DMA controller, and the transmit interface is configured with a second DMA controller, and the apparatus includes:
a determining module 601, configured to determine the number of data blocks to be transmitted in an external storage device, and a start position and a data length of each data block, where the data length of the data block is not greater than a capacity of the first cache unit and not greater than a capacity of the second cache unit;
a read control module 602, configured to read an nth data block in an external storage device into the first cache unit through the first DMA controller based on a start position and a data length of the data block, where N is an integer greater than 0;
a sending control module 603, configured to send the nth data block to an external processing device through the second DMA controller after the nth data block is completely read into the first cache unit;
the read control module 602 is further configured to read, by the first DMA controller, an N +1 th data block in an external storage device into the second cache unit after the nth data block is completely read into the first cache unit;
the sending control module 603 is further configured to send the (N + 1) th data block to an external processing device through the second DMA controller after the (N + 1) th data block is completely read into the second cache unit.
As an embodiment, the capacity of the first cache unit is consistent with the capacity of the second cache unit, and the determining module 601 is specifically configured to:
and determining the number of the data blocks to be transmitted in the external storage device, and the starting position and the data length of each data block to be transmitted based on the starting position and the data length corresponding to the data to be transmitted in the external storage device and the capacity of the first cache unit or the second cache unit.
For one embodiment, the read control module 602 is further configured to:
before the Nth data block in the external storage device is read into the first cache unit through the first DMA controller, judging whether all data blocks to be transmitted in the external storage device are transmitted completely or not based on the number of the data blocks to be transmitted in the external storage device;
if it is determined that all the data blocks to be transmitted in the external storage device are not completely transmitted, executing a step of reading an Nth data block in the external storage device into the first cache unit through the first DMA controller;
before the N +1 th data block in the external storage device is read into the second cache unit through the first DMA controller, whether all data blocks to be transmitted in the external storage device are transmitted completely is judged based on the number of the data blocks to be transmitted in the external storage device;
and if the data blocks to be transmitted in the external storage device are determined not to be transmitted completely, executing a step of reading the (N + 1) th data block in the external storage device into the second cache unit through the first DMA controller.
As an embodiment, the reading, by the first DMA controller, the nth data block in the external storage device into the first cache unit includes:
determining the residual capacity of the first cache unit;
judging whether the residual capacity is smaller than the data length of the Nth data block or not;
if the residual capacity is determined to be not smaller than the data length of the Nth data block, reading the whole Nth data block into the first cache unit through the first DMA controller;
if the residual capacity is smaller than the data length of the Nth data block, reading the sub-data block with the data length consistent with the residual capacity in the Nth data block into the first cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the Nth data block into the first cache unit through the first DMA controller after the sub-data block is read into the first cache unit.
As an embodiment, the reading, by the first DMA controller, a sub data block in the nth data block, where a data length of the sub data block is consistent with the remaining capacity, into the first cache unit includes:
taking the initial position corresponding to the Nth data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the Nth data block into the first cache unit through the first DMA controller according to the initial position and the data length of the sub data block.
As an embodiment, the reading, by the first DMA controller, the (N + 1) th data block in the external storage device into the second cache unit includes:
determining the residual capacity of the second cache unit;
judging whether the residual capacity is smaller than the data length of the (N + 1) th data block;
if the residual capacity is determined to be not smaller than the data length of the (N + 1) th data block, reading the whole (N + 1) th data block into the second cache unit through the first DMA controller;
if the residual capacity is determined to be smaller than the data length of the (N + 1) th data block, reading the sub-data block with the data length consistent with the residual capacity in the (N + 1) th data block into the second cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the (N + 1) th data block into the second cache unit through the first DMA controller after the sub-data block is completely read into the second cache unit.
As an embodiment, the reading, by the first DMA controller, the sub data block of which the data length is consistent with the remaining capacity in the N +1 th data block into the second cache unit includes:
taking the initial position corresponding to the (N + 1) th data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the (N + 1) th data block into the second cache unit according to the initial position and the data length of the sub data block by the first DMA controller.
Referring to fig. 7, a data transmission system according to another embodiment of the present invention is provided, where the data transmission system is applied to a driving scenario of a display device, and as shown in fig. 7, the apparatus may include an external storage device, a display device, and a microcontroller that implements the data transmission method according to any of the foregoing embodiments, where the microcontroller is connected to the external storage device through a reading interface to read data in the external storage device; the microcontroller is connected with the display device through a sending interface to send data to the display device, wherein the reading interface and the sending interface are both SPI in a DMA mode, the external storage device can be EEPROM, and the display device can be LCD.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an electronic device according to another embodiment of the present application.
As shown in fig. 8, the electronic device provided in this embodiment includes: at least one processor 801, memory 802, at least one network interface 803, and other user interfaces 804. The various components in the electronic device 800 are coupled together by a bus system 805. It is understood that the bus system 805 is used to enable communications among the components connected. The bus system 805 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 805 in fig. 8.
The user interface 804 may include, among other things, a display, a keyboard, or a pointing device (e.g., a mouse, trackball, touch pad, or touch screen, among others.
It will be appreciated that the memory 802 in embodiments of the invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a Read-only memory (ROM), a programmable Read-only memory (PROM), an Erasable programmable Read-only memory (EPROM), an electrically Erasable programmable Read-only memory (EEPROM), or a flash memory. The volatile memory may be a Random Access Memory (RAM) which functions as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (statram, SRAM), dynamic random access memory (dynamic RAM, DRAM), Synchronous dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous dynamic random access memory (ddr Data Rate SDRAM, ddr SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct memory bus RAM (DRRAM). The memory 802 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In some embodiments, memory 802 stores elements, executable units or data structures, or a subset thereof, or an expanded set thereof as follows: an operating system 8021 and application programs 8022.
The operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is used for implementing various basic services and processing hardware-based tasks. The application program 8022 includes various application programs, such as a Media Player (Media Player), a Browser (Browser), and the like, for implementing various application services. A program implementing a method according to an embodiment of the present invention may be included in application program 8022.
In the embodiment of the present invention, the processor 801 is configured to execute the method steps provided by each method embodiment by calling the program or instruction stored in the memory 802, specifically, the program or instruction stored in the application 8022, and for example, includes:
determining the number of data blocks to be transmitted in external storage equipment, and the starting position and the data length of each data block, wherein the data length is not more than the capacity of the first cache unit and not more than the capacity of the second cache unit;
reading an Nth data block in an external storage device into the first cache unit through the first DMA controller based on the initial position and the data length of the data block, wherein N is an integer greater than 0;
after the Nth data block is read into the first cache unit, the Nth data block is sent to external processing equipment through the second DMA controller, and the (N + 1) th data block in external storage equipment is read into the second cache unit through the first DMA controller;
and after the N +1 th data block is read into the second cache unit, the N +1 th data block is sent to external processing equipment through the second DMA controller.
The methods disclosed in the embodiments of the present invention described above may be implemented in the processor 801 or implemented by the processor 801. The processor 801 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 801. The Processor 801 may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software elements in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in the memory 802, and the processor 801 reads the information in the memory 802, and combines the hardware to complete the steps of the method.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the Processing units may be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions of the present Application, or a combination thereof.
For a software implementation, the techniques herein may be implemented by means of units performing the functions herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
The embodiment of the invention also provides a storage medium (computer readable storage medium). The storage medium herein stores one or more programs. Among others, the storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.
When one or more programs in the storage medium are executable by one or more processors, the data transmission method executed on the electronic device side is realized.
The processor is used for executing the data transmission program stored in the memory to realize the following steps of the data transmission method executed on the electronic equipment side:
the microcontroller reads an Nth data block in external storage equipment into the first cache unit through the first DMA controller, wherein N is an integer greater than 0;
after the Nth data block is read into the first cache unit, the Nth data block is sent to external processing equipment through the second DMA controller, and the (N + 1) th data block in external storage equipment is read into the second cache unit through the first DMA controller;
and after the N +1 th data block is read into the second cache unit, the N +1 th data block is sent to external processing equipment through the second DMA controller.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (11)
1. A data transmission method is applied to a microcontroller, wherein the microcontroller comprises a reading interface, a sending interface, a first cache unit and a second cache unit, the reading interface is configured with a first DMA controller, the sending interface is configured with a second DMA controller, and the method comprises the following steps:
determining the number of data blocks to be transmitted in external storage equipment, and the starting position and the data length of each data block, wherein the data length of each data block is not more than the capacity of the first cache unit and not more than the capacity of the second cache unit;
reading an Nth data block in an external storage device into the first cache unit through the first DMA controller based on the initial position and the data length of the data block, wherein N is an integer greater than 0;
after the Nth data block is read into the first cache unit, the Nth data block is sent to external processing equipment through the second DMA controller, and the (N + 1) th data block in external storage equipment is read into the second cache unit through the first DMA controller;
and after the N +1 th data block is read into the second cache unit, the N +1 th data block is sent to external processing equipment through the second DMA controller.
2. The method of claim 1, wherein the capacity of the first buffer unit is consistent with the capacity of the second buffer unit, and wherein the determining the number of data blocks to be transmitted in the external storage device, and the start position and the data length of each data block comprises: and determining the number of data blocks to be transmitted in the external storage device, and the starting position and the data length of each data block based on the starting position and the data length corresponding to the data to be transmitted in the external storage device and the capacity of the first cache unit or the second cache unit.
3. The method of claim 1, further comprising:
before the Nth data block in the external storage device is read into the first cache unit through the first DMA controller, judging whether all data blocks to be transmitted in the external storage device are transmitted completely or not based on the number of the data blocks to be transmitted in the external storage device;
if it is determined that all the data blocks to be transmitted in the external storage device are not completely transmitted, executing a step of reading an Nth data block in the external storage device into the first cache unit through the first DMA controller;
before the N +1 th data block in the external storage device is read into the second cache unit through the first DMA controller, whether all data blocks to be transmitted in the external storage device are transmitted completely is judged based on the number of the data blocks to be transmitted in the external storage device;
and if the data blocks to be transmitted in the external storage device are determined not to be transmitted completely, executing a step of reading the (N + 1) th data block in the external storage device into the second cache unit through the first DMA controller.
4. The method of claim 1, wherein reading the nth data block in the external storage device into the first buffer unit through the first DMA controller comprises:
determining the residual capacity of the first cache unit;
judging whether the residual capacity is smaller than the data length of the Nth data block or not;
if the residual capacity is determined to be not smaller than the data length of the Nth data block, reading the whole Nth data block into the first cache unit through the first DMA controller;
if the residual capacity is smaller than the data length of the Nth data block, reading the sub-data block with the data length consistent with the residual capacity in the Nth data block into the first cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the Nth data block into the first cache unit through the first DMA controller after the sub-data block is read into the first cache unit.
5. The method as claimed in claim 4, wherein said reading, by the first DMA controller, the sub data block with the data length consistent with the remaining capacity in the nth data block into the first buffer unit includes:
taking the initial position corresponding to the Nth data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the Nth data block into the first cache unit through the first DMA controller according to the initial position and the data length of the sub data block.
6. The method of claim 1, wherein reading, by the first DMA controller, the (N + 1) th data block in the external storage device into the second buffer unit comprises:
determining the residual capacity of the second cache unit;
judging whether the residual capacity is smaller than the data length of the (N + 1) th data block;
if the residual capacity is determined to be not smaller than the data length of the (N + 1) th data block, reading the whole (N + 1) th data block into the second cache unit through the first DMA controller;
if the residual capacity is determined to be smaller than the data length of the (N + 1) th data block, reading the sub-data block with the data length consistent with the residual capacity in the (N + 1) th data block into the second cache unit through the first DMA controller, and reading other sub-data blocks except the sub-data block in the (N + 1) th data block into the second cache unit through the first DMA controller after the sub-data block is completely read into the second cache unit.
7. The method as claimed in claim 6, wherein the reading, by the first DMA controller, the sub data block with the data length consistent with the remaining capacity in the N +1 th data block into the second buffer unit includes:
taking the initial position corresponding to the (N + 1) th data block as the initial position of the sub data block, and taking the residual capacity as the data length of the sub data block;
and reading the sub data block in the (N + 1) th data block into the second cache unit according to the initial position and the data length of the sub data block by the first DMA controller.
8. A data transmission device is characterized in that the data transmission device is applied to a microcontroller, the microcontroller comprises a reading interface, a sending interface, a first cache unit and a second cache unit, the reading interface is provided with a first DMA controller, the sending interface is provided with a second DMA controller, and the device comprises:
the determining module is used for determining the number of data blocks to be transmitted in the external storage device, and the starting position and the data length of each data block, wherein the data length of each data block is not greater than the capacity of the first cache unit and not greater than the capacity of the second cache unit;
a read control module, configured to read an nth data block in an external storage device into the first cache unit through the first DMA controller based on a start position and a data length of the data block, where N is an integer greater than 0;
the sending control module is used for sending the Nth data block to external processing equipment through the second DMA controller after the Nth data block is read into the first cache unit;
the read control module is further configured to read an N +1 th data block in an external storage device into the second cache unit through the first DMA controller after the nth data block is completely read into the first cache unit;
and the sending control module is further configured to send the (N + 1) th data block to an external processing device through the second DMA controller after the (N + 1) th data block is completely read into the second cache unit.
9. A data transmission system comprising an external storage device, a display device and a microcontroller implementing the data transmission method of any one of claims 1 to 7;
the microcontroller is connected with the external storage device through the reading interface;
the microcontroller is connected with the display device through the sending interface.
10. An electronic device, comprising: a processor and a memory, the processor being configured to execute a data transfer program stored in the memory to implement the data transfer method of any one of claims 1-7.
11. A storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the data transmission method of any one of claims 1-7.
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