CN115079996A - Ultra-high-speed pipeline type five-point median filtering method based on full-parallel hardware logic - Google Patents
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Abstract
The invention discloses a super-high-speed pipelined five-point median filtering method based on full-parallel hardware logic, which comprises the following steps of: s1, performing five-point data caching on the input one-dimensional signed number sequence x (n), and outputting the complement form of the data in parallel at a specific time sequence; s2, preprocessing the parallel data output in the S1; s3, carrying out parallelization pairwise comparison on the preprocessed data in the S2 to obtain the size relationship between the data, and registering the comparison result into a corresponding size relationship register; s4, calculating redundancy according to the parallel data preprocessed in S2 and the value of the size relation register in S3
Outputting the median index number; and S5, selecting the index value of the corresponding index number in the original parallel data by utilizing the MUX to output according to the median index number calculated in the S4. According to the method, the median filtering result is output through fewer comparison times and clock delay, less hardware logic resources are consumed, and the calculation delay is lower.
Description
Technical Field
The invention relates to the technical field of ultrahigh-speed real-time signal processing, in particular to an ultrahigh-speed pipelined five-point median filtering method based on full-parallel hardware logic.
Background
The basic principle is that the value of a point in a digital image or a digital sequence is replaced by the median value of each point value in a neighborhood near the point, thereby eliminating an isolated noise point and achieving the filtering purpose.
In the process of implementing the median filtering algorithm by using hardware logic, calculating the median of each window is a core step, and the calculation of the median occupies most of the logic operation time, so that the efficiency of the median calculation determines the operation speed of the whole filtering circuit to a great extent. Currently, a median filtering scheme implemented based on an FPGA or an ASIC generally uses three or more stages of pipelines to perform block comparison on data in a window when calculating a median, and the scheme consumes a large amount of hardware logic resources and consumes a large number of clock cycles.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a superspeed pipeline type five-point median filtering method based on full parallel hardware logic, and the median filtering result can be output by fewer comparison times and less clock delay.
The technical scheme of the invention is as follows:
a super-high speed pipeline type five-point median filtering method based on full parallel hardware logic comprises the following steps:
s1, performing five-point data caching on the input one-dimensional signed number sequence x (n) through a data caching and shaping module, and transmitting the complement form of the data to the first-level pipeline module in parallel at a specific time sequence;
s2, preprocessing the parallel data output in S1 through the preprocessing logic of the one-level pipeline module, wherein the preprocessing comprises data format conversion and data low-order supplement;
s3, performing parallelization pairwise comparison on the preprocessed data in the S2 through a comparison unit of the first-level pipeline module to obtain the size relationship between each data and other data, and registering the comparison result into a corresponding size relationship register;
s4, calculating the redundancy according to the preprocessed parallel data in S2 and the values of ten size relation registers in S3 by the median index decision logic of the secondary pipeline module
Thereby judging the median position and outputting a median index number;
and S5, selecting the index value of the corresponding index number in the original parallel data by the MUX according to the median index number calculated in S4 by the median selection unit of the secondary pipeline module, and outputting the index value.
Preferably, in step S1, a register array with a bit width Nbits and a length 5 and a counter defined inside the data caching and shaping module are used to implement five-point data caching for the input one-dimensional signed number sequence x (n); the complement form of the data is output in parallel in a specific time sequence, and the specific method comprises the following steps: and performing original code to complement code combinational logic conversion on the input one-dimensional N bits signed number sequence, inputting the complement code after conversion to the register array for shift register on the rising edge of the current clock, simultaneously performing self-adding operation on the counter, repeating the process until the count value of the counter is 4, resetting the counter in the next clock cycle, raising the output effective signal out _ vld, maintaining a clock cycle, and completing one-time data transmission.
Preferably, the specific method of step S2 is as follows:
s21, when out _ vld of the data caching and shaping module is high, judging whether the five paths of parallel data have negative numbers, if yes, performing data format conversion, and then performing S22, if not, skipping data format conversion, and directly performing S22;
s22, performing low-order supplement operation on the data obtained in the step S21, namely supplementing 3bits of redundant bit index + 1' b1 to the low order of each path of data according to the data index number, and outputting five paths of parallel data by the preprocessing logic, wherein the width of the five paths of parallel data is N +3+1 bits.
Preferably, in step S21, the data format conversion method includes: carrying out logical OR operation on the sign bits of the five paths of parallel data; judging a logical OR operation result, if the logical OR operation result is '1', negating the sign bit of each path of data, and filling 1-bit data '0' in the highest bit as the sign bit; if "0", step S21 is skipped.
Preferably, in step S22, the method for appending the low bits of the data is: splicing a 3bits redundant bit 001 at the low bit of the data with the index number of 0; splicing 3bits redundant bits 010 at the low bits of the data with the index number of 1, and repeating the steps to obtain five paths of parallel data finally; and inputting the obtained five paths of parallel data into a comparison unit of the first-stage pipeline module as an output signal of the preprocessing logic.
Preferably, in S3, the parallelized pairwise comparison is performed on the data preprocessed in S2, and the specific comparison method is as follows:
according to the formula of carry look ahead calculation:
G n ＝A n .B n
P n ＝A n +B n
C n+1 ＝G n +P n ·C n
wherein A is n And B n Is the n-th bit logic value of addends A and B, P n And G n Is an intermediate variable, C n Is a carry value from low to home.
Assuming that the five paths of parallel data are respectively A, B, C, D, E and the corresponding index numbers are 0, 1,2,3 and 4, the parallel pairwise comparison is carried out on the five paths of parallel data, namely ten groups of data of A, B, A, C, B and C … … are parallelly calculated Cn, each group of data of Cn is registered to a corresponding large-small relation register, and the large-small relation registers are BT01, BT02 and BT12 … … respectively
Preferably, the step S4 includes the following sub-steps:
s41, classifying ten size relation registers according to whether the index values corresponding to the index numbers participate in the comparison, wherein the classification can be class 1-class 5;
s42, accumulating the register values in each class to obtain an accumulated value S n ；
S43, adding value S n Making a difference with a predetermined threshold value T to perform redundancy
Calculating;
s44, outputting an index number with redundancy of 0, namely an index number of a median;
preferably, the processing method of the register value in each class in step S42 is as follows: if x1 of the BT [ x1] [ x2] register in classn is not n, the register value is inverted, and if n, no operation is performed.
Preferably, the predetermined threshold T in step S43 is a median value of the index numbers, and is changed according to a change in the filter length, which is a constant 2 here.
The invention has the following characteristics and beneficial effects:
by adopting the technical scheme, the number of pipeline stages is compressed by optimizing a sorting strategy, the median filtering result can be output by fewer comparison times and less clock delay, and compared with the traditional median filtering implementation method, the method has the advantages of less consumed hardware logic resources, lower calculation delay and higher theoretical maximum clock frequency of more than 450 MHz.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flowchart illustrating the steps of a very high speed pipelined five-point median filtering method based on fully parallel hardware logic according to this embodiment.
Fig. 2 is a diagram of an architecture of the FPGA hardware logic based on the ultra-high-speed pipelined five-point median filtering method of the fully parallel hardware logic in this embodiment.
FIG. 3 is a table of register classifications of class 1-class 5 in the super-speed pipelined five-point median filtering method based on fully parallel hardware logic in the present embodiment.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The technical solution of the present invention is further specifically described below by using specific embodiments and with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
The embodiment provides a super-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, as shown in fig. 1, and described with reference to the FPGA hardware logic architecture diagram of fig. 2 and the register classification table of fig. 3, including the following steps:
s1, the data buffering and shaping module buffers the five-point data of the input one-dimensional signed number sequence x (n), and transmits the complement form of the data to the first-level pipeline module in parallel with a specific time sequence.
Specifically, in step S1, a register array with bit width Nbits and length 5 and a counter defined inside the data buffering and shaping module are used to implement five-point data buffering for an input one-dimensional signed number sequence x (n), and the complement form of the data is output in parallel in a specific time sequence.
It should be noted that the data that is transmitted in parallel to the first-stage pipeline module after the data complement is completed is the parallel data.
And S2, preprocessing the parallel data output in the S1 through the preprocessing logic of the one-stage pipeline module, wherein the preprocessing comprises data format conversion and data low-order supplement.
S21, when out _ vld of the data caching and shaping module is high, judging whether the five paths of parallel data have negative numbers, if yes, performing data format conversion, and then performing S22, if not, skipping data format conversion, and directly performing S22;
specifically, the data format conversion method includes: carrying out logical OR operation on the sign bits of the five paths of parallel data; judging a logical OR operation result, if the logical OR operation result is '1', negating the sign bit of each path of data, and filling 1-bit data '0' in the highest bit as the sign bit; if "0", step S21 is skipped.
S22, performing low-order supplement operation on the data obtained in the step S21, namely supplementing 3bits of redundant bit index + 1' b1 to the low order of each path of data according to the data index number, and outputting five paths of parallel data by the preprocessing logic, wherein the width of the five paths of parallel data is N +3+1 bits.
Specifically, the method for low-order data supplement is as follows: splicing a 3bits redundant bit 001 at the low bit of the data with the index number of 0; splicing 3bits redundant bits 010 at the low bits of the data with the index number of 1, and repeating the steps to obtain five paths of parallel data finally; and inputting the obtained five paths of parallel data serving as output signals of the preprocessing logic into a comparison unit of the first-stage pipeline module.
And S3, performing parallelization pairwise comparison on the preprocessed data in the S2 through a comparison unit of the first-level pipeline module to obtain the size relationship between each data and other data, and registering the comparison result into a corresponding size relationship register.
Specifically, according to the carry look ahead formula:
G n ＝A n .B n
P n ＝A n +B n
C n+1 ＝G n +P n ·C n
wherein A is n And B n Is the n-th bit logic value of addends A and B, P n And G n Is an intermediate variable, C n Is a carry value from low to home.
Assuming that the five paths of parallel data are respectively A, B, C, D, E and the corresponding index numbers are 0, 1,2,3 and 4, the parallel pairwise comparison is carried out on the five paths of parallel data, namely ten groups of data of A, B, A, C, B and C … … are parallelly calculated Cn, each group of data of Cn is registered to a corresponding large-small relation register, and the large-small relation registers are BT01, BT02 and BT12 … … respectively
It should be noted that the carry look ahead solution is an addition of two numbers, and therefore should be considered as A + (-B), i.e. a pairwise comparison of A and-B.
S4, calculating the redundancy according to the preprocessed parallel data in S2 and the values of ten size relation registers in S3 by the median index decision logic of the secondary pipeline module
Thereby judging the median position and outputting a median index number;
specifically, the step S4 includes the following sub-steps:
s41, classifying ten size relation registers according to whether the index value corresponding to the index number participates in the comparison, wherein the ten size relation registers can be classified into class 1-class 5;
further, the classification method is shown in fig. 3, and the classification principle is as follows: whether an index value corresponding to a certain index number participates in the comparison, if data with index of 0 participate in the data comparison process with index of 1,2,3 and 4 respectively, so that five registers BT01, BT02, BT03 and BT04 are classified into class1, and by analogy, class 2-5 is classified;
s42, accumulating the register values in each class to obtain an accumulated value S n ；
Further, the processing method for the register value in each class comprises the following steps: if x1 of the BT [ x1] [ x2] register in classn is not n, the register value is inverted, and if n, no operation is performed.
S43, adding value S n Making a difference with a predetermined threshold value T to perform redundancy
Calculation, the expression is as follows:
wherein, Sn corresponds to the accumulation result of each register value in classn, and the predetermined threshold value T is the median value of the index number and is changed according to the change of the filter length.
It is understood that in the embodiment, five-point median filtering is performed, so the predetermined threshold T is a constant of 2.
And S44, outputting the index number with the redundancy rate of 0, namely the index number of the median.
And S5, selecting the index value of the corresponding index number in the original parallel data by the MUX according to the median index number calculated in S4 by the median selection unit of the secondary pipeline module, and outputting the index value.
Specifically, the index number calculated in S44 is used as a strobe signal, five N bits of original data registered in the pipeline are used as data signals, and median selection and output are performed.
In the above technical solution, the problems that the delay is high and the consumption of logic resources is large when the median of each window is calculated by the existing median filtering algorithm based on the traditional sorting strategy are mainly solved. By adopting the technical scheme, the sorting strategy is optimized, the pipeline stage number is compressed, the median filtering result can be output through fewer comparison times and fewer clock delays, and the hardware logic deployment experiment verification of the method is performed through the FPGA.
It should be noted that the implementation method of the FPGA hardware logic architecture of this embodiment is the prior art, and therefore, the data caching and shaping module, the first-level pipeline module, and the second-level pipeline module are not specifically described in this embodiment.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments, including the components, without departing from the principles and spirit of the invention, and still fall within the scope of the invention.
Claims (9)
1. The ultra-high-speed pipelined five-point median filtering method based on the fully-parallel hardware logic is characterized by comprising the following steps of:
s1, performing five-point data caching on the input one-dimensional signed number sequence x (n) through a data caching and shaping module, and transmitting the complement form of the data to the first-level pipeline module in parallel at a specific time sequence;
s2, preprocessing the parallel data output in S1 through the preprocessing logic of the one-level pipeline module, wherein the preprocessing comprises data format conversion and data low-order supplement;
s3, performing parallelization pairwise comparison on the preprocessed data in the S2 through a comparison unit of the primary pipelining module, obtaining the size relationship between each data and other data, and registering the comparison result into a corresponding size relationship register;
s4, the median index decision logic of the secondary pipeline module is according to the pretreatment in S2Calculating redundancy by the processed parallel data and the values of the ten size relation registers in S3
Thereby judging the median position and outputting a median index number;
and S5, selecting the index value of the corresponding index number in the original parallel data by the MUX according to the median index number calculated in S4 by the median selection unit of the secondary pipeline module, and outputting the index value.
2. The method according to claim 1, wherein in step S1, five-point data buffering for the input one-dimensional signed number sequence x (N) is implemented by a register array with N bits of bit width and 5 length and a counter defined inside the data buffering and shaping module; the complement form of the data is output in parallel in a specific time sequence, and the specific method comprises the following steps: and performing original code to complement code combinational logic conversion on the input one-dimensional N bits signed number sequence, inputting the complement code after conversion to the register array for shift register on the rising edge of the current clock, simultaneously performing self-adding operation on the counter, repeating the process until the count value of the counter is 4, resetting the counter in the next clock cycle, raising the output effective signal out _ vld, maintaining a clock cycle, and completing one-time data transmission.
3. The very high speed pipelined five-point median filtering method based on fully parallel hardware logic according to claim 1, wherein the specific method of step S2 is as follows:
s21, when out _ vld of the data caching and shaping module is high, judging whether the five paths of parallel data have negative numbers, if yes, performing data format conversion, and then performing S22, if not, skipping data format conversion, and directly performing S22;
s22, performing low-order supplement operation on the data obtained in the step S21, namely supplementing 3bits of redundant bit index + 1' b1 to the low order of each path of data according to the data index number, and outputting five paths of parallel data by the preprocessing logic, wherein the width of the five paths of parallel data is N +3+1 bits.
4. The very high speed pipelined five-point median filtering method based on fully parallel hardware logic of claim 3, wherein in step S21, the data format conversion method is as follows: carrying out logical OR operation on the sign bits of the five paths of parallel data; judging a logical OR operation result, if the logical OR operation result is '1', negating the sign bit of each path of data, and filling 1-bit data '0' in the highest bit as the sign bit; if "0", step S21 is skipped.
5. The method for very high speed pipelined five-point median filtering based on fully parallel hardware logic of claim 3, wherein in step S22, the method for data low-order addition is: splicing a 3bits redundant bit 001 at the low bit of the data with the index number of 0; splicing 3bits redundant bits 010 at the low bits of the data with the index number of 1, and repeating the steps to obtain five paths of parallel data finally; and inputting the obtained five paths of parallel data into a comparison unit of the first-stage pipeline module as an output signal of the preprocessing logic.
6. The very high speed pipelined five-point median filtering method based on fully parallel hardware logic of claim 1, wherein in S3, the preprocessed data from S2 are compared in parallel, and the specific comparison method is as follows:
according to the formula of carry look ahead calculation:
G n ＝A n ·B n
P n ＝A n +B n
C n+1 ＝G n +P n ·C n
wherein A is n And B n Is the n-th bit logic value of addends A and B, P n And G n Is an intermediate variable, C n Is a carry value from low to home.
Assuming that the five paths of parallel data are respectively A, B, C, D, E, the corresponding index numbers are 0, 1,2,3 and 4, the parallel pairwise comparison is carried out on the five paths of parallel data, namely ten groups of data of A, B, A, C, B and C … … are parallelly calculated Cn, and each group of data of Cn is registered to a corresponding size relation register which is BT01, BT02 and BT12 … … respectively.
7. The fully parallel hardware logic based super speed pipelined five-point median filtering method according to claim 6, wherein said step S4 includes the sub-steps of:
s41, classifying ten size relation registers according to whether the index value corresponding to the index number participates in the comparison, wherein the ten size relation registers can be classified into class 1-class 5;
s42, accumulating the register values in each class to obtain an accumulated value S n ；
S43, adding value S n Making a difference with a predetermined threshold value T to perform redundancy
Calculating;
and S44, outputting the index number with the redundancy rate of 0, namely the index number of the median.
8. The method according to claim 7, wherein the processing method of the register value in each class in step S42 is as follows: if x1 of the BT [ x1] [ x2] register in classn is not n, the register value is inverted, and if n, no operation is performed.
9. The very high speed pipelined five-point median filtering method according to claim 7, wherein the predetermined threshold T in step S43 is the median of the index number, and is changed according to the change of the filter length, and is a constant 2.
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| CN116112580B (en) * | 2022-11-23 | 2024-04-26 | 国网智能电网研究院有限公司 | Hardware pipeline GTP data distribution method and device for power low-delay service |
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